74AUP1G02GF,132 [NXP]
74AUP1G02 - Low-power 2-input NOR-gate SON 6-Pin;![74AUP1G02GF,132](http://pdffile.icpdf.com/pdf2/p00228/img/icpdf/74AUP1G02GF-_1337172_icpdf.jpg)
型号: | 74AUP1G02GF,132 |
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描述: | 74AUP1G02 - Low-power 2-input NOR-gate SON 6-Pin 栅 光电二极管 逻辑集成电路 触发器 |
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74AUP1G02
Low-power 2-input NOR gate
Rev. 02 — 28 June 2006
Product data sheet
1. General description
The 74AUP1G02 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G02 provides the single 2-input NOR function.
2. Features
■ Wide supply voltage range from 0.8 V to 3.6 V
■ High noise immunity
■ Complies with JEDEC standards:
◆ JESD8-12 (0.8 V to 1.3 V)
◆ JESD8-11 (0.9 V to 1.65 V)
◆ JESD8-7 (1.2 V to 1.95 V)
◆ JESD8-5 (1.8 V to 2.7 V)
◆ JESD8-B (2.7 V to 3.6 V)
■ ESD protection:
◆ HBM JESD22-A114-C Class 3A. Exceeds 5000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Low static power consumption; ICC = 0.9 µA (maximum)
■ Latch-up performance exceeds 100 mA per JESD 78 Class II
■ Inputs accept voltages up to 3.6 V
■ Low noise overshoot and undershoot < 10 % of VCC
■ IOFF circuitry provides partial Power-down mode operation
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1G02GW
74AUP1G02GM
74AUP1G02GF
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
XSON6
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code
74AUP1G02GW
74AUP1G02GM
74AUP1G02GF
pB
pB
pB
5. Functional diagram
B
1
1
2
B
A
≥1
Y
4
Y
4
2
A
mna166
mna165
mna103
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
2 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
6. Pinning information
6.1 Pinning
74AUP1G02
74AUP1G02
B
A
1
2
3
6
5
4
V
CC
74AUP1G02
1
2
3
5
4
B
A
V
Y
B
A
1
2
3
6
5
4
V
CC
CC
n.c.
Y
n.c.
Y
GND
GND
GND
001aaf020
001aaf021
Transparent top view
Transparent top view
001aaf019
Fig 4. Pin configuration SOT353-1
(TSSOP5)
Fig 5. Pin configuration SOT886
(XSON6)
Fig 6. Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP5
XSON6
B
1
2
3
4
-
1
2
3
4
5
6
data input B
data input A
ground (0 V)
data output Y
not connected
supply voltage
A
GND
Y
n.c.
VCC
5
7. Functional description
Table 4.
Function table[1]
Input
Output
A
L
B
L
Y
H
L
L
L
L
H
L
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
3 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+4.6
−50
Unit
V
supply voltage
−0.5
input clamping current
input voltage
VI < 0 V
-
mA
V
[1]
[1]
VI
−0.5
+4.6
±50
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
-
mA
V
VO
Active mode and Power-down mode
VO = 0 V to VCC
−0.5
+4.6
±20
IO
output current
-
mA
mA
mA
°C
ICC
supply current
-
+50
−50
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
−65
+150
250
[2]
Tamb = −40 °C to +125 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Max
3.6
Unit
supply voltage
input voltage
output voltage
0.8
0
V
VI
3.6
V
VO
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
−40
0
+125
200
°C
ns/V
∆t/∆V
input transition rise and fall rate VCC = 0.8 V to 3.6 V
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
4 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-state input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
VOL
LOW-state output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.5
40
µA
µA
V
[1]
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
CI
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
0.8
1.7
-
-
pF
pF
CO
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
5 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C
VIH
HIGH-state input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
VOL
LOW-state output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
µA
µA
V
[1]
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
6 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
HIGH-state input voltage
VCC = 0.8 V
0.75 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.70 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.25 × VCC
0.30 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
VOL
LOW-state output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
±0.75
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
µA
µA
V
[1]
∆ICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
V
[1] One input at VCC − 0.6 V, other input at VCC or GND.
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
7 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8
Symbol
Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = 25 °C; CL = 5 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
see Figure 7
VCC = 0.8 V
-
17.0
5.1
3.7
3.0
2.4
2.2
-
ns
ns
ns
ns
ns
ns
propagation delay A or B to Y
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.5
1.6
1.3
1.0
1.0
10.8
6.7
5.3
3.9
3.4
Tamb = 25 °C; CL = 10 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
see Figure 7
VCC = 0.8 V
-
20.4
6.0
4.3
3.6
3.0
2.7
-
ns
ns
ns
ns
ns
ns
propagation delay A or B to Y
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.4
1.9
1.6
1.4
1.3
12.8
7.9
6.2
4.7
4.2
Tamb = 25 °C; CL = 15 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
see Figure 7
VCC = 0.8 V
-
23.9
6.8
4.8
4.0
3.4
3.2
-
ns
ns
ns
ns
ns
ns
propagation delay A or B to Y
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.4
2.3
1.9
1.7
1.6
14.6
8.9
7.0
5.4
4.8
Tamb = 25 °C; CL = 30 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
see Figure 7
VCC = 0.8 V
-
34.2
9.0
6.4
5.3
4.5
4.2
-
ns
ns
ns
ns
ns
ns
propagation delay A or B to Y
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.6
3.4
2.6
2.4
2.3
19.9
11.8
9.3
7.1
6.4
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
8 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8
Symbol
Tamb = 25 °C
CPD
Parameter
Conditions
Min
Typ [1]
Max
Unit
[2]
power dissipation capacitance f = 1 MHz; VI = GND to VCC
VCC = 0.8 V
-
-
-
-
-
-
2.6
2.7
2.9
3.1
3.5
4.1
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
CL = 5 pF
tPHL, tPLH HIGH-to-LOW and see Figure 7
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.1
1.4
1.1
0.9
0.8
12.1
7.8
6.2
4.6
4.0
2.1
1.4
1.1
0.9
0.8
13.4
8.6
6.9
5.1
4.4
ns
ns
ns
ns
ns
propagation delay
A or B to Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 10 pF
tPHL, tPLH HIGH-to-LOW and see Figure 7
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.2
1.7
1.5
1.2
1.2
14.3
9.2
7.3
5.6
5.0
2.2
1.7
1.5
1.2
1.2
15.8
10.2
8.1
ns
ns
ns
ns
ns
propagation delay
A or B to Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
6.2
5.5
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
9 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
CL = 15 pF
tPHL, tPLH HIGH-to-LOW and see Figure 7
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
3.1
2.0
1.7
1.5
1.4
16.4
10.4
8.3
3.1
2.0
1.7
1.5
1.4
18.1
11.5
9.2
ns
ns
ns
ns
ns
propagation delay
A or B to Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
6.3
7.0
5.7
6.3
CL = 30 pF
tPHL, tPLH HIGH-to-LOW and see Figure 7
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
4.1
2.9
2.3
2.1
2.1
22.4
13.9
11.1
8.5
4.1
2.9
2.3
2.1
2.1
24.7
15.3
12.3
9.4
ns
ns
ns
ns
ns
propagation delay
A or B to Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
7.7
8.5
12. Waveforms
V
I
V
A, B input
GND
M
t
t
PHL
PLH
V
OH
V
Y output
M
mna612
V
OL
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The data input (A or B) to output (Y) propagation delays
Table 10. Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
≤ 3.0 ns
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
10 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
V
V
EXT
CC
5 kΩ
V
V
O
I
PULSE
GENERATOR
DUT
R
C
R
L
T
L
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuitry for switching times
Table 11. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
11 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 9. Package outline SOT353-1 (TSSOP5)
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
12 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 10. Package outline SOT886 (XSON6)
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
13 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
L
L
1
e
6
5
4
e
1
e
1
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-03-11
05-04-06
SOT891
Fig 11. Package outline SOT891 (XSON6)
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
14 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
14. Abbreviations
Table 12: Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor Transistor Logic
15. Revision history
Table 13. Revision history
Document ID
74AUP1G02_2
Modifications:
Release date
20060628
Data sheet status
Change notice
Supersedes
Product data sheet
-
74AUP1G02_1
• ESD HBM and CPD values modified in Section 2, Table 8
• Added type number 74AUP1G02GF (XSON6/SOT891) package
74AUP1G02_1
20050718
Product data sheet
-
-
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
15 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.semiconductors.philips.com.
malfunction of a Philips Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. Philips Semiconductors accepts no liability for inclusion and/or use
of Philips Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Philips Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Philips Semiconductors
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — Philips Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.semiconductors.philips.com/profile/terms, including those
pertaining to warranty, intellectual property rights infringement and limitation
of liability, unless explicitly otherwise agreed to in writing by Philips
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, Philips Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Semiconductors. In case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — Philips Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — Philips Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74AUP1G02_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 28 June 2006
16 of 17
74AUP1G02
Philips Semiconductors
Low-power 2-input NOR gate
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com.
For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com.
Date of release: 28 June 2006
Document identifier: 74AUP1G02_2
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74AUP1G02GM-H
IC AUP/ULP/V SERIES, 2-INPUT NOR GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, Gate
NXP
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