74AUP1G14GS [NXP]
Low-power Schmitt trigger inverter; 低功耗施密特触发器逆变器
| 型号： | 74AUP1G14GS |
| 厂家： | 
NXP |
| 描述： | Low-power Schmitt trigger inverter |
| 文件： | 总24页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G14
Low-power Schmitt trigger inverter
Rev. 6 — 28 June 2012
Product data sheet
1. General description
The 74AUP1G14 provides a single inverting Schmitt trigger which accepts standard input
signals. It is capable of transforming slowly changing input signals into sharply defined,
jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT− is defined as the input
hysteresis voltage VH.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Applications
Wave and pulse shaper
Astable multivibrator
Monostable multivibrator
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1G14GW
74AUP1G14GM
74AUP1G14GF
74AUP1G14GN
74AUP1G14GS
74AUP1G14GX
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
XSON6
XSON6
XSON6
XSON6
X2SON5
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 × 1.0 × 0.35 mm
SOT1115
SOT1202
SOT1226
extremely thin small outline package; no leads;
6 terminals; body 1.0 × 1.0 × 0.35 mm
X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 × 0.8 × 0.35 mm
5. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1G14GW
74AUP1G14GM
74AUP1G14GF
74AUP1G14GN
74AUP1G14GS
74AUP1G14GX
pF
pF
pF
pF
pF
pF
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
A
Y
4
2
A
Y
2
4
mna025
mna023
mna024
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
74AUP1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 28 June 2012
2 of 24
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
7. Pinning information
7.1 Pinning
74AUP1G14
74AUP1G14
n.c.
A
1
2
3
6
5
4
V
CC
1
2
3
5
4
n.c.
A
V
Y
CC
n.c.
Y
GND
GND
001aaf122
Transparent top view
001aaf121
Fig 4. Pin configuration SOT353-1
Fig 5. Pin configuration SOT886
74AUP1G14
74AUP1G14
n.c.
A
1
2
5
4
V
Y
CC
n.c.
A
1
2
3
6
5
4
V
CC
3
GND
n.c.
Y
GND
001aaf123
aaa-003002
Transparent top view
Transparent top view
Fig 6. Pin configuration SOT891, SOT1115 and
SOT1202
Fig 7. Pin configuration SOT1226 (X2SON5)
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP5 and X2SON5 XSON6
n.c.
A
1
2
3
4
-
1
2
3
4
5
6
not connected
data input
GND
Y
ground (0 V)
data output
n.c.
VCC
not connected
supply voltage
5
74AUP1G14
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 28 June 2012
3 of 24
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
8. Functional description
Table 4.
Function table[1]
Input
Output
A
L
Y
H
L
H
[1] H = HIGH voltage level;
L = LOW voltage level.
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
−50
−0.5
-
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
VO
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
20
IO
output current
mA
mA
mA
°C
ICC
supply current
-
+50
-
IGND
Tstg
Ptot
ground current
−50
−65
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
0.8
0
Max
3.6
Unit
supply voltage
V
VI
input voltage
3.6
V
VO
output voltage
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
−40
+125
°C
74AUP1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 28 June 2012
4 of 24
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VOH
HIGH-level output voltage
VI = VT+ or VT−
IO = −20 μA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VT+ or VT−
VCC − 0.1
0.75 × VCC
1.11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output voltage
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
0.1
V
V
V
V
V
V
V
II
input leakage current
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current
0.2
additional power-off leakage VI or VO = 0 V to 3.6 V;
0.2
current
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
0.5
40
μA
μA
ΔICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
CI
input capacitance
output capacitance
VI = GND or VCC; VCC = 0 V to 3.6 V
VO = GND; VCC = 0 V
-
-
1.1
1.7
-
-
pF
pF
CO
Tamb = −40 °C to +85 °C
VOH
HIGH-level output voltage
VI = VT+ or VT−
IO = −20 μA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VCC − 0.1
0.7 × VCC
1.03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.30
1.97
1.85
2.67
2.55
74AUP1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 28 June 2012
5 of 24
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VT+ or VT−
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
0.5
V
V
V
V
V
V
V
II
input leakage current
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current
0.5
additional power-off leakage VI or VO = 0 V to 3.6 V;
0.6
current
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
μA
μA
ΔICC
additional supply current
HIGH-level output voltage
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
Tamb = −40 °C to +125 °C
VOH
VI = VT+ or VT−
IO = −20 μA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VT+ or VT−
VCC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.6 × VCC
0.93
-
-
-
-
-
-
-
1.17
1.77
1.67
2.40
2.30
VOL
LOW-level output voltage
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
0.75
μA
μA
IOFF
power-off leakage current
0.75
74AUP1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 28 June 2012
6 of 24
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
0.75
Unit
ΔIOFF
ICC
additional power-off leakage VI or VO = 0 V to 3.6 V;
current
-
-
μA
VCC = 0 V to 0.2 V
supply current
VI = GND or VCC; IO = 0 A;
-
-
-
-
1.4
75
μA
μA
VCC = 0.8 V to 3.6 V
ΔICC
additional supply current
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
12. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
CL = 5 pF
[2]
[2]
[2]
tpd
propagation delay A to Y; see Figure 8
VCC = 0.8 V
-
19.9
5.9
4.3
3.7
3.0
2.8
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
2.7
2.6
2.1
2.0
1.9
11.0
6.6
5.4
4.1
3.6
2.4
2.4
2.0
1.7
1.5
11.1
7.1
6.0
4.5
3.9
11.2
7.4
6.2
4.7
4.0
VCC = 1.4 V to 1.6 V
V
CC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 10 pF
tpd
propagation delay A to Y; see Figure 8
VCC = 0.8 V
-
23.4
6.8
5.0
4.2
3.6
3.3
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.9
2.8
2.7
2.3
2.1
12.7
7.7
6.2
4.8
4.3
2.8
2.6
2.5
2.1
2.0
12.8
8.2
6.7
5.2
4.5
12.9
8.6
7.1
5.5
4.7
CL = 15 pF
tpd
propagation delay A to Y; see Figure 8
VCC = 0.8 V
-
26.9
7.6
5.5
4.7
4.0
3.8
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.3
3.3
2.8
2.7
2.6
14.3
8.6
7.0
5.5
4.8
3.0
2.9
2.8
2.4
2.2
14.5
9.4
7.7
5.9
5.2
14.7
9.8
8.1
6.2
5.4
CL = 30 pF
74AUP1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 28 June 2012
7 of 24
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max Min
Max
Max
(85 °C) (125 °C)
[2]
tpd
propagation delay A to Y; see Figure 8
VCC = 0.8 V
-
37.3
9.8
7.1
6.0
5.2
4.8
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.0
3.7
3.6
3.5
3.3
18.7
11.2
9.1
6.9
6.1
3.9
3.8
3.6
3.2
3.1
19.6
12.3
10.0
7.5
20.0
12.9
10.6
7.9
7.1
7.4
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation fi = 1 MHz; VI = GND to VCC
[3]
capacitance
VCC = 0.8 V
-
-
-
-
-
-
2.6
2.7
2.9
3.1
3.7
4.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
[2] tpd is the same as tPLH and tPHL
[3] PD is used to determine the dynamic power dissipation (PD in μW).
.
.
C
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
13. Waveforms
V
I
V
A input
M
GND
t
t
PHL
PLH
V
OH
V
Y output
M
V
mna640
OL
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The data input (A) to output (Y) propagation delays
74AUP1G14
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 28 June 2012
8 of 24
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
Table 9.
Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Load circuitry for switching times
Table 10. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
14. Transfer characteristics
Table 11. Transfer characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol
Tamb = 25 °C
VT+
Parameter
Conditions
Min
Typ
Max
Unit
positive-going
threshold voltage
see Figure 10 and Figure 11
VCC = 0.8 V
0.30
0.53
0.74
0.91
1.37
1.88
-
-
-
-
-
-
0.60
0.90
1.11
1.29
1.77
2.29
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
74AUP1G14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 28 June 2012
9 of 24
74AUP1G14
NXP Semiconductors
Low-power Schmitt trigger inverter
Table 11. Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VT−
negative-going
threshold voltage
see Figure 10 and Figure 11
VCC = 0.8 V
0.10
0.26
0.39
0.47
0.69
0.88
-
-
-
-
-
-
0.60
0.65
0.75
0.84
1.04
1.24
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VH
hysteresis voltage
see Figure 10, Figure 11,
Figure 12 and Figure 13
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
0.07
0.08
0.18
0.27
0.53
0.79
-
-
-
-
-
-
0.50
0.46
0.56
0.66
0.92
1.31
V
V
V
V
V
V
Tamb = −40 °C to +85 °C
VT+
VT−
VH
positive-going
threshold voltage
see Figure 10 and Figure 11
VCC = 0.8 V
0.30
0.53
0.74
0.91
1.37
1.88
-
-
-
-
-
-
0.60
0.90
1.11
1.29
1.77
2.29
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
negative-going
threshold voltage
see Figure 10 and Figure 11
VCC = 0.8 V
0.10
0.26
0.39
0.47
0.69
0.88
-
-
-
-
-
-
0.60
0.65
0.75
0.84
1.04
1.24
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
hysteresis voltage
see Figure 10, Figure 11,
Figure 12 and Figure 13
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
0.07
0.08
0.18
0.27
0.53
0.79
-
-
-
-
-
-
0.50
0.46
0.56
0.66
0.92
1.31
V
V
V
V
V
V
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Table 11. Transfer characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VT+
VT−
VH
positive-going
threshold voltage
see Figure 10 and Figure 11
VCC = 0.8 V
0.30
0.53
0.74
0.91
1.37
1.88
-
-
-
-
-
-
0.62
0.92
1.13
1.31
1.80
2.32
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
negative-going
threshold voltage
see Figure 10 and Figure 11
VCC = 0.8 V
0.10
0.26
0.39
0.47
0.69
0.88
-
-
-
-
-
-
0.60
0.65
0.75
0.84
1.04
1.24
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
hysteresis voltage
see Figure 10, Figure 11,
Figure 12 and Figure 13
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
0.07
0.08
0.18
0.27
0.53
0.79
-
-
-
-
-
-
0.50
0.46
0.56
0.66
0.92
1.31
V
V
V
V
V
V
15. Waveforms transfer characteristics
V
T+
V
O
V
I
V
H
V
T−
V
O
V
I
mna208
V
H
V
V
T+
T−
mna207
VT+ and VT− limits at 70 % and 20 %.
Fig 10. Transfer characteristic
Fig 11. Definition of VT+, VT− and VH
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001aad691
240
I
CC
(μA)
160
80
0
0
0.4
0.8
1.2
1.6
2.0
V (V)
I
Fig 12. Typical transfer characteristics; VCC = 1.8 V
001aad692
1200
I
CC
(μA)
800
400
0
0
1.0
2.0
3.0
V (V)
I
Fig 13. Typical transfer characteristics; VCC = 3.0 V
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16. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Pad = fi × (tr × ICC(AV) + tf × ICC(AV)) × VCC where:
Pad = additional power dissipation (μW);
fi = input frequency (MHz);
tr = input rise time (ns); 10 % to 90 %;
tf = input fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (μA).
Average ICC differs with positive or negative input transitions, as shown in Figure 14.
An example of a relaxation circuit using the 74AUP1G14 is shown in Figure 15.
001aad027
0.3
ΔI
CC(AV)
(mA)
(1)
0.2
(2)
0.1
0
0.8
1.8
2.8
3.8
V
(V)
CC
(1) Positive-going edge
(2) Negative-going edge.
Fig 14. Average ICC as a function of VCC
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R
C
mna035
1
T
1
-- ----------------
f =
≈
a × RC
Average values for variable a are given in Table 12.
Fig 15. Relaxation oscillator
Table 12. Variable values
Supply voltage
1.1 V
Variable a
1.28
1.5 V
1.22
1.8 V
1.24
2.8 V
1.34
3.3 V
1.45
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17. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 16. Package outline SOT353-1 (TSSOP5)
74AUP1G14
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Low-power Schmitt trigger inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4x
(2)
L
L
1
e
6
5
4
e
1
e
1
6x
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
D
E
e
e
L
L
1
1
max 0.5 0.04 0.25 1.50 1.05
0.35 0.40
0.20 1.45 1.00 0.6 0.5 0.30 0.35
0.17 1.40 0.95 0.27 0.32
mm nom
min
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
sot886_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
MO-252
JEITA
04-07-22
12-01-05
SOT886
Fig 17. Package outline SOT886 (XSON6)
74AUP1G14
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Low-power Schmitt trigger inverter
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(1)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 18. Package outline SOT891 (XSON6)
74AUP1G14
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Low-power Schmitt trigger inverter
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
SOT1115
b
3
(2)
(4×)
1
2
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 0.95 1.05
0.35 0.40
0.15 0.90 1.00 0.55 0.3 0.30 0.35
0.12 0.85 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1115_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1115
Fig 19. Package outline SOT1115 (XSON6)
74AUP1G14
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Low-power Schmitt trigger inverter
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
b
3
(2)
1
2
(4×)
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
0.15 1.00 1.00 0.55 0.35 0.30 0.35
0.12 0.95 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1202_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1202
Fig 20. Package outline SOT1202 (XSON6)
74AUP1G14
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Low-power Schmitt trigger inverter
X2SON5: plastic thermal enhanced extremely thin small outline package; no leads;
5 terminals; body 0.8 x 0.8 x 0.35 mm
SOT1226
D
A
B
X
A
E
A
1
A
3
detail X
terminal 1
index area
e
C
v
C
C
A
B
b
y
y
C
1
w
1
2
terminal 1
index area
3
L
5
4
0
1 mm
scale
v
Dimensions
Unit
max 0.35 0.04 0.128 0.85 0.30 0.85 0.27
(1)
A
A
1
A
3
D
D
E
b
e
k
L
w
y
y
1
h
0.27
0.22 0.1 0.05 0.05 0.05
0.20 0.17
mm nom
min
0.80 0.25 0.80 0.22 0.48
0.040 0.75 0.20 0.75 0.17
Note
1. Dimension A is including plating thickness.
2. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1226_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
EIAJ
12-04-10
12-04-25
SOT1226
Fig 21. Package outline SOT1226 (X2SON5)
74AUP1G14
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18. Abbreviations
Table 13. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
19. Revision history
Table 14. Revision history
Document ID
74AUP1G14 v.6
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20120628
Product data sheet
-
74AUP1G14 v.5
• Added type number 74AUP1G14GX (SOT1226)
• Package outline drawing of SOT886 (Figure 17) modified.
74AUP1G14 v.5
Modifications:
20111128
Product data sheet
-
74AUP1G14 v.4
• Legal pages updated.
74AUP1G14 v.4
74AUP1G14 v.3
74AUP1G14 v.2
74AUP1G14 v.1
20100713
20090708
20060828
20050718
Product data sheet
-
-
-
-
74AUP1G14 v.3
74AUP1G14 v.2
74AUP1G14 v.1
-
Product data sheet
Product data sheet
Product data sheet
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20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
20.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Low-power Schmitt trigger inverter
22. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Transfer characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms transfer characteristics. . . . . . . . 11
Application information. . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
9
10
11
12
13
14
15
16
17
18
19
20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
20.1
20.2
20.3
20.4
21
22
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 June 2012
Document identifier: 74AUP1G14
相关型号：
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