74AUP1G175GM [NXP]
Low-power D-type flip-flop with reset; positive-edge trigger; 低功耗D类IP- FL佛罗里达州运带复位;正边沿触发
| 型号： | 74AUP1G175GM |
| 厂家： | 
NXP |
| 描述： | Low-power D-type flip-flop with reset; positive-edge trigger |
| 文件： | 总26页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G175
Low-power D-type flip-flop with reset; positive-edge trigger
Rev. 01.mm — 27 March 2006
Preliminary data sheet
1. General description
The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.The master reset
(MR) is an asynchronous active LOW input and operates independently of the clock input.
Information on the data input is transferred to the Q output on the LOW-to-HIGH transition
of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH
clock transition, for predictable operation.
2. Features
■ Wide supply voltage range from 0.8 V to 3.6 V
■ High noise immunity
■ Complies with JEDEC standards:
◆ JESD8-12 (0.8 V to 1.3 V)
◆ JESD8-11 (0.9 V to 1.65 V)
◆ JESD8-7 (1.2 V to 1.95 V)
◆ JESD8-5 (1.8 V to 2.7 V)
◆ JESD8-B (2.7 V to 3.6 V)
■ ESD protection:
◆ HBM JESD22-A114-C Class 3A. Exceeds 5000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Low static power consumption; ICC = 0.9 µA (maximum)
■ Latch-up performance exceeds 100 mA per JESD 78 Class II
■ Inputs accept voltages up to 3.6 V
■ Low noise overshoot and undershoot < 10 % of VCC
■ IOFF circuitry provides partial Power-down mode operation
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3 ns.
Symbol Parameter
Conditions
CL = 5 pF; RL = 1 MΩ;
CC = 0.8 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.1 V to 1.3 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.4 V to 1.6 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.65 V to 1.95 V
CL = 5 pF; RL = 1 MΩ;
CC = 2.3 V to 2.7 V
CL = 5 pF; RL = 1 MΩ;
CC = 3.0 V to 3.6 V
CL = 5 pF; RL = 1 MΩ;
CC = 0.8 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.1 V to 1.3 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.4 V to 1.6 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.65 V to 1.95 V
CL = 5 pF; RL = 1 MΩ;
CC = 2.3 V to 2.7 V
CL = 5 pF; RL = 1 MΩ;
CC = 3.0 V to 3.6 V
maximum input clock VCC = 3.0 V to 3.6 V;
Min
Typ
Max
Unit
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
-
21.1
-
ns
V
propagation delay
CP to Q
2.4
2.0
1.6
1.3
1.2
-
5.9
4.1
3.3
2.5
2.1
17.4
5.2
3.8
3.1
2.6
2.4
300
11.7
6.8
5.4
3.6
2.9
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
V
V
V
V
V
HIGH-to-LOW and
LOW-to-HIGH
propagation delay
MR to Q
V
2.4
2.3
1.8
1.8
1.6
190
9.7
4.9
4.9
3.6
3.1
-
V
V
V
V
V
fmax
frequency
CL = 30 pF
CI
input capacitance
-
-
-
1.5
2.0
2.7
-
-
-
pF
pF
pF
[1] [2]
[1] [2]
CPD
power dissipation
capacitance
VCC = 1.8 V; f = 1 MHz
VCC = 3.3 V; f = 1 MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC
.
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
2 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1G175GW
74AUP1G175GM
−40 °C to +125 °C
−40 °C to +125 °C
SC-88
plastic surface mounted package; 6 leads
SOT363
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
74AUP1G175GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
5. Marking
Table 3:
Marking
Type number
74AUP1G175GW
74AUP1G175GM
74AUP1G175GF
Marking code
aT
aT
aT
6. Functional diagram
6
MR
D
1
3
1
C1
4
3
FF
4
Q
1D
CP
6
R
001aaa469
001aaa468
Fig 1. Logic symbol
Fig 2. IEC logic symbol
CP
C
C
Q
C
C
C
C
C
C
C
C
D
MR
001aaa466
Fig 3. Logic diagram
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
3 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
7. Pinning information
7.1 Pinning
74AUP1G175
74AUP1G175
CP
GND
D
1
2
3
6
5
4
MR
CP
GND
D
1
2
3
6
5
4
MR
V
CC
V
CC
Q
Q
001aab657
001aaa467
Transparent top view
Fig 4. Pin configuration SOT363 (SC-88)
Fig 5. Pin configuration SOT886 (XSON6)
74AUP1G175
CP
GND
D
1
2
3
6
5
4
MR
V
CC
Q
001aae246
Transparent top view
Fig 6. Pin configuration SOT891 (XSON6)
7.2 Pin description
Table 4:
Pin description
Symbol
CP
Pin
1
Description
clock input (LOW-to-HIGH, edge-triggered)
ground (0 V)
GND
D
2
3
data input
Q
4
flip-flop output
VCC
MR
5
supply voltage
6
master reset input (active LOW)
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
4 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
8. Functional description
8.1 Function table
Table 5:
Function table[1]
Operating mode
Input
Output
MR
L
CP
X
D
X
h
l
Q
L
Reset (clear)
Load ‘1’
H
↑
H
L
Load ‘0’
H
↑
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑ = LOW-to-HIGH CP transition;
X = don’t care.
9. Limiting values
Table 6:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
-
Max
+4.6
−50
Unit
V
VCC
IIK
supply voltage
input clamping
current
VI < 0 V
mA
[1]
[1]
VI
input voltage
−0.5
+4.6
V
IOK
output clamping
current
VO < 0 V
-
−50
mA
VO
output voltage
active mode and
−0.5
+4.6
V
Power-down mode
IO
output current
VO = 0 V to VCC
-
-
±20
mA
mA
ICC
quiescent supply
current
+50
IGND
Tstg
Ptot
ground current
-
−50
mA
°C
storage temperature
−65
+150
250
[2]
total power
dissipation
Tamb = −40 °C to +125 °C
-
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are
observed.
[2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
5 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
10. Recommended operating conditions
Table 7:
Recommended operating conditions
Symbol Parameter
Conditions
Min
0.8
0
Max Unit
VCC
VI
supply voltage
input voltage
output voltage
3.6
3.6
VCC
3.6
V
V
V
V
VO
active mode
0
Power-down mode; VCC = 0 V
0
Tamb
ambient temperature
−40
0
+125 °C
200 ns/V
∆t/∆V
input transition rise and
fall rate
VCC = 0.8 V to 3.6 V
11. Static characteristics
Table 8:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-state input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
6 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.5
40
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current
VCC = 3.3 V
CI
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
0.8
1.7
-
-
pF
pF
CO
Tamb = −40 °C to +85 °C
VIH HIGH-state input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
7 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current CC = 3.3 V
V
Tamb = −40 °C to +125 °C
VIH HIGH-state input voltage
VCC = 0.8 V
0.75 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.70 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.25 × VCC
0.30 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
8 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
±0.75
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current CC = 3.3 V
V
[1] One input at VCC − 0.6 V, other input at VCC or GND.
12. Dynamic characteristics
Table 9:
Dynamic characteristics
GND = 0 V; see Figure 9
[1]
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C; CL = 5 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
see Figure 7
VCC = 0.8 V
-
21.1
5.9
4.1
3.3
2.5
2.1
-
ns
ns
ns
ns
ns
ns
propagation delay CP to Q
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
2.4
2.0
1.6
1.3
1.2
11.7
6.8
5.4
3.6
2.9
HIGH-to-LOW and
LOW-to-HIGH
propagation delay MR to Q
VCC = 0.8 V
-
17.4
5.2
3.8
3.1
2.6
2.4
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.4
2.3
1.8
1.8
1.6
9.7
4.9
4.9
3.6
3.1
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
9 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics …continued
GND = 0 V; see Figure 9
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock
frequency CP
see Figure 7
VCC = 0.8 V
-
-
-
-
-
-
50
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
200
345
435
550
615
Tamb = 25 °C; CL = 10 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
see Figure 7
VCC = 0.8 V
-
24.7
6.8
4.8
3.9
3.0
2.7
-
ns
ns
ns
ns
ns
ns
propagation delay CP to Q
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
2.6
2.3
2.1
1.7
1.6
13.3
7.9
6.1
4.3
3.6
HIGH-to-LOW and
LOW-to-HIGH
propagation delay MR to Q
VCC = 0.8 V
-
21.0
6.2
4.4
3.7
3.2
3.0
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
2.6
2.5
2.5
2.1
2.0
11.5
5.9
5.7
4.3
3.9
fmax
maximum input clock
frequency CP
VCC = 0.8 V
-
-
-
-
-
-
50
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
190
320
420
485
550
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
10 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics …continued
GND = 0 V; see Figure 9
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C; CL = 15 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
see Figure 7
VCC = 0.8 V
-
28.1
7.6
5.3
4.4
3.5
3.1
-
ns
ns
ns
ns
ns
ns
propagation delay CP to Q
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
3.0
2.7
2.3
2.1
2.0
14.8
8.7
6.8
5.0
4.3
HIGH-to-LOW and
LOW-to-HIGH
propagation delay MR to Q
VCC = 0.8 V
-
24.6
7.0
5.0
4.3
3.7
3.5
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
3.1
3.1
2.6
2.6
2.4
13.2
6.7
6.5
5.0
4.4
fmax
maximum input clock
frequency CP
VCC = 0.8 V
-
-
-
-
-
-
50
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
180
300
405
420
480
Tamb = 25 °C; CL = 30 pF
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
see Figure 7
VCC = 0.8 V
-
38.4
9.8
6.9
5.7
4.6
4.2
-
ns
ns
ns
ns
ns
ns
propagation delay CP to Q
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
3.6
3.3
3.1
3.0
2.8
19.5
11.2
8.8
6.4
5.7
HIGH-to-LOW and
LOW-to-HIGH
propagation delay MR to Q
VCC = 0.8 V
-
35.1
9.3
6.6
5.6
4.8
4.6
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.9
3.9
3.6
3.5
3.3
18.0
8.7
8.6
6.4
5.7
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
11 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics …continued
GND = 0 V; see Figure 9
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock
frequency CP
see Figure 7
VCC = 0.8 V
-
-
-
-
-
-
35
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
130
200
240
275
300
Tamb = 25 °C
tW
pulse width HIGH or LOW CP see Figure 7
VCC = 0.8 V
-
-
-
-
-
-
5.25
1.6
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
1.0
0.75
0.6
0.55
pulse width LOW MR
VCC = 0.8 V
-
-
-
-
-
-
9.0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
3.0
1.75
1.35
0.9
0.8
trem
removal time MR
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
−1.1
−2.0
−0.5
−0.9
−1.0
tsu(H)
set-up time HIGH D to CP
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.5
0.4
0.5
0.3
0.2
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
12 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics …continued
GND = 0 V; see Figure 9
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tsu(L)
set-up time LOW D to CP
see Figure 7
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
0.8
0.6
0.4
0.4
0.5
-
th
hold time D to CP
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
−0.7
−0.5
−0.5
−0.3
−0.4
[2] [3]
CPD
power dissipation capacitance f = 1 MHz
VCC = 0.8 V
-
-
-
-
-
-
1.8
1.9
1.9
2.0
2.3
2.7
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[3] The condition is VI = GND to VCC
.
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
13 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 10: Dynamic characteristics
GND = 0 V; see Figure 9
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
CL = 5 pF
tPHL, tPLH HIGH-to-LOW and see Figure 7
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.2
1.8
1.3
1.1
1.0
11.9
7.3
5.9
4.0
3.3
2.2
1.8
1.3
1.1
1.0
12.0
7.6
6.2
4.2
3.5
ns
ns
ns
ns
ns
propagation delay
CP to Q
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
HIGH-to-LOW and see Figure 8
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.2
2.1
1.7
1.5
1.3
10.0
6.4
5.4
4.0
3.3
2.2
2.1
1.7
1.5
1.3
12.0
6.6
5.6
4.0
3.6
ns
ns
ns
ns
ns
propagation delay
MR to Q
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
fmax
maximum input
clock frequency CP
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
170
310
400
490
550
CL = 10 pF
tPHL, tPLH HIGH-to-LOW and see Figure 7
LOW-to-HIGH
V CC = 1.1 V to 1.3 V
2.4
2.0
1.8
1.5
1.3
13.6
8.4
6.6
4.7
4.0
2.4
2.0
1.8
1.5
1.3
13.6
8.7
6.9
5.0
4.2
ns
ns
ns
ns
ns
propagation delay
CP to Q
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
HIGH-to-LOW and see Figure 8
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.6
2.4
2.2
1.9
1.8
11.7
7.6
6.3
4.7
4.1
2.6
2.4
2.2
1.9
1.8
13.6
7.8
6.3
4.9
4.3
ns
ns
ns
ns
ns
propagation delay
MR to Q
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
14 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 10: Dynamic characteristics …continued
GND = 0 V; see Figure 9
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
fmax
maximum input
see Figure 7
clock frequency CP
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
150
280
310
370
410
CL = 15 pF
tPHL, tPLH HIGH-to-LOW and see Figure 7
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.8
2.3
2.1
1.9
1.7
15.2
9.4
7.4
5.3
4.7
2.8
2.3
2.1
1.9
1.7
15.4
9.9
7.9
5.6
4.9
ns
ns
ns
ns
ns
propagation delay
CP to Q
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
HIGH-to-LOW and see Figure 8
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.9
2.6
2.5
2.2
2.1
13.5
8.6
7.2
5.4
4.8
2.9
2.6
2.5
2.2
2.1
15.2
9.1
7.4
5.5
5.0
ns
ns
ns
ns
ns
propagation delay
MR to Q
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
fmax
maximum input
clock frequency CP
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
120
190
240
300
320
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
15 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 10: Dynamic characteristics …continued
GND = 0 V; see Figure 9
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
CL = 30 pF
tPHL, tPLH HIGH-to-LOW and see Figure 7
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
3.4
3.2
2.9
2.6
2.5
20.6
12.4
9.6
3.4
3.2
2.9
2.6
2.5
21.0
13.0
10.2
7.3
ns
ns
ns
ns
ns
propagation delay
CP to Q
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
6.9
6.5
6.9
HIGH-to-LOW and see Figure 8
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
3.7
3.6
3.4
2.9
3.1
18.6
11.6
9.6
3.7
3.6
3.4
2.9
3.1
19.8
12.2
9.7
ns
ns
ns
ns
ns
propagation delay
MR to Q
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
7.2
7.2
6.4
6.9
fmax
maximum input
clock frequency CP
VCC = 0.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
70
120
150
190
200
CL = 5 pF, 10 pF, 15 pF, 30 pF
tW
pulse width
see Figure 7
HIGH or LOW CP
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
1.5
0.9
0.7
0.4
0.4
-
-
-
-
-
1.5
0.9
0.7
0.4
0.4
-
-
-
-
-
ns
ns
ns
ns
ns
pulse width LOW
MR
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 8
4.9
2.5
1.8
1.1
0.8
-
-
-
-
-
4.9
2.5
1.8
1.1
0.8
-
-
-
-
-
ns
ns
ns
ns
ns
trem
removal time MR
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
−1.2
−0.8
−0.7
−0.4
−0.2
-
-
-
-
-
−1.2
−0.8
−0.7
−0.4
−0.2
-
-
-
-
-
ns
ns
ns
ns
ns
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
16 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
Table 10: Dynamic characteristics …continued
GND = 0 V; see Figure 9
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
tsu(H)
set-up time HIGH
D to CP
see Figure 7
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
1.2
0.8
0.6
0.5
0.5
-
-
-
-
-
1.2
0.8
0.6
0.5
0.5
-
-
-
-
-
ns
ns
ns
ns
ns
tsu(L)
set-up time LOW
D to CP
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 7
1.7
1.1
0.9
0.9
0.9
-
-
-
-
-
1.7
1.1
0.9
0.9
0.9
-
-
-
-
-
ns
ns
ns
ns
ns
th
hold time D to CP
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.2
0
-
-
-
-
-
0.2
0
-
-
-
-
-
ns
ns
ns
ns
ns
0
0
0
0
0
0
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
17 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
13. Waveforms
V
I
V
M
D input
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
CP input
V
M
GND
t
W
t
t
PHL
PLH
V
OH
V
Q output
M
V
001aaa465
OL
Measurement points are given in Table 11.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the
D to CP set-up, the CP to D hold times and the maximum input clock frequency
Table 11: Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
18 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
V
I
V
M
MR input
GND
t
t
rem
W
V
I
CP input
Q output
V
M
GND
t
PHL
V
OH
V
M
V
OL
001aaa464
Measurement points are given in Table 12.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 8. The master reset (MR) input to output (Q) propagation delays, the master reset
pulse width and the MR to CP removal time
Table 12: Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
19 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
V
V
EXT
CC
5 kΩ
V
V
O
I
PULSE
GENERATOR
DUT
R
C
R
L
T
L
001aac521
Test data is given in Table 13.
Definitions for test circuit:
RL = Load resistance
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator
VEXT = External voltage for measuring switching times.
Fig 9. Load circuitry for switching times
Table 13: Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF,
5 kΩ or 1 MΩ open
GND
2 × VCC
15 pF and 30 pF
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times
and pulse width RL = 1 MΩ.
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
20 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
14. Package outline
Plastic surface mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
97-02-28
04-11-08
SOT363
SC-88
Fig 10. Package outline SOT363 (SC-88)
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
21 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 11. Package outline SOT886 (XSON6)
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
22 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
L
L
1
e
6
5
4
e
1
e
1
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-03-11
05-04-06
SOT891
Fig 12. Package outline SOT891 (XSON6)
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
23 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
15. Abbreviations
Table 14: Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor Transistor Logic
16. Revision history
Table 15: Revision history
Document ID
Release date Data sheet status
20060327 Preliminary data sheet
Change notice Doc. number
Supersedes
74AUP1G175_1
-
-
-
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
24 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
17. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
18. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
20. Trademarks
Notice — All referenced brands, product names, service names and
19. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74AUP1G175_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.xx — 27 March 2006
25 of 26
74AUP1G175
Philips Semiconductors
Low-power D-type flip-flop with reset; positive-edge trigger
22. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
9
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contact information . . . . . . . . . . . . . . . . . . . . 25
10
11
12
13
14
15
16
17
18
19
20
21
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 27 March 2006
Document number: 74AUP1G175_1
Published in The Netherlands
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