74AUP1G57_10_技术文档

74AUP1G57

Low-power configurable multiple function gate

Rev. 4 — 20 July 2010

Product data sheet

1. General description

The 74AUP1G57 provides configurable multiple functions. The output state is determined

by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,

NOR, XNOR, inverter, and buffer. All inputs can be connected to V_CCor GND.

This device ensures a very low static and dynamic power consumption across the entire

V

_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

The 74AUP1G57 has Schmitt trigger inputs making it capable of transforming slowly

changing input signals into sharply defined, jitter-free output signals.

The inputs switch at different points for positive and negative-going signals. The difference

between the positive voltage V_T+and the negative voltage V_T−is defined as the input

hysteresis voltage V_H.

2. Features and benefits

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

ESD protection:

HBM JESD22-A114F exceeds 5000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

Low static power consumption; I_CC= 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial power-down mode operation

Multiple package options

Specified from −40 °C to +85 °C and −40 °C to +125 °C

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

plastic surface-mounted package; 6 leads

Version

74AUP1G57GW

74AUP1G57GM

−40 °C to +125 °C

SC-88

SOT363

XSON6

plastic extremely thin small outline package; no leads; SOT886

6 terminals; body 1 × 1.45 × 0.5 mm

74AUP1G57GF

74AUP1G57GN

74AUP1G57GS

−40 °C to +125 °C

XSON6

plastic extremely thin small outline package; no leads; SOT891

6 terminals; body 1 × 1 × 0.5 mm

extremely thin small outline package; no leads;

6 terminals; body 0.9 × 1.0 × 0.35 mm

SOT1115

SOT1202

extremely thin small outline package; no leads;

6 terminals; body 1.0 × 1.0 × 0.35 mm

4. Marking

Table 2.

Marking

Type number

Marking code^[1]

74AUP1G57GW

74AUP1G57GM

74AUP1G57GF

74AUP1G57GN

74AUP1G57GS

aC

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

3

A

4

Y

1

B

6

C

001aab583

Fig 1. Logic symbol

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Low-power configurable multiple function gate

6. Pinning information

6.1 Pinning

74AUP1G57

B

GND

A

1

2

3

6

5

C

74AUP1G57

1

2

3

6

5

4

B

GND

A

C

B

GND

A

1

2

3

6

5

4

C

V

Y

CC

V

CC

V

CC

4

Y

001aab592

001aae058

Transparent top view

001aab591

Fig 2. Pin configuration SOT363

Fig 3. Pin configuration SOT886

Fig 4. Pin configuration SOT891,

SOT1115 and SOT1202

6.2 Pin description

Table 3.

Pin description

Symbol

1

Description

data input

B

GND

A

2

ground (0 V)

data input

3

Y

4

data output

supply voltage

data input

V_CC

C

5

6

7. Functional description

Table 4.

Function table^[1]

Input

Output

C

L

B

L

A

L

Y

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

[1] H = HIGH voltage level; L = LOW voltage level.

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Product data sheet

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Low-power configurable multiple function gate

7.1 Logic configurations

Table 5.

Function selection table

Logic function

Figure

2-input AND

see Figure 5

2-input AND with both inputs inverted

2-input NAND with inverted input

2-input OR with inverted input

2-input NOR

see Figure 8

see Figure 6 and Figure 7

see Figure 8

2-input NOR with both inputs inverted

2-input XNOR

see Figure 5

see Figure 9

Inverter

see Figure 10

Buffer

see Figure 11

V

CC

V

CC

B

C

B

Y

C

Y

B

1

2

3

6

5

4

C

Y

B

1

2

3

6

5

4

C

Y

B

C

B

Y

C

Y

001aab585

001aab584

Fig 5. 2-input AND gate or 2-input NOR gate with

both inputs inverted

Fig 6. 2-input NAND gate with input B inverted or

2-input OR gate with inverted C input

V

CC

V

CC

A

C

A

C

Y

1

2

3

6

5

4

C

Y

1

2

3

6

5

4

C

Y

A

C

A

C

A

001aab586

001aab587

Fig 7. 2-input NAND gate with input C inverted or

2-input OR gate with inverted A input

Fig 8. 2-input NOR gate or 2-input AND gate with

both inputs inverted

V

CC

V

CC

B

1

2

3

6

5

4

C

Y

1

2

3

6

5

4

B

C

Y

A

Y

A

Y

001aab588

001aab589

Fig 9. 2-input XNOR gate

Fig 10. Inverter

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Low-power configurable multiple function gate

V

CC

B

1

2

3

6

5

4

B

Y

001aab590

Fig 11. Buffer

8. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

−0.5

−50

−0.5

−50

−0.5

-

Max

+4.6

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+4.6

-

I_OK

output clamping current

output voltage

V_O< 0 V

mA

V

V_O

Active mode and Power-down mode

V_O= 0 V to V_CC

+4.6

±20

50

I_O

output current

mA

°C

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

−50

−65

-

storage temperature

total power dissipation

+150

250

[2]

T_amb= −40 °C to +125 °C

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SC-88 packages: above 87.5 °C the value of P_totderates linearly with 4.0 mW/K.

For XSON6 packages: above 118 °C the value of P_totderates linearly with 7.8 mW/K.

9. Recommended operating conditions

Table 7.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

Max

3.6

Unit

supply voltage

input voltage

output voltage

0.8

0

V

V_I

3.6

V

V_O

Active mode

0

V_CC

3.6

V

Power-down mode; V_CC= 0 V

0

V

T_amb

ambient temperature

−40

+125

°C

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Product data sheet

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Low-power configurable multiple function gate

10. Static characteristics

Table 8.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

T_amb= 25 °C

V_OH

HIGH-level output voltage

V_I= V_T+or V_T−

I_O= −20 μA; V_CC= 0.8 V to 3.6 V

I_O= −1.1 mA; V_CC= 1.1 V

I_O= −1.7 mA; V_CC= 1.4 V

I_O= −1.9 mA; V_CC= 1.65 V

I_O= −2.3 mA; V_CC= 2.3 V

I_O= −3.1 mA; V_CC= 2.3 V

I_O= −2.7 mA; V_CC= 3.0 V

I_O= −4.0 mA; V_CC= 3.0 V

V_I= V_T+or V_T−

V_CC− 0.1

0.75 × V_CC

1.11

-

V

1.32

2.05

1.9

2.72

2.6

V_OL

LOW-level output voltage

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

-

0.1

V

0.3 × V_CC

0.31

0.44

0.31

0.44

±0.1

±0.2

V

I_I

input leakage current

μA

I_OFF

ΔI_OFF

power-off leakage current

additional power-off leakage V_Ior V_O= 0 V to 3.6 V;

current

V_CC= 0 V to 0.2 V

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

V_CC= 0.8 V to 3.6 V

-

0.5

40

μA

ΔI_CC

additional supply current

V_I= V_CC− 0.6 V; I_O= 0 A;

V_CC= 3.3 V

C_I

input capacitance

output capacitance

V_I= GND or V_CC; V_CC= 0 V to 3.6 V

V_O= GND; V_CC= 0 V

-

1.1

1.7

-

pF

C_O

T_amb= −40 °C to +85 °C

V_OH

HIGH-level output voltage

V_I= V_T+or V_T−

I_O= −20 μA; V_CC= 0.8 V to 3.6 V

I_O= −1.1 mA; V_CC= 1.1 V

I_O= −1.7 mA; V_CC= 1.4 V

I_O= −1.9 mA; V_CC= 1.65 V

I_O= −2.3 mA; V_CC= 2.3 V

I_O= −3.1 mA; V_CC= 2.3 V

I_O= −2.7 mA; V_CC= 3.0 V

I_O= −4.0 mA; V_CC= 3.0 V

V_CC− 0.1

0.7 × V_CC

1.03

-

V

1.30

1.97

1.85

2.67

2.55

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Product data sheet

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Low-power configurable multiple function gate

Table 8.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_OL

LOW-level output voltage

V_I= V_T+or V_T−

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

-

0.1

V

0.3 × V_CC

0.37

0.35

0.33

0.45

0.33

0.45

±0.5

±0.6

V

I_I

input leakage current

μA

I_OFF

ΔI_OFF

power-off leakage current

additional power-off leakage V_Ior V_O= 0 V to 3.6 V;

current

V_CC= 0 V to 0.2 V

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

V_CC= 0.8 V to 3.6 V

-

0.9

50

μA

ΔI_CC

additional supply current

HIGH-level output voltage

V_I= V_CC− 0.6 V; I_O= 0 A;

V_CC= 3.3 V

T

_amb= −40 °C to +125 °C

V_OH

V_I= V_T+or V_T−

I_O= −20 μA; V_CC= 0.8 V to 3.6 V

I_O= −1.1 mA; V_CC= 1.1 V

I_O= −1.7 mA; V_CC= 1.4 V

I_O= −1.9 mA; V_CC= 1.65 V

I_O= −2.3 mA; V_CC= 2.3 V

I_O= −3.1 mA; V_CC= 2.3 V

I_O= −2.7 mA; V_CC= 3.0 V

I_O= −4.0 mA; V_CC= 3.0 V

V_I= V_T+or V_T−

V_CC− 0.11 -

-

V

0.6 × V_CC

0.93

-

1.17

1.77

1.67

2.40

2.30

V_OL

LOW-level output voltage

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

-

0.11

V

0.33 × V_CC

0.41

V

0.39

V

0.36

V

0.50

V

0.36

V

0.50

V

I_I

input leakage current

±0.75

μA

I_OFF

power-off leakage current

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Low-power configurable multiple function gate

Table 8.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

ΔI_OFFadditional power-off leakage V_Ior V_O= 0 V to 3.6 V;

-

±0.75

μA

current

V_CC= 0 V to 0.2 V

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

-

1.4

75

μA

V_CC= 0.8 V to 3.6 V

ΔI_CC

additional supply current

V_I= V_CC− 0.6 V; I_O= 0 A;

V_CC= 3.3 V

11. Dynamic characteristics

Table 9.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.

Symbol Parameter

Conditions

25 °C

−40 °C to +125 °C

Unit

Min Typ^[1]Max Min

Max

(85 °C) (125 °C)

C_L= 5 pF

[2]

t_pd

propagation delay A, B and C to Y;

see Figure 12

V_CC= 0.8 V

-

22.6

6.5

4.6

3.9

3.1

2.8

-

ns

V_CC= 1.1 V to 1.3 V

2.8

2.2

2.1

2.0

1.8

12.6 2.5

13.0

8.2

6.8

5.1

4.1

13.2

8.6

7.2

5.3

4.3

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

7.6

6.2

4.5

3.9

2.5

2.0

1.8

1.5

C_L= 10 pF

t_pd

propagation delay A, B and C to Y;

see Figure 12

V_CC= 0.8 V

-

26.1

7.3

5.2

4.5

3.7

3.4

-

ns

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

3.2

2.6

2.5

2.4

2.3

14.4 2.8

14.9

9.3

7.8

5.9

4.9

15.2

9.8

8.2

6.2

5.1

8.7

7.0

5.2

4.6

2.8

2.2

2.1

1.9

C_L= 15 pF

t_pd

propagation delay A, B and C to Y;

see Figure 12

V_CC= 0.8 V

-

31.6

8.0

5.7

4.9

4.1

3.8

-

ns

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

3.4

2.8

2.6

2.5

15.7 3.1

16.7

10.4

8.7

6.5

17.0

10.9

9.2

9.4

7.7

5.7

5.0

3.1

2.5

2.4

2.2

6.9

5.5

5.7

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Low-power configurable multiple function gate

Table 9.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 13.

Symbol Parameter

Conditions

25 °C

−40 °C to +125 °C

Unit

Min Typ^[1]Max Min

Max

(85 °C) (125 °C)

C_L= 30 pF

[2]

t_pd

propagation delay A, B and C to Y;

see Figure 12

V_CC= 0.8 V

-

37.8

10.4

7.4

-

ns

V_CC= 1.1 V to 1.3 V

4.6

3.6

3.5

3.4

3.2

20.9 3.9

12.2 3.8

21.8

13.4

11.1

8.3

22.3

14.1

11.8

8.8

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

6.2

9.9

7.4

6.6

3.1

2.8

5.2

4.9

7.0

7.4

C_L= 5 pF, 10 pF, 15 pF and 30 pF

C_PDpower dissipation f_i= 1 MHz; V_I= GND to V_CC

[3][4]

capacitance

V_CC= 0.8 V

-

2.6

2.8

2.9

3.1

3.7

4.3

-

pF

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] All typical values are measured at nominal V_CC

.

[2] t_pdis the same as t_PLHand t_PHL

.

[3] All specified values are the average typical values over all stated loads.

[4] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

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Product data sheet

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Low-power configurable multiple function gate

12. Waveforms

V

I

A, B, C input

GND

V

M

V

M

t

PLH

PHL

V

OH

V

M

Y output

M

V

OL

t

PLH

PHL

V

OH

Y output

V

M

V

OL

001aab593

Measurement points are given in Table 10.

V_OLand V_OHare typical output voltage drops that occur with the output load.

Fig 12. Input A, B and C to output Y propagation delay times

Table 10. Measurement points

Supply voltage

V_CC

Output

V_M

Input

V_M

V_I

t_r= t_f

0.8 V to 3.6 V

0.5 × V_CC

V_CC

≤ 3.0 ns

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Product data sheet

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74AUP1G57

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Low-power configurable multiple function gate

V

CC

V

EXT

5 kΩ

V

O

I

G

DUT

R

C

R

L

T

L

001aac521

Test data is given in Table 11.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 13. Test circuit for measuring switching times

Table 11. Test data

Supply voltage

V_CC

Load

C_L

V_EXT

[1]

R_L

t_PLH, t_PHL

open

t_PZH, t_PHZ

t_PZL, t_PLZ

0.8 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ

GND

2 × V_CC

[1] For measuring enable and disable times, R_L= 5 kΩ. For measuring propagation delays, set-up and hold times, and pulse width,

R_L= 1 MΩ.

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Product data sheet

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Low-power configurable multiple function gate

13. Transfer characteristics

Table 12. Transfer characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.

Symbol Parameter

Conditions

25 °C

−40 °C to +125 °C

Unit

Min Typ Max

Min

Max

(85 °C) (125 °C)

V_T+

V_T−

V_H

positive-going

threshold voltage Figure 15

see Figure 14 and

V_CC= 0.8 V

0.30

0.53

0.74

0.91

1.37

1.88

-

0.60

0.90

1.11

1.29

1.77

2.29

0.30

0.53

0.74

0.91

1.37

1.88

0.60

0.90

1.11

1.29

1.77

2.29

0.62

0.92

1.13

1.31

1.80

2.32

V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

negative-going

threshold voltage Figure 15

see Figure 14 and

V_CC= 0.8 V

0.10

0.26

0.39

0.47

0.69

0.88

-

0.60

0.65

0.75

0.84

1.04

1.24

0.10

0.26

0.39

0.47

0.69

0.88

0.60

0.65

0.75

0.84

1.04

1.24

0.60

0.65

0.75

0.84

1.04

1.24

V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

hysteresis voltage (V_T+− V_T−); see Figure 14,

Figure 15, Figure 16 and

Figure 17

V_CC= 0.8 V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

0.07

0.08

0.18

0.27

0.53

0.79

-

0.50

0.46

0.56

0.66

0.92

1.31

0.07

0.08

0.18

0.27

0.53

0.79

0.50

0.46

0.56

0.66

0.92

1.31

0.50

0.46

0.56

0.66

0.92

1.31

V

14. Waveform transfer characteristics

V

O

T+

V

I

V

H

V

T−

V

O

V

I

V

H

mna208

V

T+

T−

mna207

V_T+and V_T−limits at 70 % and 20 %.

Fig 14. Transfer characteristic

Fig 15. Definition of V_T+, V_T−, and V_H

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Product data sheet

Rev. 4 — 20 July 2010

12 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

001aad691

240

I

CC

(μA)

160

80

0

0.4

0.8

1.2

1.6

2.0

V (V)

I

Fig 16. Typical transfer characteristics; V_CC= 1.8 V

001aad692

1200

I

CC

(μA)

800

400

0

1.0

2.0

3.0

V (V)

I

Fig 17. Typical transfer characteristics; V_CC= 3.0 V

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Product data sheet

Rev. 4 — 20 July 2010

13 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

15. Package outline

Plastic surface-mounted package; 6 leads

SOT363

D

B

E

A

X

y

H

v

M

A

E

6

5

4

Q

pin 1

index

A

1

2

3

c

e

1

b

L

p

w

M B

p

e

detail X

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

1

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

p

1

E

max

0.30

0.20

1.1

0.8

0.25

0.10

2.2

1.8

1.35

1.15

2.2

2.0

0.45

0.15

0.25

0.15

mm

0.1

1.3

0.65

0.2

0.1

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

04-11-08

06-03-16

SOT363

SC-88

Fig 18. Package outline SOT363 (SC-88)

74AUP1G57

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Product data sheet

Rev. 4 — 20 July 2010

14 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

SOT886

b

1

2

3

4×

(2)

L

1

e

6

5

4

e

1

e

1

6×

A

(2)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

1

UNIT

b

D

E

e

L

1

max max

0.25

0.17

1.5

1.4

1.05

0.95

0.35 0.40

0.27 0.32

mm

0.5 0.04

0.6

0.5

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

04-07-15

04-07-22

SOT886

MO-252

Fig 19. Package outline SOT886 (XSON6)

74AUP1G57

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Product data sheet

Rev. 4 — 20 July 2010

15 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm

SOT891

b

1

2

3

4×

(1)

L

1

e

6

5

4

e

1

e

1

6×

A

(1)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

1

UNIT

b

D

E

e

L

1

max max

0.20 1.05 1.05

0.12 0.95 0.95

0.35 0.40

0.27 0.32

mm

0.5 0.04

0.55 0.35

Note

1. Can be visible in some manufacturing processes.

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

05-04-06

07-05-15

SOT891

Fig 20. Package outline SOT891 (XSON6)

74AUP1G57

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Product data sheet

Rev. 4 — 20 July 2010

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74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

XSON6: extremely thin small outline package; no leads;

6 terminals; body 0.9 x 1.0 x 0.35 mm

SOT1115

b

3

(2)

(4×)

1

2

L

1

e

6

5

4

e

1

e

1

(2)

(6×)

A

1

A

D

E

terminal 1

index area

0

L

0.5

scale

1 mm

Dimensions

Unit

(1)

A

1

b

D

E

e

1

L

1

max 0.35 0.04 0.20 0.95 1.05

0.35 0.40

0.15 0.90 1.00 0.55 0.3 0.30 0.35

0.12 0.85 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1115_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

10-04-02

10-04-07

SOT1115

Fig 21. Package outline SOT1115 (XSON6)

74AUP1G57

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Product data sheet

Rev. 4 — 20 July 2010

17 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

XSON6: extremely thin small outline package; no leads;

6 terminals; body 1.0 x 1.0 x 0.35 mm

SOT1202

b

3

(2)

1

2

(4×)

L

1

e

6

5

4

e

1

e

1

(2)

(6×)

A

1

A

D

E

terminal 1

index area

0

L

0.5

1 mm

scale

Dimensions

Unit

(1)

A

1

b

D

E

e

1

L

1

max 0.35 0.04 0.20 1.05 1.05

0.35 0.40

0.15 1.00 1.00 0.55 0.35 0.30 0.35

0.12 0.95 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1202_po

References

Outline

version

European

Issue date

projection

IEC

JEDEC

JEITA

10-04-02

10-04-06

SOT1202

Fig 22. Package outline SOT1202 (XSON6)

74AUP1G57

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Product data sheet

Rev. 4 — 20 July 2010

18 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

16. Abbreviations

Table 13. Abbreviations

Acronym

CDM

DUT

Description

Charged Device Model

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

ESD

HBM

MM

17. Revision history

Table 14. Revision history

Document ID

74AUP1G57 v.4

Modifications:

Release date

20100720

Data sheet status

Change notice

Supersedes

Product data sheet

-

74AUP1G57 v.3

• Added type number 74AUP1G57GN (SOT1115/XSON6 package).

• Added type number 74AUP1G57GS (SOT1202/XSON6 package).

74AUP1G57 v.3

74AUP1G57 v.2

74AUP1G57 v.1

20090622

20090323

20061123

Product data sheet

-

74AUP1G57 v.2

74AUP1G57 v.1

-

74AUP1G57

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Product data sheet

Rev. 4 — 20 July 2010

19 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

18.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

74AUP1G57

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Product data sheet

Rev. 4 — 20 July 2010

20 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74AUP1G57

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Product data sheet

Rev. 4 — 20 July 2010

21 of 22

74AUP1G57

NXP Semiconductors

Low-power configurable multiple function gate

20. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 3

Logic configurations . . . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Transfer characteristics . . . . . . . . . . . . . . . . . 12

Waveform transfer characteristics. . . . . . . . . 12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19

9

10

11

12

13

14

15

16

17

18

Legal information. . . . . . . . . . . . . . . . . . . . . . . 20

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

18.1

18.2

18.3

18.4

19

20

Contact information. . . . . . . . . . . . . . . . . . . . . 21

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 20 July 2010

Document identifier: 74AUP1G57


型号：	74AUP1G57_10
厂家：	NXP
描述：	Low-power configurable multiple function gate 低功耗可配置多功能门
文件：	总22页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AUP1G57_10 [NXP]

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