74AUP1G58 [NXP]
Low-power configurable multiple function gate; 低功耗可配置多功能门
| 型号： | 74AUP1G58 |
| 厂家： | 
NXP |
| 描述： | Low-power configurable multiple function gate |
| 文件： | 总19页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G58
Low-power configurable multiple function gate
Rev. 03 — 22 June 2009
Product data sheet
1. General description
The 74AUP1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G58 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT− is defined as the input
hysteresis voltage VH.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I ESD protection:
N HBM JESD22-A114E exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
plastic surface-mounted package; 6 leads
Version
74AUP1G58GW
74AUP1G58GM
−40 °C to +125 °C
−40 °C to +125 °C
SC-88
SOT363
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
74AUP1G58GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1G58GW
74AUP1G58GM
74AUP1G58GF
aK
aK
aK
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
A
4
Y
1
B
6
C
001aab687
Fig 1. Logic symbol
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
2 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
74AUP1G58
74AUP1G58
B
GND
A
1
2
3
6
5
C
74AUP1G58
1
2
3
6
5
4
B
GND
A
C
B
GND
A
1
2
3
6
5
4
C
V
Y
CC
V
Y
CC
V
CC
4
Y
001aad698
001aad690
Transparent top view
Transparent top view
001aad697
Fig 2. Pin configuration SOT363
(SC-88)
Fig 3. Pin configuration SOT886
(XSON6)
Fig 4. Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Pin description
Pin
Symbol
Description
data input
B
1
2
3
4
5
6
GND
A
ground (0 V)
data input
Y
data output
supply voltage
data input
VCC
C
7. Functional description
Table 4.
Function table[1]
Input
Output
C
L
B
L
A
L
Y
L
L
L
H
L
H
L
L
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
L
H
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level.
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
3 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input NAND
see Figure 5
2-input NAND with both inputs inverted
2-input AND with inverted input
2-input NOR with inverted input
2-input OR
see Figure 8
see Figure 6 and Figure 7
see Figure 6 and Figure 7
see Figure 8
2-input OR with both inputs inverted
2-input XOR
see Figure 5
see Figure 9
Buffer
see Figure 10
Inverter
see Figure 11
V
CC
V
CC
B
C
B
Y
C
Y
B
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
B
C
B
Y
C
Y
001aab689
001aab688
Fig 5. 2-input NAND gate or 2-input OR with both
inputs inverted
Fig 6. 2-input AND gate with inverted B input or
2-input NOR gate with inverted C input
V
CC
V
CC
A
C
A
C
Y
Y
Y
Y
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
C
Y
A
C
A
A
C
A
001aab690
001aab691
Fig 7. 2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
Fig 8. 2-input OR gate or 2-input NAND gate with
both inputs inverted
V
CC
V
CC
B
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
B
C
A
Y
Y
A
Y
001aab692
001aab693
Fig 9. 2-input XOR gate
Fig 10. Buffer
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
4 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
V
CC
B
1
2
3
6
5
4
B
Y
Y
001aab694
Fig 11. Inverter
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
−50
−0.5
-
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
VO
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
±20
50
IO
output current
mA
mA
mA
°C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−50
−65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Max
3.6
Unit
supply voltage
input voltage
output voltage
0.8
0
V
VI
3.6
V
VO
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
−40
+125
°C
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
5 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VOH
HIGH-level output voltage
VI = VT+ or VT−
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VT+ or VT−
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current
additional power-off leakage VI or VO = 0 V to 3.6 V;
current
V
CC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
ICC
supply current
-
-
-
-
0.5
40
µA
µA
V
∆ICC
additional supply current
V
CI
input capacitance
output capacitance
VI = GND or VCC; VCC = 0 V to 3.6 V
VO = GND; VCC = 0 V
-
-
1.1
1.8
-
-
pF
pF
CO
Tamb = −40 °C to +85 °C
VOH
HIGH-level output voltage
VI = VT+ or VT−
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
6 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VT+ or VT−
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current
additional power-off leakage VI or VO = 0 V to 3.6 V;
current
V
CC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
ICC
supply current
-
-
-
-
0.9
50
µA
µA
V
∆ICC
additional supply current
V
Tamb = −40 °C to +125 °C
VOH HIGH-level output voltage
VI = VT+ or VT−
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VT+ or VT−
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
VOL
LOW-level output voltage
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
µA
µA
IOFF
power-off leakage current
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
7 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
∆IOFF additional power-off leakage VI or VO = 0 V to 3.6 V;
-
-
±0.75
µA
current
V
CC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
CC = 3.3 V
ICC
supply current
-
-
-
-
1.4
75
µA
µA
V
∆ICC
additional supply current
V
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
Conditions
25 °C
Min Typ[1] Max
−40 °C to +125 °C
Unit
Min
Max
Max
(85 °C) (125 °C)
CL = 5 pF
[2]
[2]
[2]
tpd
propagation delay A, B and C to Y;
see Figure 12
VCC = 0.8 V
-
22.8
6.6
4.8
4.0
3.2
2.9
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
2.8
2.4
2.1
2.0
1.9
12.9
7.6
6.3
4.6
3.9
2.6
2.4
2.0
1.8
1.6
13.1
8.3
6.9
5.1
4.2
13.3
8.6
7.3
5.4
4.4
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 10 pF
tpd
propagation delay A, B and C to Y;
see Figure 12
VCC = 0.8 V
-
26.4
7.4
5.4
4.5
3.8
3.5
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.2
2.7
2.5
2.4
2.3
14.5
8.7
7.1
5.3
4.6
3.0
2.7
2.3
2.2
1.9
14.9
9.4
7.9
5.9
4.9
15.2
9.8
8.3
6.2
5.1
CL = 15 pF
tpd
propagation delay A, B and C to Y;
see Figure 12
VCC = 0.8 V
-
29.9
8.3
5.9
5.0
4.2
3.9
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.6
3.0
2.8
2.7
2.5
16.1
9.7
7.9
5.9
5.2
3.3
3.0
2.5
2.5
2.2
16.7
10.5
8.7
17.0
11.0
9.2
6.6
6.9
5.5
5.8
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
8 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ[1] Max
Min
Max
Max
(85 °C) (125 °C)
CL = 30 pF
[2]
tpd
propagation delay A, B and C to Y;
see Figure 12
VCC = 0.8 V
-
38.0
10.5
7.5
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
4.5
3.8
3.4
3.4
3.3
20.8
12.2
10.0
7.5
4.1
3.8
3.1
3.1
2.9
21.9
13.5
11.2
8.4
24.1
14.1
11.9
8.9
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
6.3
5.3
5.0
6.6
7.1
7.4
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation fi = 1 MHz; VI = GND to VCC
[3][4]
capacitance
VCC = 0.8 V
-
-
-
-
-
-
2.7
2.8
3.0
3.2
3.8
4.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] All specified values are the average typical values over all stated loads.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
9 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
12. Waveforms
V
I
A, B, C input
GND
V
V
M
M
t
t
PLH
PHL
V
OH
V
V
V
M
Y output
M
V
OL
t
t
PLH
PHL
V
OH
Y output
V
M
M
V
OL
001aab593
Measurement points are given in Table 10.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 12. Input A, B and C to output Y propagation delay times
Table 10. Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
10 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Load circuitry for switching times
Table 11. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
11 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
13. Transfer characteristics
Table 12. Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 13.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C
Unit
Min Typ Max
Min
Max
Max
(85 °C) (125 °C)
VT+
VT−
VH
positive-going
threshold voltage Figure 15
see Figure 14 and
VCC = 0.8 V
0.30
0.53
0.74
0.91
1.37
1.88
-
-
-
-
-
-
0.60
0.90
1.11
1.29
1.77
2.29
0.30
0.53
0.74
0.91
1.37
1.88
0.60
0.90
1.11
1.29
1.77
2.29
0.62
0.92
1.13
1.31
1.80
2.32
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
negative-going
threshold voltage Figure 15
see Figure 14 and
VCC = 0.8 V
0.10
0.26
0.39
0.47
0.69
0.88
-
-
-
-
-
-
0.60
0.65
0.75
0.84
1.04
1.24
0.10
0.26
0.39
0.47
0.69
0.88
0.60
0.65
0.75
0.84
1.04
1.24
0.60
0.65
0.75
0.84
1.04
1.24
V
V
V
V
V
V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
hysteresis voltage (VT+ − VT−); see Figure 14,
Figure 15, Figure 16 and
Figure 17
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
0.07
0.08
0.18
0.27
0.53
0.79
-
-
-
-
-
-
0.50
0.46
0.56
0.66
0.92
1.31
0.07
0.08
0.18
0.27
0.53
0.79
0.50
0.46
0.56
0.66
0.92
1.31
0.50
0.46
0.56
0.66
0.92
1.31
V
V
V
V
V
V
14. Waveforms transfer characteristics
V
T+
V
O
V
I
V
H
V
T−
V
O
V
I
mna208
V
H
V
V
T+
T−
mna207
VT+ and VT− limits at 70 % and 20 %.
Fig 14. Transfer characteristic
Fig 15. Definition of VT+, VT− and VH
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
12 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
001aad691
240
I
CC
(µA)
160
80
0
0
0.4
0.8
1.2
1.6
2.0
V (V)
I
Fig 16. Typical transfer characteristics; VCC = 1.8 V
001aad692
1200
I
CC
(µA)
800
400
0
0
1.0
2.0
3.0
V (V)
I
Fig 17. Typical transfer characteristics; VCC = 3.0 V
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
13 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
15. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 18. Package outline SOT363 (SC-88)
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
14 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 19. Package outline SOT886 (XSON6)
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
15 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
(1)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 20. Package outline SOT891 (XSON6)
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
16 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
16. Abbreviations
Table 13. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
17. Revision history
Table 14. Revision history
Document ID
74AUP1G58_3
Modifications:
74AUP1G58_2
74AUP1G58_1
Release date
20090622
Data sheet status
Change notice
Supersedes
Product data sheet
-
74AUP1G58_2
• Table 6: Derating factor of XSON6 packages has been changed.
20090326
Product data sheet
-
74AUP1G58_1
-
20070131
Product data sheet
-
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
17 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AUP1G58_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 June 2009
18 of 19
74AUP1G58
NXP Semiconductors
Low-power configurable multiple function gate
20. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 3
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Transfer characteristics. . . . . . . . . . . . . . . . . . 12
Waveforms transfer characteristics. . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
9
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 June 2009
Document identifier: 74AUP1G58_3
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