74AUP1G885 [NXP]
Low-power dual function gate; 低功耗双门功能
| 型号： | 74AUP1G885 |
| 厂家： | 
NXP |
| 描述： | Low-power dual function gate |
| 文件： | 总19页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G885
Low-power dual function gate
Rev. 01.00 — 26 January 2006
Preliminary data sheet
1. General description
The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G885 provides two functions in one device.The output state of the outputs
(1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the boolean
funtion: 1Y = A × C. The output 2Y provides the boolean funtion: 2Y = A × B + A × C
2. Features
■ Wide supply voltage range from 0.8 V to 3.6 V
■ High noise immunity
■ Complies with JEDEC standards:
◆ JESD8-12 (0.8 V to 1.3 V)
◆ JESD8-11 (0.9 V to 1.65 V)
◆ JESD8-7 (1.2 V to 1.95 V)
◆ JESD8-5 (1.8 V to 2.7 V)
◆ JESD8-B (2.7 V to 3.6 V)
■ ESD protection:
◆ HBM JESD22-A114-C Class 3A exceeds 4000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101-C exceeds 1000 V
■ Low static power consumption; ICC = 0.9 µA (maximum)
■ Latch-up performance exceeds 100 mA per JESD 78 Class II
■ Inputs accept voltages up to 3.6 V
■ Low noise overshoot and undershoot < 10 % of VCC
■ IOFF circuitry provides partial Power-down mode operation
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74AUP1G885
Philips Semiconductors
Low-power dual function gate
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3 ns.
Symbol Parameter
Conditions
CL = 5 pF; RL = 1 MΩ;
CC = 0.8 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.1 V to 1.3 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.4 V to 1.6 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.65 V to 1.95 V
CL = 5 pF; RL = 1 MΩ;
CC = 2.3 V to 2.7 V
CL = 5 pF; RL = 1 MΩ;
CC = 3.0 V to 3.6 V
CL = 5 pF; RL = 1 MΩ;
CC = 0.8 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.1 V to 1.3 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.4 V to 1.6 V
CL = 5 pF; RL = 1 MΩ;
CC = 1.65 V to 1.95 V
CL = 5 pF; RL = 1 MΩ;
CC = 2.3 V to 2.7 V
CL = 5 pF; RL = 1 MΩ;
CC = 3.0 V to 3.6 V
Min
Typ
Max
Unit
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
-
17.3
-
ns
V
propagation delay
A, C to 1Y
1.1
1.2
1.1
1.1
1.1
-
5.2
3.7
3.0
2.4
2.1
21.5
6.0
4.2
3.3
2.6
2.3
9.7
5.9
4.8
3.6
3.1
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH
V
propagation delay
A, B to 2Y
1.7
1.7
1.4
1.2
1.1
12.7
7.2
5.8
4.1
3.5
V
V
V
V
V
CI
input capacitance
-
-
-
0.8
3.1
4.1
-
-
-
pF
pF
pF
[1] [2]
[1] [2]
CPD
power dissipation
capacitance
VCC = 1.8 V; f = 1 MHz
VCC = 3.3 V; f = 1 MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC
.
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
2 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1G885DC
74AUP1G885GT
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
5. Marking
Table 3:
Marking
Type number
74AUP1G885DC
74AUP1G885GT
Marking code
pS8
pS8
6. Functional diagram
1
A
3
7
2Y
1Y
2
6
B
C
001aae353
Fig 1. Logic diagram
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
3 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
7. Pinning information
7.1 Pinning
74AUP1G885
A
B
1
2
3
4
8
7
6
5
V
CC
1Y
C
74AUP1G885
2Y
1
2
3
4
8
7
6
5
A
B
V
CC
1Y
C
GND
n.c.
2Y
GND
n.c.
001aae355
Transparent top view
001aae354
Fig 2. Pin configuration SOT765-1
(VSSOP8)
Fig 3. Pin configuration SOT833-1
(XSON8)
7.2 Pin description
Table 4:
Pin description
Symbol
A
Pin
1
Description
data input A
data input B
data output 2Y
ground (0 V)
not connected
data input C
data output 1Y
supply voltage
B
2
2Y
3
GND
n.c.
C
4
5
6
1Y
7
VCC
8
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
4 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
8. Functional description
8.1 Function table
Table 5:
Function table[1]
Input
Output
A
L
B
L
C
L
1Y
L
2Y
L
H
L
L
L
L
H
H
H
L
H
H
L
L
L
H
L
L
L
H
H
H
H
L
H
L
L
H
L
L
H
H
H
L
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
9. Limiting values
Table 6:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
-
Max
+4.6
−50
Unit
V
VCC
IIK
supply voltage
input clamping
current
VI < 0 V
mA
[1]
VI
input voltage
−0.5
+4.6
V
IOK
output clamping
current
VO < 0 V
-
−50
mA
[1]
[1]
VO
output voltage
active mode
−0.5
VCC + 0.5 V
Power-down mode
VO = 0 V to VCC
−0.5
+4.6
±20
+50
V
IO
output current
-
-
mA
mA
ICC
quiescent supply
current
IGND
Tstg
Ptot
ground current
-
−50
mA
°C
storage temperature
−65
+150
300
[2]
total power
dissipation
Tamb = −40 °C to +125 °C
-
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are
observed.
[2] For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
5 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
10. Recommended operating conditions
Table 7:
Recommended operating conditions
Symbol Parameter
Conditions
Min
0.8
0
Max Unit
VCC
VI
supply voltage
input voltage
output voltage
3.6
3.6
VCC
3.6
V
V
V
V
VO
active mode
0
Power-down mode; VCC = 0 V
0
Tamb
ambient temperature
−40
0
+125 °C
200 ns/V
∆t/∆V
input transition rise and
fall rate
VCC = 0.8 V to 3.6 V
11. Static characteristics
Table 8:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-state input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
0.75 × VCC
1.11
1.32
2.05
1.9
2.72
2.6
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
6 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.5
40
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current
VCC = 3.3 V
CI
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
0.8
1.7
-
-
pF
pF
CO
Tamb = −40 °C to +85 °C
VIH HIGH-state input voltage
VCC = 0.8 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
7 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
II
input leakage current
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current CC = 3.3 V
V
Tamb = −40 °C to +125 °C
VIH HIGH-state input voltage
VCC = 0.8 V
0.75 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.70 × VCC
-
1.6
-
2.0
-
VIL
LOW-state input voltage
-
-
-
-
0.25 × VCC
0.30 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-state output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
V
CC − 0.11 -
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
0.6 × VCC
0.93
1.17
1.77
1.67
2.40
2.30
-
-
-
-
-
-
-
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
8 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
Table 8:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
0.33 × VCC
0.41
V
V
0.39
V
0.36
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
±0.75
µA
µA
µA
IOFF
∆IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
CC = 0 V to 0.2 V
V
ICC
quiescent supply current
VI = GND or VCC; IO = 0 A;
CC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
µA
µA
V
[1]
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0 A;
current CC = 3.3 V
V
[1] One input at VCC − 0.6 V, other input at VCC or GND.
12. Dynamic characteristics
Table 9:
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C; CL = 5 pF
tPHL, tPLH HIGH-to-LOW and
see Figure 4
LOW-to-HIGH propagation
delay A, C to 1Y
VCC = 0.8 V
-
17.3
5.2
3.7
3.0
2.4
2.1
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 4
1.1
1.2
1.1
1.1
1.1
9.7
5.9
4.8
3.6
3.1
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH propagation
delay A, B to 2Y
VCC = 0.8 V
-
21.5
6.0
4.2
3.3
2.6
2.3
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.7
1.7
1.4
1.2
1.1
12.7
7.2
5.8
4.1
3.5
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
9 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
Table 9:
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C; CL = 10 pF
tPHL, tPLH HIGH-to-LOW and
see Figure 4
LOW-to-HIGH propagation
delay A, C to 1Y
VCC = 0.8 V
-
20.8
6.1
4.3
3.6
2.9
2.7
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 4
1.2
1.4
1.4
1.4
1.4
11.4
7.2
5.7
4.2
3.9
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH propagation
delay A, B to 2Y
VCC = 0.8 V
-
25.0
6.9
4.8
3.9
3.1
2.8
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.8
1.9
1.9
1.5
1.4
14.4
8.5
6.6
4.7
4.3
Tamb = 25 °C; CL = 15 pF
tPHL, tPLH HIGH-to-LOW and
see Figure 4
LOW-to-HIGH propagation
delay A, C to 1Y
VCC = 0.8 V
-
24.3
6.9
4.9
4.1
3.4
3.1
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
see Figure 4
1.3
1.7
1.5
1.7
1.7
13.0
8.0
6.4
5.0
4.4
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH propagation
delay A, B to 2Y
VCC = 0.8 V
-
28.5
7.7
5.4
4.4
3.6
3.3
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.1
2.2
2.0
1.8
1.7
16.0
9.4
7.4
5.5
4.8
Tamb = 25 °C; CL = 30 pF
tPHL, tPLH HIGH-to-LOW and
see Figure 4
LOW-to-HIGH propagation
delay A, C to 1Y
VCC = 0.8 V
-
34.7
9.2
6.5
5.4
4.5
4.2
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.4
2.5
2.5
2.6
2.5
17.7
10.6
8.5
6.4
5.7
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Preliminary data sheet
Rev. 01.00 — 26 January 2006
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Low-power dual function gate
Table 9:
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5
[1]
Symbol
tPHL, tPLH HIGH-to-LOW and
LOW-to-HIGH propagation
delay A, B to 2Y
Parameter
Conditions
Min
Typ
Max
Unit
see Figure 4
VCC = 0.8 V
-
38.9
10.0
6.9
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.6
2.6
2.7
2.5
2.4
20.5
11.9
9.5
6.9
6.1
5.7
4.7
4.4
Tamb = 25 °C
[2] [3]
CPD
power dissipation capacitance f = 1 MHz
VCC = 0.8 V
-
-
-
-
-
-
2.7
2.9
3.0
3.1
3.5
4.1
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[3] The condition is VI = GND to VCC
.
74AUP1G885_1
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Preliminary data sheet
Rev. 01.00 — 26 January 2006
11 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
Table 10: Dynamic characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
CL = 5 pF
tPHL, tPLH HIGH-to-LOW and see Figure 4
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
0.9
1.0
0.9
1.0
1.0
12.8
7.8
6.2
4.1
3.6
0.9
1.0
0.9
1.0
1.0
14.2
8.6
6.9
4.5
4.1
ns
ns
ns
ns
ns
propagation delay
A, C to 1Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
tPHL, tPLH HIGH-to-LOW and see Figure 4
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
1.4
1.4
1.2
1.0
0.9
12.8
7.8
6.5
4.7
3.8
1.4
1.4
1.2
1.0
0.9
14.2
8.7
7.2
5.2
4.2
ns
ns
ns
ns
ns
propagation delay
A, B to 2Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
CL = 10 pF
tPHL, tPLH HIGH-to-LOW and see Figure 4
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
1.2
1.2
1.3
1.2
1.3
14.6
8.7
6.8
4.8
4.1
1.2
1.2
1.3
1.2
1.3
16.1
9.6
7.5
5.4
4.6
ns
ns
ns
ns
ns
propagation delay
A, C to 1Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
tPHL, tPLH HIGH-to-LOW and see Figure 4
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
1.7
1.5
1.7
1.3
1.3
14.6
9.1
7.2
5.4
4.6
1.7
1.5
1.7
1.3
1.3
16.1
10.1
8.0
ns
ns
ns
ns
ns
propagation delay
A, B to 2Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
5.9
5.1
CL = 15 pF
tPHL, tPLH HIGH-to-LOW and see Figure 4
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
1.2
1.4
1.4
1.6
1.6
16.2
9.7
7.6
5.4
4.7
1.2
1.4
1.4
1.6
1.6
17.9
10.8
8.4
ns
ns
ns
ns
ns
propagation delay
A, C to 1Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
6.0
5.3
tPHL, tPLH HIGH-to-LOW and see Figure 4
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
1.9
2.4
1.8
1.6
1.5
16.3
10.3
8.2
1.9
2.4
1.8
1.6
1.5
18.0
11.4
9.1
ns
ns
ns
ns
ns
propagation delay
A, B to 2Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
6.0
6.7
5.2
5.8
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
12 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
Table 10: Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5
Symbol
Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
CL = 30 pF
tPHL, tPLH HIGH-to-LOW and see Figure 4
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.3
2.5
2.4
2.4
2.3
20.9
12.2
9.4
2.3
2.5
2.4
2.4
2.3
23.0
13.5
10.4
7.7
ns
ns
ns
ns
ns
propagation delay
A, C to 1Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
7.0
6.6
7.3
tPHL, tPLH HIGH-to-LOW and see Figure 4
LOW-to-HIGH
VCC = 1.1 V to 1.3 V
2.6
2.6
2.7
2.5
2.4
21.5
13.2
10.5
7.6
2.6
2.6
2.7
2.5
2.4
23.7
14.5
11.6
8.4
ns
ns
ns
ns
ns
propagation delay
A, B to 2Y
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
7.1
7.9
13. Waveforms
V
I
A, B, C input
V
M
GND
t
t
PLH
PHL
V
OH
nY output
V
M
001aae356
V
OL
Measurement points are given in Table 11.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 4. The data input (A, B, C) to output (nY) propagation delays
Table 11: Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
13 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
V
V
EXT
CC
5 kΩ
V
V
O
I
PULSE
GENERATOR
DUT
R
C
R
L
T
L
001aac521
Test data is given in Table 12.
Definitions for test circuit:
RL = Load resistance
CL = Load capacitance including jig and probe capacitance
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator
VEXT = External voltage for measuring switching times.
Fig 5. Load circuitry for switching times
Table 12: Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF,
5 kΩ or 1 MΩ open
GND
2 × VCC
15 pF and 30 pF
[1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times
and pulse width RL = 1 MΩ.
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
14 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
14. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 6. Package outline SOT765-1 (VSSOP8)
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
15 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
04-07-22
04-11-09
SOT833-1
- - -
MO-252
Fig 7. Package outline SOT833-1 (XSON8)
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
16 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
15. Abbreviations
Table 13: Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor Transistor Logic
16. Revision history
Table 14: Revision history
Document ID
Release date Data sheet status
<tbd> Preliminary data sheet
Change notice Doc. number
Supersedes
74AUP1G885_1
-
-
-
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
17 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
17. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
18. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
20. Trademarks
Notice — All referenced brands, product names, service names and
19. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74AUP1G885_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01.00 — 26 January 2006
18 of 19
74AUP1G885
Philips Semiconductors
Low-power dual function gate
22. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
9
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information . . . . . . . . . . . . . . . . . . . . 18
10
11
12
13
14
15
16
17
18
19
20
21
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 26 January 2006
Document number: 74AUP1G885_1
Published in The Netherlands
相关型号：
74AUP1G885DC-G
IC AUP/ULP/V SERIES, DUAL 3-INPUT XOR GATE, PDSO8, 2.30 MM, GREEN, PLASTIC, MO-187, SOT-765-1, VSSOP-8, Gate
NXP
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