74AUP1T34GW-Q100 [NXP]
IC NON-INVERT GATE, Gate;
| 型号： | 74AUP1T34GW-Q100 |
| 厂家： | 
NXP |
| 描述： | IC NON-INVERT GATE, Gate 栅 光电二极管 逻辑集成电路 |
| 文件： | 总18页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1T34-Q100
Low-power dual supply translating buffer
Rev. 1 — 5 June 2013
Product data sheet
1. General description
The 74AUP1T34-Q100 provides a single buffer with two separate supply voltages. Input A
is designed to track VCC(A). Output Y is designed to track VCC(Y). Both, VCC(A) and VCC(Y)
accepts any supply voltage from 1.1 V to 3.6 V. This feature allows universal low voltage
interfacing between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 1.1 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire VCC range from 1.1 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.1 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
HBM JESD22-A114F Class 3A. Exceeds 5000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Wide supply voltage range:
VCC(A): 1.1 V to 3.6 V
VCC(Y): 1.1 V to 3.6 V
Low static power consumption; ICC = 0.9 A (maximum)
Each port operates over the full 1.1 V to 3.6 V power supply range
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1T34GW-Q100 40 C to +125 C
TSSOP5
plastic thin shrink small outline package; 5 leads; SOT353-1
body width 1.25 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1T34GW-Q100
pQ
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
2
A
Y
4
2
4
A
Y
001aac538
001aac537
001aac536
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
ꢀꢁ$83ꢂ7ꢃꢁꢄ4ꢂꢅꢅ
ꢂ
ꢃ
ꢄ
ꢅ
9
9
<
&&ꢀ$ꢁ
&&ꢀ<ꢁ
$
ꢆ
*1'
DDDꢀꢁꢁꢂꢃꢂꢁ
Fig 4. Pin configuration SOT353-1
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
2 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
6.2 Pin description
Table 3.
Symbol
VCC(A)
A
Pin description
Pin
1
Description
supply voltage port A
data input A
2
GND
Y
3
ground (0 V)
4
data output Y
VCC(Y)
5
supply voltage port Y
7. Functional description
Table 4.
Function table[1]
Input
Output
A
L
Y
L
H
H
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(Y)
IIK
Parameter
Conditions
Min
0.5
0.5
50
0.5
50
0.5
-
Max
+4.6
+4.6
-
Unit
V
supply voltage A
supply voltage Y
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
VO
Active mode and Power-down mode
VO = 0 V to VCC(Y)
+4.6
20
50
IO
output current
mA
mA
mA
C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = 40 C to +125 C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
3 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(Y)
VI
Recommended operating conditions
Parameter
Conditions
Min
1.1
1.1
0
Max
3.6
Unit
V
supply voltage A
supply voltage Y
input voltage
3.6
V
3.6
V
VO
output voltage
ambient temperature
0
VCC(Y)
+125
200
V
Tamb
40
0
C
ns/V
t/V
input transition rise and fall rate control and data inputs;
VCC(A) = 1.1 V to 3.6 V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
Tamb = 25 C
VIH
HIGH-level
input voltage
VCC(A) = 1.1 V to 1.95 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.0 V to 3.6 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 1.1 V to 1.95 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.0 V to 3.6 V; VCC(Y) = 1.1 V to 3.6 V
VI = VIH
0.65 VCC(A)
-
-
-
-
-
-
-
V
V
V
V
V
V
1.6
-
2.0
-
VIL
LOW-levelinput
voltage
-
-
-
0.35 VCC(A)
0.7
0.9
VOH
HIGH-level
output voltage
IO = 20 A; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(Y) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(Y) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(Y) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(Y) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(Y) = 3.0 V
VI = VIL
VCC(Y) 0.1
0.75 VCC(Y)
1.11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level
output voltage
IO = 20 A; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(Y) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(Y) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(Y) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(Y) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(Y) = 3.0 V
VI = 0 V to 3.6 V; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
V
V
A
0.3 VCC(Y)
0.31
0.31
0.31
0.44
0.31
0.44
II
input leakage
current
0.1
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
4 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
IOFF
IOFF
ICC
power-off
Input A; VI = 0 V to 3.6 V;
-
-
-
-
-
0.2
0.2
0.2
0.2
A
leakage current VCC(A) = 0 V; VCC(Y) = 0 V to 3.6 V
Output Y; VO = 0 V to 3.6 V; VCC(A) = 0 V to 3.6 V;
VI = 0 V or 3.6 V; VCC(Y) = 0 V
-
-
-
A
A
A
additional
power-off
leakage current
Input A; VI = 0 V to 3.6 V;
VCC(A) = 0 V to 0.2 V; VCC(Y) = 0 V to 3.6 V
Output Y; VO = 0 V to 3.6 V; VCC(A) = 0 V to 3.6 V;
VI = 0 V or 3.6 V; VCC(Y) = 0 V to 0.2 V
supply current port A; VI = GND or VCC(A); IO = 0 A
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(Y) = 0 V
-
-
-
-
0.5
0.5
-
A
A
A
-
VCC(A) = 0 V; VCC(Y) = 3.6 V
0.0
port Y; VI = GND or VCC(A); IO = 0 A
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(Y) = 0 V
-
-
-
-
-
0.5
-
A
A
A
A
0.0
VCC(A) = 0 V; VCC(Y) = 3.6 V
-
-
0.5
0.5
port A and port Y; VI = GND or VCC(A); IO = 0 A;
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
ICC
CI
additional
supply current VI = VCC(A) 0.6 V
Input A; VCC(A) = 3.3 V; VCC(Y) = 0 V to 3.6 V;
-
-
-
-
40
-
A
pF
pF
input
capacitance
Input A; VCC(A) = VCC(Y) = 0 V to 3.6 V;
VI = GND or VCC(A)
1.0
1.8
CO
output
capacitance
Output Y; VO = GND; VCC(Y) = 0 V;
VCC(A) = 0 V to 3.6 V
-
T
amb = 40 C to +85 C
VIH
HIGH-level
input voltage
VCC(A) = 1.1 V to 1.95 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.0 V to 3.6 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 1.1 V to 1.95 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.0 V to 3.6 V; VCC(Y) = 1.1 V to 3.6 V
VI = VIH
0.65 VCC(A)
-
-
-
-
-
-
-
V
V
V
V
V
V
1.6
-
2.0
-
VIL
LOW-levelinput
voltage
-
-
-
0.35 VCC(A)
0.7
0.9
VOH
HIGH-level
output voltage
IO = 20 A; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(Y) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(Y) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(Y) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(Y) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(Y) = 3.0 V
VCC(Y) 0.1
0.7 VCC(Y)
1.03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.30
1.97
1.85
2.67
2.55
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
5 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
VOL
LOW-level
VI = VIL
output voltage
IO = 20 A; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(Y) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(Y) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(Y) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(Y) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(Y) = 3.0 V
VI = 0 V to 3.6 V; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
V
V
A
0.3 VCC(Y)
0.37
0.35
0.33
0.45
0.33
0.45
II
input leakage
current
0.5
IOFF
power-off
Input A; VI = 0 V to 3.6 V;
-
-
-
-
-
-
-
-
0.5
0.5
0.6
0.6
A
A
A
A
leakage current VCC(A) = 0 V; VCC(Y) = 0 V to 3.6 V
Output Y; VO = 0 V to 3.6 V; VCC(A) = 0 V to 3.6 V;
VI = 0 V or 3.6 V; VCC(Y) = 0 V
IOFF
additional
power-off
leakage current
Input A; VI = 0 V to 3.6 V;
VCC(A) = 0 V to 0.2 V; VCC(Y) = 0 V to 3.6 V
Output Y; VO = 0 V to 3.6 V; VCC(A) = 0 V to 3.6 V;
VI = 0 V or 3.6 V; VCC(Y) = 0 V to 0.2 V
ICC
supply current port A; VI = GND or VCC(A); IO = 0 A
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(Y) = 0 V
-
-
-
-
0.9
0.9
-
A
A
A
-
VCC(A) = 0 V; VCC(Y) = 3.6 V
0.0
port Y; VI = GND or VCC(A); IO = 0 A
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(Y) = 0 V
-
-
-
-
-
0.9
-
A
A
A
A
0.0
VCC(A) = 0 V; VCC(Y) = 3.6 V
-
-
0.9
0.9
port A and port Y; VI = GND or VCC(A); IO = 0 A;
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
ICC
additional
supply current VI = VCC(A) 0.6 V
Input A; VCC(A) = 3.3 V; VCC(Y) = 0 V to 3.6 V;
-
-
50
A
Tamb = 40 C to +125 C
VIH
HIGH-level
input voltage
VCC(A) = 1.1 V to 1.95 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.0 V to 3.6 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 1.1 V to 1.95 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 2.3 V to 2.7 V; VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.0 V to 3.6 V; VCC(Y) = 1.1 V to 3.6 V
0.7 VCC(A)
-
-
-
-
-
-
-
V
V
V
V
V
V
1.6
-
2.0
-
VIL
LOW-levelinput
voltage
-
-
-
0.3 VCC(A)
0.7
0.9
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
6 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ Max
Unit
VOH
HIGH-level
VI = VIH
output voltage
IO = 20 A; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(Y) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(Y) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(Y) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(Y) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(Y) = 3.0 V
VI = VIL
VCC(Y) 0.11
0.6 VCC(Y)
0.93
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.17
1.77
1.67
2.40
2.30
VOL
LOW-level
output voltage
IO = 20 A; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
IO = 1.1 mA; VCC(A) = VCC(Y) = 1.1 V
IO = 1.7 mA; VCC(A) = VCC(Y) = 1.4 V
IO = 1.9 mA; VCC(A) = VCC(Y) = 1.65 V
IO = 2.3 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 3.1 mA; VCC(A) = VCC(Y) = 2.3 V
IO = 2.7 mA; VCC(A) = VCC(Y) = 3.0 V
IO = 4.0 mA; VCC(A) = VCC(Y) = 3.0 V
VI = 0 V to 3.6 V; VCC(A) = VCC(Y) = 1.1 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
V
V
V
V
V
V
V
V
A
0.33 VCC(Y)
0.41
0.39
0.36
0.50
0.36
0.50
II
input leakage
current
0.75
IOFF
power-off
Input A; VI = 0 V to 3.6 V;
-
-
-
-
-
-
-
-
0.75
0.75
0.75
0.75
A
A
A
A
leakage current VCC(A) = 0 V; VCC(Y) = 0 V to 3.6 V
Output Y; VO = 0 V to 3.6 V; VCC(A) = 0 V to 3.6 V;
VI = 0 V or 3.6 V; VCC(Y) = 0 V
IOFF
additional
power-off
leakage current
Input A; VI = 0 V to 3.6 V;
VCC(A) = 0 V to 0.2 V; VCC(Y) = 0 V to 3.6 V
Output Y; VO = 0 V to 3.6 V; VCC(A) = 0 V to 3.6 V;
VI = 0 V or 3.6 V; VCC(Y) = 0 V to 0.2 V
ICC
supply current port A; VI = GND or VCC(A); IO = 0 A
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(Y) = 0 V
-
-
-
-
1.4
1.4
-
A
A
A
-
VCC(A) = 0 V; VCC(Y) = 3.6 V
0.0
port Y; VI = GND or VCC(A); IO = 0 A
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(Y) = 0 V
-
-
-
-
-
1.4
-
A
A
A
A
0.0
VCC(A) = 0 V; VCC(Y) = 3.6 V
-
-
1.4
1.4
port A and port Y; VI = GND or VCC(A); IO = 0 A;
VCC(A) = VCC(Y) = 1.1 V to 3.6 V
ICC
additional
supply current VI = VCC(A) 0.6 V
Input A; VCC(A) = 3.3 V; VCC(Y) = 0 V to 3.6 V;
-
-
75
A
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
7 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter Conditions
25 C
40 C to +125 C
Max Max
(85 C) (125 C)
Unit
Min Typ[1] Max Min
CL = 5 pF; VCC(A) = 1.1 V to 1.3 V
tpd propagation delay A to Y; see Figure 5
[2]
[2]
[2]
[2]
[2]
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.6
2.4
2.1
2.0
2.1
9.8
7.1
6.0
5.1
4.7
25.4 2.3
15.3 2.2
12.7 1.9
25.9
16.3
13.8
10.5
9.1
25.9
16.7
14.3
10.9
9.3
ns
ns
ns
ns
ns
9.8
8.8
2.0
1.9
CL = 5 pF; VCC(A) = 1.4 V to 1.6 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.3
2.1
1.8
1.7
1.8
9.1
6.4
5.3
4.3
3.9
23.9 2.0
13.6 1.9
10.9 1.6
24.5
14.7
12.1
8.7
24.5
15.2
12.6
9.2
ns
ns
ns
ns
ns
7.8
6.6
1.6
1.6
7.1
7.5
CL = 5 pF; VCC(A) = 1.65 V to 1.95 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.2
2.0
1.8
1.6
1.7
8.8
6.0
4.9
3.9
3.5
23.2 1.9
13.0 1.8
10.3 1.5
23.9
14.1
11.4
8.0
24.0
14.6
12.0
8.5
ns
ns
ns
ns
ns
7.2
5.9
1.5
1.5
6.4
6.8
CL = 5 pF; VCC(A) = 2.3 V to 2.7 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.2
1.9
1.7
1.5
1.6
8.4
5.7
4.6
3.5
3.1
22.8 1.9
12.3 1.8
23.4
13.4
10.7
7.2
23.4
14.0
11.2
7.7
ns
ns
ns
ns
ns
9.6
6.3
5.1
1.5
1.5
1.4
5.6
6.0
CL = 5 pF; VCC(A) = 3.0 V to 3.6 V
tpd
propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.2
1.9
1.7
1.5
1.6
8.1
5.4
4.3
3.3
2.9
22.5 1.9
12.0 1.8
22.9
12.9
10.2
6.7
22.9
13.4
10.7
7.2
ns
ns
ns
ns
ns
9.2
6.0
4.8
1.5
1.5
1.4
5.2
5.5
74AUP1T34_Q100
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Product data sheet
Rev. 1 — 5 June 2013
8 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Max Max
(85 C) (125 C)
Unit
Min Typ[1] Max Min
CL = 10 pF; VCC(A) = 1.1 V to 1.3 V
tpd propagation delay A to Y; see Figure 5
[2]
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.6
2.6
2.7
2.2
2.5
10.7 27.1 2.5
27.6
17.5
14.2
11.0
9.7
27.6
17.6
14.7
11.4
10.0
ns
ns
ns
ns
ns
7.7
6.6
5.6
5.3
16.7 2.3
13.4 2.4
10.3 2.2
9.5
2.2
CL = 10 pF; VCC(A) = 1.4 V to 1.6 V
tpd propagation delay A to Y; see Figure 5
[2]
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.4
2.4
2.4
2.0
2.2
10.0 25.6 2.2
26.1
15.8
12.5
9.2
26.1
16.4
13.1
9.7
ns
ns
ns
ns
ns
7.0
5.9
4.8
4.4
15.0 2.0
11.6 2.1
8.4
7.4
1.9
1.9
7.7
8.1
CL = 10 pF; VCC(A) = 1.65 V to 1.95 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.3
2.3
2.3
1.9
2.1
9.7
6.6
5.5
4.4
4.0
24.8 2.1
14.3 2.0
11.0 2.0
25.5
15.3
11.9
8.6
25.7
15.8
12.5
9.0
ns
ns
ns
ns
ns
7.7
6.6
1.8
1.8
7.1
7.4
CL = 10 pF; VCC(A) = 2.3 V to 2.7 V
tpd propagation delay A to Y; see Figure 5
[2]
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.3
2.2
2.2
1.8
2.0
9.3
6.3
5.1
4.1
3.6
24.4 2.1
13.6 1.9
10.3 2.0
25.1
14.6
11.2
7.7
25.1
15.1
11.7
8.2
ns
ns
ns
ns
ns
6.9
5.8
1.8
1.7
6.3
6.6
CL = 10 pF; VCC(A) = 3.0 V to 3.6 V
[2]
tpd
propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.3
2.2
2.2
1.8
2.0
9.0
6.0
4.9
3.9
3.5
24.2 2.1
13.3 1.9
24.6
14.1
10.6
7.3
24.6
14.6
11.2
7.7
ns
ns
ns
ns
ns
9.9
6.5
5.4
2.0
1.8
1.7
5.8
6.2
74AUP1T34_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
9 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Max Max
(85 C) (125 C)
Unit
Min Typ[1] Max Min
CL = 15 pF; VCC(A) = 1.1 V to 1.3 V
tpd propagation delay A to Y; see Figure 5
[2]
[2]
[2]
[2]
[2]
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
3.0
3.1
2.8
2.6
2.9
11.5
8.3
7.1
6.1
5.7
28.6 2.8
17.3 2.7
14.1 2.7
11.1 2.7
29.2
18.6
15.2
11.6
10.3
29.2
19.1
15.8
12.1
10.6
ns
ns
ns
ns
ns
9.9
2.6
CL = 15 pF; VCC(A) = 1.4 V to 1.6 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.8
2.8
2.5
2.3
2.6
10.8 27.1 2.6
27.7
17.0
13.5
9.9
27.7
17.6
14.1
10.3
8.7
ns
ns
ns
ns
ns
7.6
6.3
5.3
4.9
15.7 2.4
12.3 2.4
9.2
7.8
2.4
2.3
8.3
CL = 15 pF; VCC(A) = 1.65 V to 1.95 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.7
2.7
2.4
2.2
2.5
10.5 26.4 2.5
27.1
16.4
12.8
9.2
27.3
17.0
13.5
9.7
ns
ns
ns
ns
ns
7.2
6.0
4.9
4.5
15.0 2.3
11.7 2.3
8.5
7.1
2.2
2.2
7.7
8.0
CL = 15 pF; VCC(A) = 2.3 V to 2.7 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.6
2.7
2.4
2.1
2.4
10.1 26.0 2.4
26.7
15.7
12.1
8.4
26.7
16.3
12.7
8.9
ns
ns
ns
ns
ns
6.9
5.6
4.5
4.1
14.3 2.3
10.9 2.2
7.6
6.2
2.2
2.1
6.8
7.2
CL = 15 pF; VCC(A) = 3.0 V to 3.6 V
tpd
propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
2.6
2.7
2.4
2.1
2.4
9.8
6.6
5.4
4.3
3.9
25.7 2.4
14.0 2.3
10.5 2.2
26.2
15.2
11.6
7.9
26.2
15.7
12.1
8.4
ns
ns
ns
ns
ns
7.3
5.9
2.2
2.1
6.4
6.8
74AUP1T34_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
10 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Max Max
(85 C) (125 C)
Unit
Min Typ[1] Max Min
CL = 30 pF; VCC(A) = 1.1 V to 1.3 V
tpd propagation delay A to Y; see Figure 5
[2]
[2]
[2]
[2]
[2]
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
3.7
3.6
3.7
3.0
3.8
13.7 32.9 3.5
33.5
20.9
17.0
12.7
12.2
33.5
21.4
17.7
13.2
12.5
ns
ns
ns
ns
ns
9.8
8.4
7.2
6.8
19.5 3.6
15.9 3.5
12.2 3.4
10.9 3.4
CL = 30 pF; VCC(A) = 1.4 V to 1.6 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
3.5
3.3
3.4
2.8
3.5
13.1 31.5 3.2
32.0
19.2
15.4
11.0
10.1
32.0
19.9
16.0
11.5
10.5
ns
ns
ns
ns
ns
9.1
7.6
6.4
5.9
17.8 3.3
14.2 3.2
10.3 3.1
8.9
3.1
CL = 30 pF; VCC(A) = 1.65 V to 1.95 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
3.4
3.2
3.3
2.7
3.4
12.7 30.7 3.1
31.5
18.7
14.7
10.4
9.4
31.5
19.3
15.4
10.9
9.8
ns
ns
ns
ns
ns
8.8
7.3
6.0
5.6
17.2 3.2
13.5 3.1
9.6
8.2
3.0
2.9
CL = 30 pF; VCC(A) = 2.3 V to 2.7 V
tpd propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
3.3
3.2
3.2
2.6
3.3
12.4 30.3 3.1
31.0
18.0
14.0
9.6
31.0
18.7
14.6
10.1
9.0
ns
ns
ns
ns
ns
8.4
6.9
5.6
5.2
16.5 3.1
12.8 3.0
8.8
7.3
2.9
2.9
8.5
CL = 30 pF; VCC(A) = 3.0 V to 3.6 V
tpd
propagation delay A to Y; see Figure 5
VCC(Y) = 1.1 V to 1.3 V
VCC(Y) = 1.4 V to 1.6 V
VCC(Y) = 1.65 V to 1.95 V
VCC(Y) = 2.3 V to 2.7 V
VCC(Y) = 3.0 V to 3.6 V
3.3
3.2
3.2
2.6
3.2
12.0 30.0 3.1
30.5
17.5
13.4
9.1
30.5
18.1
14.1
9.6
ns
ns
ns
ns
ns
8.1
6.7
5.5
5.0
16.2 3.1
12.4 3.0
8.5
7.0
2.9
2.9
8.1
8.5
74AUP1T34_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
11 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Max Max
(85 C) (125 C)
Unit
Min Typ[1] Max Min
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation fi = 1 MHz; VI = GND to VCC(A)
[3][4]
capacitance
VCC(A) = VCC(Y) = 1.2 V
VCC(A) = VCC(Y) = 1.5 V
VCC(A) = VCC(Y) = 1.8 V
VCC(A) = VCC(Y) = 2.5 V
VCC(A) = VCC(Y) = 3.3 V
-
-
-
-
-
3.8
3.8
4.1
4.2
4.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
[1] All typical values are measured at nominal VCC
[2] tpd is the same as tPLH and tPHL
[3] All specified values are the average typical values over all stated loads.
[4] PD is used to determine the dynamic power dissipation (PD in W).
.
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
12. Waveforms
V
I
V
M
A input
GND
t
t
PHL
PLH
V
OH
V
Y output
M
V
mnb153
OL
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. The data input (A) to output (Y) propagation delays
Table 9.
Measurement points
Supply voltage
VCC(A)/VCC(Y)
1.1 V to 3.6 V
Output
VM
Input
VM
VI
tr = tf
0.5 VCC(Y)
0.5 VCC(A)
VCC(A)
3.0 ns
74AUP1T34_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
12 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
V
V
V
EXT
CCA
CCY
5 kΩ
V
V
O
I
PULSE
GENERATOR
DUT
R
C
R
L
T
L
001aad742
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 6. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC(A)/VCC(Y)
1.1 V to 3.6 V
Load
VEXT
[1]
CL
RL
5 k or 1 M
tPLH, tPHL
open
5 pF, 10 pF, 15 pF and 30 pF
[1] For measuring enable and disable times, RL = 5 k. For measuring propagation delays, setup and hold times and pulse width,
RL = 1 M.
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
13 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 7. Package outline SOT353-1 (TSSOP5)
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
14 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
14. Abbreviations
Table 11. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
ESD
HBM
MIL
MM
Machine Model
15. Revision history
Table 12. Revision history
Document ID
Release date
20130605
Data sheet status
Change notice
Supersedes
74AUP1T34_Q100 v.1
Product data sheet
-
-
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
15 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
16.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
16 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AUP1T34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
17 of 18
NXP Semiconductors
74AUP1T34-Q100
Low-power dual supply translating buffer
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 June 2013
Document identifier: 74AUP1T34_Q100
相关型号：
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