74AUP1T57GN [NXP]
IC AUP/ULP/V SERIES, 3-INPUT MAJORITY LOGIC GATE, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6, Gate;
| 型号： | 74AUP1T57GN |
| 厂家： | 
NXP |
| 描述： | IC AUP/ULP/V SERIES, 3-INPUT MAJORITY LOGIC GATE, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6, Gate 栅 输入元件 光电二极管 |
| 文件： | 总20页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1T57
Low-power configurable gate with voltage-level translator
Rev. 4 — 1 December 2011
Product data sheet
1. General description
The 74AUP1T57 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions AND, OR, NAND, NOR, XNOR, inverter and buffer. All inputs can be connected
to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 2.3 V to 3.6 V.
The 74AUP1T57 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire VCC range.
2. Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 1.5 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1T57GW
74AUP1T57GM
40 C to +125 C
40 C to +125 C
SC-88
plastic surface-mounted package; 6 leads
SOT363
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
74AUP1T57GF
74AUP1T57GN
74AUP1T57GS
40 C to +125 C
40 C to +125 C
40 C to +125 C
XSON6
XSON6
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
SOT1202
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AUP1T57GW
74AUP1T57GM
74AUP1T57GF
74AUP1T57GN
74AUP1T57GN
a7
a7
a7
a7
a7
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
A
4
Y
1
B
6
C
001aab583
Fig 1. Logic symbol
74AUP1T57
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 December 2011
2 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
6. Pinning information
6.1 Pinning
74AUP1T57
74AUP1T57
B
GND
A
1
2
3
6
5
4
C
74AUP1T57
1
2
3
6
5
4
B
GND
A
C
B
GND
A
1
2
3
6
5
4
C
V
CC
V
CC
V
CC
Y
Y
Y
001aah471
001aah473
Transparent top view
Transparent top view
001aah472
Fig 2. Pin configuration SOT363
Fig 3. Pin configuration SOT886
Fig 4. Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
1
Description
data input
B
GND
A
2
ground (0 V)
data input
3
Y
4
data output
supply voltage
data input
VCC
C
5
6
7. Functional description
Table 4.
Function table[1]
Input
Output
C
L
B
L
A
L
Y
H
L
L
L
H
L
L
H
H
L
H
L
L
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level.
74AUP1T57
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 December 2011
3 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input AND
see Figure 5
see Figure 8
see Figure 6 and 7
see Figure 6 and 7
see Figure 8
see Figure 5
see Figure 9
see Figure 10
see Figure 11
2-input AND with both inputs inverted
2-input NAND with inverted input
2-input OR with inverted input
2-input NOR
2-input NOR with both inputs inverted
2-input XNOR
Inverter
Buffer
V
CC
V
CC
B
C
B
C
Y
Y
Y
B
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
B
C
B
C
Y
001aab585
001aab584
Fig 5. 2-input AND gate or 2-input NOR gate with
both inputs inverted
Fig 6. 2-input NAND gate with input B inverted or
2-input OR gate with inverted C input
V
CC
V
CC
A
C
A
C
Y
Y
Y
Y
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
C
Y
A
C
A
A
C
A
001aab586
001aab587
Fig 7. 2-input NAND gate with input C inverted or
2-input OR gate with inverted A input
Fig 8. 2-input NOR gate or 2-input AND gate with
both inputs inverted
V
CC
V
CC
B
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
B
C
A
Y
Y
A
Y
001aab588
001aab589
Fig 9. 2-input XNOR gate
Fig 10. Inverter
74AUP1T57
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 December 2011
4 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
V
CC
B
1
2
3
6
5
4
B
Y
Y
001aab590
Fig 11. Buffer
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
0.5
50
0.5
50
0.5
-
Max
+4.6
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
VO
IO
output clamping current
output voltage
VO < 0 V
mA
V
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
20
50
output current
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
50
65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = 40 C to +125 C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 package: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
2.3
0
Max
3.6
Unit
supply voltage
V
VI
input voltage
3.6
V
VO
output voltage
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
40
+125
C
74AUP1T57
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 December 2011
5 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
VT+
VT
VH
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
(VH = VT+ VT)
0.60
0.75
0.35
0.50
-
-
-
-
1.10
1.16
0.60
0.85
V
V
V
V
negative-going threshold
voltage
hysteresis voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.23
0.25
-
-
0.60
0.56
V
V
VOH
HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V
VCC 0.1
2.05
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = VT+ or VT
1.9
2.72
2.6
VOL
LOW-level output voltage
IO = 20 A; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10
0.31
0.44
0.31
0.44
0.1
0.1
0.2
V
V
V
V
V
II
input leakage current
A
A
A
IOFF
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
-
-
1.2
A
VCC = 2.3 V to 3.6 V
[1]
[2]
ICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
VCC = 3.0 V to 3.6 V; IO = 0 A
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
-
-
-
-
-
-
-
A
A
pF
pF
-
CI
input capacitance
output capacitance
0.8
1.7
CO
Tamb = 40 C to +85 C
VT+
VT
VH
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
(VH = VT+ VT)
0.60
0.75
0.35
0.50
-
-
-
-
1.10
1.19
0.60
0.85
V
V
V
V
negative-going threshold
voltage
hysteresis voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.10
0.15
-
-
0.60
0.56
V
V
74AUP1T57
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 December 2011
6 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V
Conditions
Min
Typ
Max
Unit
VCC 0.1
1.97
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = VT+ or VT
1.85
2.67
2.55
VOL
LOW-level output voltage
IO = 20 A; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.33
0.45
0.33
0.45
0.5
0.5
0.5
V
V
V
V
II
input leakage current
A
A
A
IOFF
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.5
A
[1]
[2]
ICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
VCC = 3.0 V to 3.6 V; IO = 0 A
-
-
-
-
4
A
A
12
Tamb = 40 C to +125 C
VT+
VT
VH
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
(VH = VT+ VT)
0.60
0.75
0.33
0.46
-
-
-
-
1.10
1.19
0.64
0.85
V
V
V
V
negative-going threshold
voltage
hysteresis voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.10
0.15
-
-
0.60
0.56
V
V
VOH
HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V
VCC 0.11 -
-
-
-
-
-
V
V
V
V
V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = VT+ or VT
1.77
1.67
2.40
2.30
-
-
-
-
VOL
LOW-level output voltage
IO = 20 A; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
0.11
0.36
0.50
0.36
0.50
0.75
V
V
V
V
V
II
input leakage current
A
74AUP1T57
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 December 2011
7 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
A
IOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
0.75
0.75
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
-
-
3.5
A
VCC = 2.3 V to 3.6 V
[1]
[2]
ICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
VCC = 3.0 V to 3.6 V; IO = 0 A
-
-
-
-
7
A
A
22
[1] One input at 0.3 V or 1.1 V, other input at VCC or GND.
[2] One input at 0.45 V or 1.2 V, other input at VCC or GND.
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C
Typ[1] Max
40 C to +125 C
Unit
Min
Min
Max
Max
(85 C) (125 C)
VCC = 2.3 V to 2.7 V; VI = 1.65 V to 1.95 V
[2]
[2]
[2]
[2]
tpd
propagation delay A, B, C to Y; see Figure 12
CL = 5 pF
CL = 10 pF
CL = 15 pF
CL = 30 pF
2.1
2.6
2.9
3.8
3.6
4.1
4.6
5.8
5.5
6.2
6.8
8.2
0.5
1.0
1.0
1.5
6.8
7.9
7.5
8.7
ns
ns
ns
ns
8.7
9.6
10.8
11.9
VCC = 2.3 V to 2.7 V; VI = 2.3 V to 2.7 V
tpd
propagation delay A, B, C to Y; see Figure 12
CL = 5 pF
CL = 10 pF
CL = 15 pF
CL = 30 pF
1.7
2.1
2.5
3.3
3.4
4.0
4.5
5.6
5.4
6.2
6.7
8.2
0.5
1.0
1.0
1.5
6.0
7.1
6.6
7.9
ns
ns
ns
ns
7.9
8.7
10.0
11.0
VCC = 2.3 V to 2.7 V; VI = 3.0 V to 3.6 V
tpd
propagation delay A, B, C to Y; see Figure 12
CL = 5 pF
CL = 10 pF
CL = 15 pF
CL = 30 pF
1.4
1.8
2.2
3.0
3.2
3.7
4.2
5.4
4.9
5.7
6.3
7.8
0.5
1.0
1.0
1.5
5.5
6.5
7.4
9.5
6.1
7.2
ns
ns
ns
ns
8.2
10.5
VCC = 3.0 V to 3.6 V; VI = 1.65 V to 1.95 V
tpd
propagation delay A, B, C to Y; see Figure 12
CL = 5 pF
CL = 10 pF
CL = 15 pF
CL = 30 pF
2.0
2.5
2.8
3.6
2.9
3.5
3.9
5.1
3.9
4.6
5.2
6.6
0.5
1.0
1.0
1.5
8.0
8.5
9.1
9.8
8.8
9.4
ns
ns
ns
ns
10.1
10.8
74AUP1T57
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 December 2011
8 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min
Typ[1] Max
Min
Max
Max
(85 C) (125 C)
VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V
[2]
[2]
[3]
tpd
propagation delay A, B, C to Y; see Figure 12
CL = 5 pF
CL = 10 pF
CL = 15 pF
CL = 30 pF
1.6
2.0
2.3
3.1
2.8
3.4
3.9
5.0
4.2
4.9
5.5
6.9
0.5
1.0
1.0
1.5
5.3
6.1
6.8
8.5
5.9
6.8
7.5
9.4
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V
tpd
propagation delay A, B, C to Y; see Figure 12
CL = 5 pF
CL = 10 pF
CL = 15 pF
CL = 30 pF
1.3
1.7
2.0
2.8
2.8
3.3
3.8
4.9
4.2
4.9
5.5
7.0
0.5
1.0
1.0
1.5
4.7
5.7
6.2
7.8
5.2
6.3
6.9
8.6
ns
ns
ns
ns
Tamb = 25 C
CPD power dissipation fi = 1 MHz; VI = GND to VCC
capacitance
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
-
-
3.6
4.3
-
-
-
-
-
-
-
-
pF
pF
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
74AUP1T57
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 December 2011
9 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
12. Waveforms
V
I
A, B, C input
GND
V
V
M
M
t
t
PLH
PHL
V
OH
V
V
V
M
Y output
M
V
OL
t
t
PLH
PHL
V
OH
Y output
V
M
M
V
OL
001aab593
Measurement points are given in Table 10.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 12. Input A, B and C to output Y propagation delay times
Table 10. Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
2.3 V to 3.6 V
0.5 VCC
0.5 VI
1.65 V to 3.6 V
3.0 ns
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Product data sheet
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74AUP1T57
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Low-power configurable gate with voltage-level translator
V
V
EXT
CC
5 kΩ
V
V
O
I
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Load
CL
VEXT
[1]
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
2.3 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M
GND
2 VCC
[1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M.
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Product data sheet
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NXP Semiconductors
Low-power configurable gate with voltage-level translator
13. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 14. Package outline SOT363 (SC-88)
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Product data sheet
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12 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 15. Package outline SOT886 (XSON6)
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Product data sheet
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13 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(1)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 16. Package outline SOT891 (XSON6)
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Product data sheet
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NXP Semiconductors
Low-power configurable gate with voltage-level translator
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
SOT1115
b
(2)
(4×)
1
2
3
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 0.95 1.05
0.35 0.40
0.15 0.90 1.00 0.55 0.3 0.30 0.35
0.12 0.85 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1115_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1115
Fig 17. Package outline SOT1115 (XSON6)
74AUP1T57
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Product data sheet
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74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
b
(2)
1
2
3
(4×)
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
0.15 1.00 1.00 0.55 0.35 0.30 0.35
0.12 0.95 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1202_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1202
Fig 18. Package outline SOT1202 (XSON6)
74AUP1T57
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Product data sheet
Rev. 4 — 1 December 2011
16 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
14. Abbreviations
Table 12. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
15. Revision history
Table 13. Revision history
Document ID
74AUP1T57 v.4
Modifications:
74AUP1T57 v.3
74AUP1T57 v.2
74AUP1T57 v.1
Release date
Data sheet status
Change notice
Supersedes
20111201
Product data sheet
-
74AUP1T57 v.3
• Legal pages updated.
20100721
20090803
20080103
Product data sheet
-
-
-
74AUP1T57 v.2
Product data sheet
Product data sheet
74AUP1T57 v.1
-
74AUP1T57
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Product data sheet
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17 of 20
74AUP1T57
NXP Semiconductors
Low-power configurable gate with voltage-level translator
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
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Product data sheet
Rev. 4 — 1 December 2011
18 of 20
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NXP Semiconductors
Low-power configurable gate with voltage-level translator
Non-automotive qualified products — Unless this data sheet expressly
NXP Semiconductors’ specifications such use shall be solely at customer’s
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
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19 of 20
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NXP Semiconductors
Low-power configurable gate with voltage-level translator
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 3
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 December 2011
Document identifier: 74AUP1T57
相关型号：
74AUP1T57GW,125
74AUP1T57 - Low-power configurable gate with voltage-level translator TSSOP 6-Pin
NXP
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