74AUP2G132_技术文档

74AUP2G132

Low-power dual 2-input NAND Schmitt trigger

Rev. 03 — 15 December 2008

Product data sheet

1. General description

The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accept

standard input signals. They are capable of transforming slowly changing input signals

into sharply deﬁned, jitter-free output signals.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backﬂow current through the device

when it is powered down.

The inputs switch at different points for positive and negative-going signals. The difference

between the positive voltage V_T+and the negative voltage V_T−is deﬁned as the input

hysteresis voltage V_H.

2. Features

I Wide supply voltage range from 0.8 V to 3.6 V

I High noise immunity

I ESD protection:

N HBM JESD22-A114E Class 3A exceeds 5000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Low static power consumption; I_CC= 0.9 µA (maximum)

I Latch-up performance exceeds 100 mA per JESD 78 Class II

I Inputs accept voltages up to 3.6 V

I Low noise overshoot and undershoot < 10 % of V_CC

I I_OFFcircuitry provides partial Power-down mode operation

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

3. Applications

I Wave and pulse shaper

I Astable multivibrator

I Monostable multivibrator

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

4. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74AUP2G132DC

74AUP2G132GT

74AUP2G132GD

74AUP2G132GM

−40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package; 8 leads; SOT765-1

body width 2.3 mm

XSON8

plastic extremely thin small outline package; no leads; SOT833-1

8 terminals; body 1 × 1.95 × 0.5 mm

XSON8U plastic extremely thin small outline package; no leads; SOT996-2

8 terminals; UTLP based; body 3 × 2 × 0.5 mm

XQFN8U plastic extremely thin quad ﬂat package; no leads;

SOT902-1

8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm

5. Marking

Table 2.

Marking codes

Type number

74AUP2G132DC

74AUP2G132GT

74AUP2G132GD

74AUP2G132GM

Marking code

aE2

6. Functional diagram

1A

1Y

1B

&

2A

A

&

2Y

Y

2B

B

001aah880

001aah881

001aac532

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram (one gate)

74AUP2G132_3

Product data sheet

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

7. Pinning information

7.1 Pinning

74AUP2G132

1A

1B

1

2

3

4

8

7

6

5

V

CC

1Y

2B

2A

74AUP2G132

2Y

1

2

3

4

8

7

6

5

1A

1B

V

CC

1Y

2B

2A

GND

2Y

GND

001aaf165

Transparent top view

001aaf164

Fig 4. Pin conﬁguration SOT765-1 (VSSOP8)

Fig 5. Pin conﬁguration SOT833-1 (XSON8)

74AUP2G132

terminal 1

index area

1Y

1

7

6

5

1A

1B

2Y

74AUP2G132

1A

1B

1

2

3

4

8

7

6

5

V

CC

2B

2A

2

3

1Y

2B

2A

2Y

GND

001aaf166

001aaj264

Transparent top view

Fig 6. Pin conﬁguration SOT996-2 (XSON8U)

Fig 7. Pin conﬁguration SOT902-1 (XQFN8U)

7.2 Pin description

Table 3.

Symbol

Pin description

Description

SOT765-1, SOT833-1 and SOT996-2 SOT902-1

1A, 2A

1B, 2B

GND

1, 5

2, 6

4

7, 3

6, 2

4

data input

ground (0 V)

data output

supply voltage

1Y, 2Y

V_CC

7, 3

8

1, 5

8

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

3 of 19

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

8. Functional description

Table 4.

Function table^[1]

Input

nA

L

Output

nB

L

nY

H

L

H

L

H

L

[1] H = HIGH voltage level; L = LOW voltage level.

9. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+4.6

−50

+4.6

−50

+4.6

±20

50

Unit

V

supply voltage

input clamping current

input voltage

−0.5

V_I< 0 V

-

mA

V

[1]

V_I

−0.5

I_OK

output clamping current V_O< 0 V

-

mA

V

V_O

output voltage

Active mode and Power-down mode

−0.5

I_O

output current

V_O= 0 V to V_CC

-

mA

°C

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

-

−50

+150

250

storage temperature

total power dissipation

−65

[2]

T_amb= −40 °C to +125 °C

-

mW

[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For VSSOP8 packages: above 110 °C the value of P_totderates linearly with 8.0 mW/K.

For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of P_totderates linearly with 2.4 mW/K.

10. Recommended operating conditions

Table 6.

Symbol

V_CC

Operating conditions

Parameter

Conditions

Min

0.8

0

Max

3.6

Unit

supply voltage

input voltage

V

V_I

3.6

V

V_O

output voltage

Active mode

0

V_CC

3.6

V

Power-down mode; V_CC= 0 V

0

V

T_amb

ambient temperature

−40

+125

°C

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

4 of 19

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

11. Static characteristics

Table 7.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

T_amb= 25 °C

V_OH

HIGH-level output voltage V_I= V_T+or V_T−

I_O= −20 µA; V_CC= 0.8 V to 3.6 V

V

_CC− 0.1

-

V

I_O= −1.1 mA; V_CC= 1.1 V

I_O= −1.7 mA; V_CC= 1.4 V

I_O= −1.9 mA; V_CC= 1.65 V

I_O= −2.3 mA; V_CC= 2.3 V

I_O= −3.1 mA; V_CC= 2.3 V

I_O= −2.7 mA; V_CC= 3.0 V

I_O= −4.0 mA; V_CC= 3.0 V

V_I= V_T+or V_T−

0.75 × V_CC

1.11

1.32

2.05

1.9

2.72

2.6

V_OL

LOW-level output voltage

I_O= 20 µA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

-

0.1

V

0.3 × V_CC

0.31

0.44

0.31

0.44

±0.1

±0.2

V

I_I

input leakage current

µA

I_OFF

∆I_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

additional power-off

leakage current

V_Ior V_O= 0 V to 3.6 V;

_CC= 0 V to 0.2 V

V

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

_CC= 0.8 V to 3.6 V

-

0.5

40

µA

V

[1]

∆I_CC

additional supply current

V_I= V_CC− 0.6 V; I_O= 0 A;

_CC= 3.3 V

V

C_I

input capacitance

output capacitance

V_I= GND or V_CC; V_CC= 0 V to 3.6 V

V_O= GND; V_CC= 0 V

-

1.1

1.7

-

pF

C_O

T_amb= −40 °C to +85 °C

V_OH

HIGH-level output voltage V_I= V_T+or V_T−

I_O= −20 µA; V_CC= 0.8 V to 3.6 V

I_O= −1.1 mA; V_CC= 1.1 V

I_O= −1.7 mA; V_CC= 1.4 V

I_O= −1.9 mA; V_CC= 1.65 V

I_O= −2.3 mA; V_CC= 2.3 V

I_O= −3.1 mA; V_CC= 2.3 V

I_O= −2.7 mA; V_CC= 3.0 V

I_O= −4.0 mA; V_CC= 3.0 V

V

_CC− 0.1

-

V

0.7 × V_CC

1.03

1.30

1.97

1.85

2.67

2.55

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

Table 7.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_OL

LOW-level output voltage

V_I= V_T+or V_T−

I_O= 20 µA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

-

0.1

V

0.3 × V_CC

0.37

0.35

0.33

0.45

0.33

0.45

±0.5

±0.6

V

I_I

input leakage current

µA

I_OFF

∆I_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

additional power-off

leakage current

V_Ior V_O= 0 V to 3.6 V;

_CC= 0 V to 0.2 V

V

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

_CC= 0.8 V to 3.6 V

-

0.9

50

µA

V

[1]

∆I_CC

additional supply current

V_I= V_CC− 0.6 V; I_O= 0 A;

_CC= 3.3 V

V

T_amb= −40 °C to +125 °C

V_OHHIGH-level output voltage V_I= V_T+or V_T−

I_O= −20 µA; V_CC= 0.8 V to 3.6 V

V

_CC− 0.11 -

-

V

I_O= −1.1 mA; V_CC= 1.1 V

I_O= −1.7 mA; V_CC= 1.4 V

I_O= −1.9 mA; V_CC= 1.65 V

I_O= −2.3 mA; V_CC= 2.3 V

I_O= −3.1 mA; V_CC= 2.3 V

I_O= −2.7 mA; V_CC= 3.0 V

I_O= −4.0 mA; V_CC= 3.0 V

V_I= V_T+or V_T−

0.6 × V_CC

0.93

1.17

1.77

1.67

2.40

2.30

-

V_OL

LOW-level output voltage

I_O= 20 µA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

-

0.11

V

0.33 × V_CC

0.41

V

0.39

V

0.36

V

0.50

V

0.36

V

0.50

V

I_I

input leakage current

±0.75

µA

I_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

6 of 19

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

Table 7.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

∆I_OFFadditional power-off

Conditions

Min

Typ

Max

Unit

V_Ior V_O= 0 V to 3.6 V;

-

±0.75

µA

leakage current

V

_CC= 0 V to 0.2 V

V_I= GND or V_CC; I_O= 0 A;

_CC= 0.8 V to 3.6 V

V_I= V_CC− 0.6 V; I_O= 0 A;

_CC= 3.3 V

I_CC

supply current

-

1.4

75

µA

V

[1]

∆I_CC

additional supply current

V

[1] One input at V_CC− 0.6 V, other input at V_CCor GND.

12. Dynamic characteristics

Table 8.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9.

Symbol Parameter

Conditions

T_amb= 25 °C

Min Typ^[1]Max Min

T_amb= −40 °C to +125 °C Unit

Max Max

(85 °C) (125 °C)

C_L= 5 pF

[2]

t_pd

propagation delay nA or nB to nY; see Figure 8

V_CC= 0.8 V

-

22.5

6.3

4.6

3.9

3.2

2.9

-

ns

V_CC= 1.1 V to 1.3 V

2.6

2.2

1.9

1.7

1.6

13.4

8.2

6.6

5.3

4.7

2.4

1.9

1.7

1.5

1.4

15.1

9.7

7.9

6.2

5.6

16.6

10.7

8.7

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

6.8

V_CC= 3.0 V to 3.6 V

6.2

C_L= 10 pF

t_pd

propagation delay nA or nB to nY; see Figure 8

V_CC= 0.8 V

-

26.1

7.2

5.2

4.5

3.8

3.5

-

ns

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

3.0

2.5

2.3

2.1

2.0

15.4

9.3

7.5

6.1

5.5

2.7

2.2

2.0

1.8

17.3

11.0

9.0

19.0

12.1

9.9

7.2

7.9

6.5

7.2

C_L= 15 pF

t_pd

propagation delay nA or nB to nY; see Figure 8

V_CC= 0.8 V

-

29.6

8.0

5.8

5.0

4.2

3.9

-

ns

V_CC= 1.1 V to 1.3 V

3.3

2.8

2.6

2.3

2.2

17.2

10.4

8.3

3.0

2.5

2.3

2.1

2.0

19.4

12.3

10.0

7.9

21.3

13.5

11.0

8.7

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

6.7

V_CC= 3.0 V to 3.6 V

6.1

7.3

8.0

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

7 of 19

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

Table 8.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9.

Symbol Parameter

Conditions

T_amb= 25 °C

Min Typ^[1]Max Min

T_amb= −40 °C to +125 °C Unit

Max Max

(85 °C) (125 °C)

C_L= 30 pF

[2]

t_pd

propagation delay nA or nB to nY; see Figure 8

V_CC= 0.8 V

-

39.9

-

ns

V_CC= 1.1 V to 1.3 V

4.3

3.6

3.2

3.0

2.8

10.2 22.6

3.8

3.2

2.9

2.7

25.4

15.8

12.8

10.1

9.2

27.9

17.4

14.1

11.1

10.1

V_CC= 1.4 V to 1.6 V

7.3

6.3

5.3

5.0

13.3

10.6

8.5

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

7.8

C_L= 5 pF, 10 pF, 15 pF and 30 pF

C_PDpower dissipation f_i= 1 MHz; V_I= GND to V_CC

[3]

capacitance

V_CC= 0.8 V

-

2.6

2.9

3.0

3.2

3.8

4.4

-

pF

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] All typical values are measured at nominal V_CC

.

[2] t_pdis the same as t_PLHand t_PHL

.

[3] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

13. Waveforms

V

T+

V

nA, nB input

M

V

T−

t

PLH

PHL

V

OH

V

nY output

M

V

OL

001aaj265

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 8. The data input (nA or nB) to output (nY) propagation delays

Table 9.

Measurement points

Supply voltage

V_CC

Output

V_M

Input

V_M

V_I

t_r= t_f

0.8 V to 3.6 V

0.5 × V_CC

V_CC

≤ 3.0 ns

V

EXT

CC

5 kΩ

V

O

I

G

DUT

R

T

C

L

R

L

001aac521

Test data is given in Table 10.

Deﬁnitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 9. Load circuitry for switching times

Table 10. Test data

Supply voltage

V_CC

Load

V_EXT

[1]

C_L

R_L

5 kΩ or 1 MΩ

t_PLH, t_PHL

open

t_PZH, t_PHZ

t_PZL, t_PLZ

0.8 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF

GND

2 × V_CC

[1] For measuring enable and disable times R_L= 5 kΩ, for measuring propagation delays, setup and hold times and pulse width R_L= 1 MΩ.

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

9 of 19

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

14. Transfer characteristics

Table 11. Transfer characteristics

Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 9.

Symbol Parameter

Conditions

T_amb= 25 °C

T_amb= −40 °C to +125 °C Unit

Min Typ Max

Min

Max

(85 °C) (125 °C)

V_T+

V_T−

V_H

positive-going

threshold voltage Figure 11

see Figure 10 and

V_CC= 0.8 V

0.30

0.53

0.74

0.91

1.37

1.88

-

0.60

0.90

1.11

1.29

1.77

2.29

0.30

0.53

0.74

0.91

1.37

1.88

0.60

0.90

1.11

1.29

1.77

2.29

0.62

0.92

1.13

1.31

1.80

2.32

V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

negative-going

threshold voltage Figure 11

see Figure 10 and

V_CC= 0.8 V

0.10

0.26

0.39

0.47

0.69

0.88

-

0.60

0.65

0.75

0.84

1.04

1.24

0.10

0.26

0.39

0.47

0.69

0.88

0.60

0.65

0.75

0.84

1.04

1.24

0.60

0.65

0.75

0.84

1.04

1.24

V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

hysteresis voltage (V_T+− V_T−); see Figure 10,

Figure 11, Figure 12 and

Figure 13

V_CC= 0.8 V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

0.07

0.08

0.18

0.27

0.53

0.79

-

0.50

0.46

0.56

0.66

0.92

1.31

0.07

0.08

0.18

0.27

0.53

0.79

0.50

0.46

0.56

0.66

0.92

1.31

0.50

0.46

0.56

0.66

0.92

1.31

V

15. Waveforms transfer characteristics

V

T+

V

O

V

I

V

H

V

T−

V

O

V

I

mna208

V

H

V

T+

T−

mna207

V_T+and V_T−limits at 70 % and 20 %.

Fig 10. Transfer characteristic

Fig 11. Deﬁnition of V_T+, V_T−and V_H

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

001aad691

240

I

CC

(µA)

160

80

0

0.4

0.8

1.2

1.6

2.0

V (V)

I

V_CC= 3.0 V.

Fig 12. Typical transfer characteristics; V_CC= 1.8 V

001aad692

1200

I

CC

(µA)

800

400

0

1.0

2.0

3.0

V (V)

I

V_CC= 3.0 V.

Fig 13. Typical transfer characteristics; V_CC= 3.0 V

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

16. Application information

The slow input rise and fall times cause additional power dissipation, this can be

calculated using the following formula:

P_add= f_i× (t_r× ∆I_CC(AV)+ t_f× ∆I_CC(AV)) × V_CCwhere:

P_add= additional power dissipation (µW);

f_i= input frequency (MHz);

t_r= input rise time (ns); 10 % to 90 %;

t_f= input fall time (ns); 90 % to 10 %;

∆I_CC(AV)= average additional supply current (µA).

Average ∆I_CC(AV)differs with positive or negative input transitions, as shown in Figure 14.

001aad027

0.3

∆I

CC(AV)

(mA)

(1)

(2)

0.2

0.1

0

0.8

1.8

2.8

3.8

V

(V)

CC

(1) Positive-going edge.

(2) Negative-going edge.

Linear change of V_Ibetween 0.8 V and 2.0 V. All values given are typical, unless otherwise speciﬁed.

Fig 14. Average I_CCas a function of V_CC

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

17. Package outline

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

Q

A

2

A

1

(A )

3

pin 1 index

θ

L

p

L

detail X

1

4

e

w

M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

L

p

Q

UNIT

v

w

y

Z

θ

1

2

3

p

E

max.

0.15

0.00

0.85

0.60

0.27

0.17

0.23

0.08

2.1

1.9

2.4

2.2

3.2

3.0

0.40

0.15

0.21

0.19

0.4

0.1

8°

0°

mm

1

0.5

0.12

0.4

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-06-07

SOT765-1

MO-187

Fig 15. Package outline SOT765-1 (VSSOP8)

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

13 of 19

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

SOT833-1

b

1

2

3

4

4×

(2)

L

1

e

8

7

6

5

e

1

e

1

e

1

8×

(2)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

1

UNIT

b

D

E

e

1

L

1

max max

0.25

0.17

2.0

1.9

1.05

0.95

0.35 0.40

0.27 0.32

mm

0.5 0.04

0.6

0.5

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

07-11-14

07-12-07

SOT833-1

- - -

MO-252

Fig 16. Package outline SOT833-1 (XSON8)

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

XSON8U: plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3 x 2 x 0.5 mm

SOT996-2

D

B

A

E

A

1

detail X

terminal 1

index area

e

1

C

M

v

C A

C

B

b

e

L

1

y

w

C

1

4

L

2

L

8

5

X

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

b

D

E

e

1

L

v

w

y

1

2

max

0.05 0.35

0.00 0.15

2.1

1.9

3.1

2.9

0.5

0.3

0.15

0.05

0.6

0.4

mm

0.5

1.5

0.1

0.05 0.05

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

07-12-18

07-12-21

SOT996-2

- - -

Fig 17. Package outline SOT996-2 (XSON8U)

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

XQFN8U: plastic extremely thin quad flat package; no leads;

8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm

SOT902-1

D

B

A

terminal 1

index area

E

A

1

detail X

e

L

1

e

C

y

C

1

y

L

M

v

C A

C

B

4

w

5

6

7

3

2

metal area

not for soldering

e

1

b

e

1

terminal 1

index area

8

X

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

b

D

E

e

1

L

v

w

y

1

max

0.05 0.25 1.65 1.65

0.00 0.15 1.55 1.55

0.35 0.15

0.25 0.05

mm

0.5

0.55

0.5

0.1

0.05 0.05 0.05

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

MO-255

JEITA

05-11-25

07-11-14

SOT902-1

- - -

Fig 18. Package outline SOT902-1 (XQFN8U)

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

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74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

18. Abbreviations

Table 12. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

TTL

Transistor-Transistor Logic

19. Revision history

Table 13. Revision history

Document ID

Release date

20081215

Data sheet status

Change notice

Supersedes

74AUP2G132_3

Modiﬁcations:

Product data sheet

-

74AUP2G132_2

• Added type number 74AUP2G132GD (XSON8U package).

74AUP2G132_2

74AUP2G132_1

20080314

Product data sheet

-

74AUP2G132_1

-

20061018

Product data sheet

-

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

17 of 19

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

20. Legal information

20.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

20.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

20.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

21. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

74AUP2G132_3

Product data sheet

Rev. 03 — 15 December 2008

18 of 19

74AUP2G132

NXP Semiconductors

Low-power dual 2-input NAND Schmitt trigger

22. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

8

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Transfer characteristics. . . . . . . . . . . . . . . . . . 10

Waveforms transfer characteristics. . . . . . . . 10

Application information. . . . . . . . . . . . . . . . . . 12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

9

10

11

12

13

14

15

16

17

18

19

20

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

20.1

20.2

20.3

20.4

21

22

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 December 2008

Document identifier: 74AUP2G132_3


型号：	74AUP2G132
厂家：	NXP
描述：	Low-power dual 2-input NAND Schmitt trigger 低功耗双2输入与非施密特触发器触发器
文件：	总19页 (文件大小：104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AUP2G132 [NXP]

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