74AVC16374DGG,518_技术文档

74AVC16374

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

Rev. 3 — 16 August 2013

Product data sheet

1. General description

The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for

each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374 consist

of 2 sections of 8 edge-triggered flip-flops. A clock input (CP) and an output enable (OE)

are provided per 8-bit section.

The 74AVC16374 is designed to have an extremely fast propagation delay and a

minimum amount of power consumption.

To ensure the high-impedance output state during power-up or power-down, nOE should

be tied to VCC through a pull-up resistor (Live Insertion).

A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line

drive during transient (see Figure 5 and Figure 6).

2. Features and benefits

 Wide supply voltage range from 1.2 V to 3.6 V

 Complies with JEDEC standards:

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-1A (2.7 V to 3.6 V)

 CMOS low power consumption

 Input/output tolerant up to 3.6 V

 Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,

resulting in noise reduction without speed degradation

 Low inductance multiple V_CCand GND pins to minimize noise and ground bounce

 Supports Live Insertion

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74AVC16374DGG

40 C to +85 C

TSSOP48

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

SOT362-1

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

4. Functional diagram

1

1EN

C1

1OE

1CP

2OE

2CP

1

24

48

24

25

1OE

2OE

2EN

C2

2

47

46

44

43

41

40

38

37

36

35

33

32

30

29

27

26

1D0

1Q0

3

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2

3

47

46

44

43

41

40

38

37

36

35

33

32

30

29

27

26

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

1D

1

5

6

5

8

6

9

8

11

12

13

14

16

17

19

20

22

23

9

11

12

13

14

16

17

19

20

22

23

2D

2

1CP

2CP

mna576

48

25

mna577

Fig 1. IEC logic symbol

Fig 2. Logic symbol

1D0

1Q0

D

Q

CP

FF1

1CP

1OE

to 7 other channels

2D0

2Q0

D

Q

CP

FF9

2CP

2OE

to 7 other channels

mna578

Fig 3. Logic diagram

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

2 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

5. Pinning information

5.1 Pinning

74AVC16374

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1OE

1CP

1D0

1D1

GND

1D2

1D3

1Q0

1Q1

GND

1Q2

1Q3

3

4

5

6

7

V

CC

V

CC

8

1Q4

1Q5

GND

1Q6

1Q7

2Q0

2Q1

GND

2Q2

2Q3

1D4

1D5

GND

1D6

1D7

2D0

2D1

GND

2D2

2D3

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

V

CC

V

CC

2Q4

2Q5

GND

2Q6

2Q7

2OE

2D4

2D5

GND

2D6

2D7

2CP

mna575

Fig 4. Pin configuration

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

3 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

5.2 Pin description

Table 2.

Symbol

1OE

Pin description

Description

1

output enable input (active LOW)

3-state flip-flop outputs

ground (0 V)

1Q0 to 1Q7

GND

2, 3, 5, 6, 8, 9, 11, 12

4, 10, 15, 21, 28, 34, 39, 45

V_CC

7, 18, 31, 42

supply voltage

2Q0 to 2Q7

2OE

13, 14, 16, 17, 19, 20, 22, 23

3-state flip-flop outputs

output enable input (active LOW)

clock input

24

2CP

25

2D0 to 2D7

1D0 to 1D7

1CP

36, 35, 33, 32, 30, 29, 27, 26

47, 46, 44, 43, 41, 40, 38, 37

48

data input/output

clock input

6. Functional description

Table 3.

Function table^[1]

Operating modes

Inputs

Internal flip-flops

Outputs

nOE

L

nCp



nDn

nQn

L

Load and read register

Load register and disable outputs

I

L



h

I

H

L

H



Z

H



h

H

Z

[1] H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition

Z = high-impedance OFF-state

 = LOW-to-HIGH CP transition

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

4 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5



Max

+4.6

50

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

0.5

50

0.5

-

+4.6

-

I_OK

output clamping current

output voltage

V_O< 0 V

mA

V

[1]

V_O

output HIGH or LOW

output 3-state

V_O= 0 V to V_CC

V_CC+ 0.5

+4.6

50

V

I_O

output current

mA

C

I_CC

I_GND

T_stg

P_tot

supply current

-

+100

-

ground current

100

65

-

storage temperature

total power dissipation

+150

500

[2]

T_amb= 40 C to +85 C

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Above 60 C, the value of P_totderates linearly with 5.5 mW/K.

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Symbol Parameter

Conditions

Min

1.4

1.65

2.3

3.0

1.2

0

Typ

Max

Unit

V_CC

supply voltage

according to JEDEC Low Voltage Standards

-

1.6

1.95

2.7

3.6

V_CC

3.6

+85

40

V

for low-voltage applications

V

V_I

input voltage

V

V_O

output voltage

output HIGH or LOW

output 3-state

0

V

0

V

T_amb

ambient temperature

in free air

40

0

C

ns/V

t/V

input transition rise and fall

rate

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 2.3 V

V_CC= 2.3 V to 3.0 V

V_CC= 3.0 V to 3.6 V

0

30

0

20

0

10

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

5 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

T_amb= 40 C to +85 C

V_IH

HIGH-level input voltage

V_CC= 1.2 V

V_CC

-

V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 1.2 V

0.65  V_CC

0.9

1.2

1.5

-

0.65  V_CC

-

1.7

-

2.0

V_IL

LOW-level input voltage

-

GND

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

0.9

1.2

1.5

0.35  V_CC

0.7

0.8

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= 100 A; V_CC= 1.65 V to 3.6 V V_CC 0.20

V_CC

-

V

I_O= 3 mA; V_CC= 1.4 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

V_CC 0.35 V_CC 0.23

V_CC 0.45 V_CC 0.25

V_CC 0.55 V_CC 0.38

V_CC 0.70 V_CC 0.48

V_OL

LOW-level output voltage

I_O= 100 A; V_CC= 1.65 V to 3.6 V

I_O= 3 mA; V_CC= 1.4 V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 3.0 V

-

GND

0.10

0.26

0.36

0.1

0.20

0.35

0.45

0.55

0.70

2.5

V

I_I

input leakage current

per pin; V_I= V_CCor GND;

V_CC= 1.4 V to 3.6 V

A

I_OFF

I_OZ

power-off leakage current

OFF-state output current

V_Ior V_O= 3.6 V; V_CC= 0.0 V

V_I= V_IHor V_IL; V_O= V_CCor GND

V_CC= 1.4 V to 2.7 V

-

0.1

10

A

-

0.1

5

A

V_CC= 3.0 V to 3.6 V

10

I_CC

supply current

V_I= V_CCor GND; I_O= 0 A

V_CC= 1.4 V to 2.7 V

-

0.1

0.2

5

20

40

-

A

pF

V_CC= 3.0 V to 3.6 V

C_I

input capacitance

[1] All typical values are measured at T_amb= 25 C.

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

6 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

9.1 Graphs

mna506

mna507

0

300

I

OL

(mA)

OH

(mA)

3.3 V

1.8 V

2.5 V

-100

-200

-300

200

2.5 V

100

1.8 V

3.3 V

0

1

2

3

4

0

1

2

3

4

V

(V)

V

(V)

OL

OH

Fig 5. Output voltage as a function of the HIGH-level

output current.

Fig 6. Output voltage as a function of the LOW-level

output current.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). t_r= t_f 2 ns. For test circuit, see Figure 10.

Symbol Parameter

Conditions

40 C to +85 C

Unit

Min

Typ^[2]

Max

[1]

t_pd

t_en

t_dis

propagation delay

nCP to nQn; see Figure 7

V_CC= 1.2 V

-

3.1

2.4

2.0

1.5

1.3

-

ns

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

nOE to nQn, nBn; see Figure 8

V_CC= 1.2 V

1.2

1.0

0.8

0.7

8.4

6.7

4.1

3.3

enable time

-

5.4

3.9

3.3

2.3

2.0

-

ns

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

nOE to nQn; see Figure 8

V_CC= 1.2 V

1.6

2.3

0.9

0.7

8.5

6.7

4.3

3.4

disable time

-

5.6

4.5

3.3

1.8

2.0

-

ns

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

2.5

1.8

1.0

1.2

9.4

7.8

4.2

3.9

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

7 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). t_r= t_f 2 ns. For test circuit, see Figure 10.

Symbol Parameter

Conditions

40 C to +85 C

Unit

Min

Typ^[2]

Max

t_W

pulse width

HIGH; nCP; see Figure 7

V_CC= 1.2 V

-

0.8

0.5

0.3

0.2

-

ns

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

nDn to nCP; see Figure 8

V_CC= 1.2 V

-

3.1

2.5

t_su

set-up time

-

0.6

0.3

0.2

0.1

-

ns

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

nDn to nCP; see Figure 8

V_CC= 1.2 V

2.7

1.9

1.4

t_h

hold time

-

0.8

0.7

0.6

0.5

0.4

-

ns

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

see Figure 8

1.3

1.2

1.1

f_max

maximum frequency

V_CC= 1.2 V

-

250

300

320

350

-

MHz

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

per input; V_I= GND to V_CC

outputs enabled

-

160

200

[3]

C_PD

power dissipation

capacitance

-

66

1

-

pF

outputs disabled

[1] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[2] Typical values are measured at T_amb= 25 C and V_CC= 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V respectively.

[3] _PDis used to determine the dynamic power dissipation (P_Din W).

.

C

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs.

74AVC16374

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 August 2013

8 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

11. Waveforms

1/f

max

V

I

nCP input

V

t

V

t

M

GND

t

W

PHL

PLH

V

OH

nQn output

V

M

V

OL

mna579

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 7. Clock input (nCP) to output (nQn) propagation delays

V

I

nOE input

V

M

GND

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

mna478

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 8. 3-state enable and disable times

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

9 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

V

I

V

M

nCP input

nDn input

GND

t

su

t

su

t

h

t

h

V

I

V

M

GND

V

OH

V

nQn output

M

V

OL

mna580

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 9. Data set-up and hold times for nDn input to nCP input

Table 8.

Measurement points

Supply voltage

V_CC

V_M

Input

V_I

t_r= t_f

V_X

V_Y

1.2 V

0.5  V_CC

V_CC

 2 ns

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH 0.15 V

V_OH 0.3 V

1.4 V to 1.6 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3.0 V to 3.6 V

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

10 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 10. Test circuit for measuring switching times

Table 9.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

 2 ns

15 pF

30 pF

2 k

1 k

500 

1.4 V to 1.6 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3.0 V to 3.6 V

open

GND

open

GND

open

GND

open

GND

74AVC16374

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Product data sheet

Rev. 3 — 16 August 2013

11 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

12. Package outline

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

D

E

A

X

c

v

A

H

E

y

Z

48

25

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

24

detail X

w

b

p

e

0

5 mm

2.5

scale

Dimensions (mm are the original dimensions)

(1)

(2)

Unit

max

A

b

c

D

E

e

H

L

1

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

°

8

0

0.15 1.05

0.05 0.85

0.28 0.2 12.6 6.2

0.17 0.1 12.4 6.0

8.3

7.9

0.8 0.50

0.4 0.35

0.8

mm nom 1.2

min

0.25

0.5

0.25 0.08 0.1

°

0.4

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

sot362-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

03-02-19

13-08-05

SOT362-1

MO-153

Fig 11. Package outline SOT362-1 (TSSOP48)

74AVC16374

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 August 2013

12 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

74AVC16374 v.3

Modifications:

Release date Data sheet status

20130816 Product data sheet

Change notice Order number Supersedes

74AVC16374 v.2

-

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

74AVC16374 v.2

74AVC16374 v.1

20000309

Product specification

-

74AVC16374 v.1

19981211

Product specification

-

74AVC16374

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 August 2013

13 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74AVC16374

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 August 2013

14 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74AVC16374

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 16 August 2013

15 of 16

74AVC16374

NXP Semiconductors

16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

7

8

9

9.1

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 15

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 August 2013

Document identifier: 74AVC16374


型号：	74AVC16374DGG,518
厂家：	NXP
描述：	74AVC16374 - 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state TSSOP 48-Pin 驱动光电二极管逻辑集成电路
文件：	总16页 (文件大小：747K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AVC16374DGG,518 [NXP]

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