74AVC8T245PW,118_技术文档

74AVC8T245

8-bit dual supply translating transceiver with conﬁgurable

voltage translation; 3-state

Rev. 02 — 28 April 2009

Product data sheet

1. General description

The 74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level

translation. It features two data input-output ports (An and Bn), a direction control input

(DIR), a output enable input (OE) and dual supply pins (V_CC(A)and V_CC(B)). Both V_CC(A)

and V_CC(B)can be supplied at any voltage between 0.8 V and 3.6 V making the device

suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,

2.5 V and 3.3 V). Pins An, OE and DIR are referenced to V_CC(A)and pins Bn are

referenced to V_CC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on

DIR allows transmission from Bn to An. The output enable input (OE) can be used to

disable the outputs so the buses are effectively isolated.

The device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing any damaging backﬂow current through the

device when it is powered down. In suspend mode when either V_CC(A)or V_CC(B)are at

GND level, both An and Bn are in the high-impedance OFF-state.

2. Features

I Wide supply voltage range:

N V_CC(A): 0.8 V to 3.6 V

N V_CC(B): 0.8 V to 3.6 V

I Complies with JEDEC standards:

N JESD8-12 (0.8 V to 1.3 V)

N JESD8-11 (0.9 V to 1.65 V)

N JESD8-7 (1.2 V to 1.95 V)

N JESD8-5 (1.8 V to 2.7 V)

N JESD8-B (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E Class 3B exceeds 8000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Maximum data rates:

N 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

N 260 Mbit/s (≥ 1.1 V to 3.3 V translation)

N 260 Mbit/s (≥ 1.1 V to 2.5 V translation)

N 210 Mbit/s (≥ 1.1 V to 1.8 V translation)

N 150 Mbit/s (≥ 1.1 V to 1.5 V translation)

N 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

I Suspend mode

I Latch-up performance exceeds 100 mA per JESD 78 Class II

I Inputs accept voltages up to 3.6 V

I I_OFFcircuitry provides partial Power-down mode operation

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range Name

Type number

Description

Version

74AVC8T245PW −40 °C to +125 °C

TSSOP24

plastic thin shrink small outline package; 24 leads;

body width 4.4 mm

SOT355-1

74AVC8T245BQ −40 °C to +125 °C

DHVQFN24 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 24 terminals;

body 3.5 × 5.5 × 0.85 mm

SOT815-1

4. Functional diagram

B1

21

B2

20

B3

19

B4

18

B5

17

B6

16

B7

15

B8

14

V

CC(B)

CC(A)

22

OE

2

DIR

3

A1

4

5

6

7

8

9

10

A8

A2

A3

A4

A5

A6

A7

001aai472

Fig 1. Logic symbol

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

2 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

DIR

A1

OE

B1

V

CC(B)

CC(A)

to other seven channels

001aai473

Fig 2. Logic diagram (one channel)

5. Pinning information

5.1 Pinning

74AVC8T245

terminal 1

index area

74AVC8T245

2

3

23

22

21

20

19

18

17

16

15

14

DIR

A1

V

CC(B)

1

2

24

23

22

21

20

19

18

17

16

15

14

13

V

CC(A)

DIR

CC(B)

OE

B1

B2

B3

B4

B5

B6

B7

B8

4

A2

3

A1

A2

OE

B1

B2

B3

B4

B5

B6

B7

B8

GND

5

A3

4

6

A4

5

A3

7

A5

6

A4

8

A6

7

A5

9

A7

8

A6

(1)

10

11

A8

GND

9

A7

GND

10

11

12

A8

GND

001aai490

001aai489

Transparent top view

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 3. Pin conﬁguration TSSOP24

Fig 4. Pin conﬁguration DHVQFN24

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

3 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

5.2 Pin description

Table 2.

Symbol

V_CC(A)

DIR

Pin description

Description

1

supply voltage A (An, OE and DIR inputs are referenced to V_CC(A))

2

direction control

data input or output

ground (0 V)

A1 to A8

GND^[1]

B1 to B8

OE

3, 4, 5, 6, 7, 8, 9, 10

11

12

13

ground (0 V)

21, 20, 19, 18, 17, 16, 15, 14 data input or output

22

23

24

output enable input (active LOW)

V_CC(B)

supply voltage B (Bn inputs are referenced to V_CC(B)

)

[1] All GND pins must be connected to ground (0 V).

6. Functional description

Table 3.

Function table^[1]

Supply voltage

V_CC(A), V_CC(B)

0.8 V to 3.6 V

GND^[3]

Input

OE^[2]

Input/output^[3]

DIR^[2]

An^[2]

An = Bn

input

Z

Bn

L

input

L

H

X

Bn = An

H

X

Z

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

[2] The An, DIR and OE input circuit is referenced to V_CC(A); The Bn input circuit is referenced to V_CC(B)

[3] If at least one of V_CC(A)or V_CC(B)is at GND level, the device goes into suspend mode.

.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC(A)

V_CC(B)

I_IK

Parameter

Conditions

Min

−0.5

−50

−0.5

−50

−0.5

-

Max

+4.6

-

Unit

V

supply voltage A

supply voltage B

input clamping current

input voltage

V

V_I< 0 V

mA

V

[1]

V_I

+4.6

-

I_OK

output clamping current

output voltage

V_O< 0 V

mA

V

[1][2][3]

[1]

V_O

Active mode

V_CCO+ 0.5

+4.6

±50

Suspend or 3-state mode

V_O= 0 V to V_CC

I_CC(A)or I_CC(B)

V

I_O

output current

supply current

mA

I_CC

-

100

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

4 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

Table 4.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

I_GND

Parameter

Conditions

Min

−100

−65

-

Max

-

Unit

mA

°C

ground current

T_stg

storage temperature

total power dissipation

+150

500

[4]

P_tot

T_amb= −40 °C to +125 °C

mW

[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] V_CCOis the supply voltage associated with the output port.

[3] V_CCO+ 0.5 V should not exceed 4.6 V.

[4] For TSSOP24 package: P_totderates linearly at 5.5 mW/K above 60 °C.

For DHVQFN24 package: P_totderates linearly at 4.5 mW/K above 60 °C.

8. Recommended operating conditions

Table 5.

Symbol

V_CC(A)

V_CC(B)

V_I

Recommended operating conditions

Parameter

Conditions

Min

0.8

0

Max

3.6

Unit

V

supply voltage A

supply voltage B

input voltage

3.6

V

3.6

V

[1]

[2]

V_O

output voltage

Active mode

0

V_CCO

3.6

V

Suspend or 3-state mode

0

V

T_amb

ambient temperature

−40

-

+125

5

°C

ns/V

∆t/∆V

input transition rise and fall rate

V_CCI= 0.8 V to 3.6 V

[1] V_CCOis the supply voltage associated with the output port.

[2] V_CCIis the supply voltage associated with the input port.

9. Static characteristics

Table 6.

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Typical static characteristics at T_amb= 25 °C^[1][2]

Symbol Parameter Conditions

V_OHHIGH-level output voltage V_I= V_IHor V_IL

I_O= −1.5 mA; V_CC(A)= V_CC(B)= 0.8 V

V_I= V_IHor V_IL

Min

Typ

0.69

0.07

Max

Unit

-

V

V_OL

LOW-level output voltage

I_O= 1.5 mA; V_CC(A)= V_CC(B)= 0.8 V

-

I_I

input leakage current

DIR, OE input; V_I= 0 V or 3.6 V;

±0.025 ±0.25 µA

V

_CC(A)= V_CC(B)= 0.8 V to 3.6 V

A or B port; V_O= 0 V or V_CCO

_CC(A)= V_CC(B)= 3.6 V

suspend mode A port; V_O= 0 V or V_CCO

_CC(A)= 3.6 V; V_CC(B)= 0 V

suspend mode B port; V_O= 0 V or V_CCO

_CC(A)= 0 V; V_CC(B)= 3.6 V

[3]

I_OZ

OFF-state output current

;

-

±0.5

±2.5

µA

V

;

V

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

5 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

Table 6.

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Typical static characteristics at T_amb= 25 °C^[1][2]…continued

Symbol Parameter Conditions

power-off leakage current A port; V_Ior V_O= 0 V to 3.6 V;

_CC(A)= 0 V; V_CC(B)= 0.8 V to 3.6 V

B port; V_Ior V_O= 0 V to 3.6 V;

_CC(B)= 0 V; V_CC(A)= 0.8 V to 3.6 V

DIR, OE input; V_I= 0 V or 3.3 V;

_CC(A)= V_CC(B)= 3.3 V

A and B port; V_O= 3.3 V or 0 V;

_CC(A)= V_CC(B)= 3.3 V

Min

Typ

Max

Unit

I_OFF

-

±0.1

±1

µA

V

-

±0.1

1.5

±1

-

µA

pF

V

C_I

input capacitance

V

C_I/O

input/output capacitance

4.3

-

V

[1] V_CCOis the supply voltage associated with the output port.

[2] V_CCIis the supply voltage associated with the data input port.

[3] For I/O ports, the parameter I_OZincludes the input leakage current.

Table 7.

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Static characteristics ^[1][2]

Symbol Parameter

Conditions

−40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Max

Min

Max

V_IH

HIGH-level

data input

input voltage

V_CCI= 0.8 V

0.70V_CCI

0.65V_CCI

1.6

-

0.70V_CCI

0.65V_CCI

1.6

-

V

V_CCI= 1.1 V to 1.95 V

V_CCI= 2.3 V to 2.7 V

V_CCI= 3.0 V to 3.6 V

DIR, OE input

2

V_CC(A)= 0.8 V

0.70V_CC(A)

-

0.70V_CC(A)

-

V

V_CC(A)= 1.1 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

data input

0.65V_CC(A)

1.6

2

1.6

2

V_IL

LOW-level

input voltage

V_CCI= 0.8 V

-

0.30V_CCI

0.35V_CCI

0.7

-

0.30V_CCI

0.35V_CCI

0.7

V

V_CCI= 1.1 V to 1.95 V

V_CCI= 2.3 V to 2.7 V

V_CCI= 3.0 V to 3.6 V

DIR, OE input

0.8

V_CC(A)= 0.8 V

-

0.30V_CC(A)

0.35V_CC(A)

0.7

-

0.30V_CC(A)

0.35V_CC(A)

0.7

V

V_CC(A)= 1.1 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

0.8

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

6 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

[1][2]

Table 7.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

−40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Max

Min

Max

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= −100 µA;

V

_CCO− 0.1

0.85

1.05

1.2

-

V

_CCO− 0.1

0.85

1.05

1.2

-

V

_CC(A)= V_CC(B)= 0.8 V to 3.6 V

I_O= −3 mA;

_CC(A)= V_CC(B)= 1.1 V

I_O= −6 mA;

_CC(A)= V_CC(B)= 1.4 V

I_O= −8 mA;

_CC(A)= V_CC(B)= 1.65 V

I_O= −9 mA;

_CC(A)= V_CC(B)= 2.3 V

I_O= −12 mA;

_CC(A)= V_CC(B)= 3.0 V

V

1.75

2.3

1.75

2.3

V

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 100 µA;

-

0.1

0.25

0.35

0.45

0.55

0.7

-

0.1

0.25

0.35

0.45

0.55

0.7

V

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

I_O= 3 mA;

V

_CC(A)= V_CC(B)= 1.1 V

I_O= 6 mA;

_CC(A)= V_CC(B)= 1.4 V

I_O= 8 mA;

_CC(A)= V_CC(B)= 1.65 V

I_O= 9 mA;

_CC(A)= V_CC(B)= 2.3 V

I_O= 12 mA;

_CC(A)= V_CC(B)= 3.0 V

input leakage DIR, OE input; V_I= 0 V or 3.6 V;

V

I_I

±1

±5

µA

current

V

_CC(A)= V_CC(B)= 0.8 V to 3.6 V

A or B port; V_O= 0 V or V_CCO

_CC(A)= V_CC(B)= 3.6 V

suspend mode A port;

V_O= 0 V or V_CCO; V_CC(A)= 3.6 V;

_CC(B)= 0 V

[3]

I_OZ

OFF-state

output current

;

±5

±30

V

±5

V

[3]

suspend mode B port;

-

±5

-

±30

µA

V_O= 0 V or V_CCO; V_CC(A)= 0 V;

V

_CC(B)= 3.6 V

A port; V_Ior V_O= 0 V to 3.6 V;

_CC(A)= 0 V; V_CC(B)= 0.8 V to 3.6 V

B port; V_Ior V_O= 0 V to 3.6 V;

_CC(B)= 0 V; V_CC(A)= 0.8 V to 3.6 V

I_OFF

power-off

leakage

current

-

±5

-

±30

µA

V

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

7 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

[1][2]

Table 7.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C

−40 °C to +125 °C

Unit

Min

Max

Min

Max

I_CC

supply current A port; V_I= 0 V or V_CCI; I_O= 0 A

V_CC(A)= 0.8 V to 3.6 V;

-

10

8

-

55

50

µA

V

_CC(B)= 0.8 V to 3.6 V

V_CC(A)= 1.1 V to 3.6 V;

_CC(B)= 1.1 V to 3.6 V

V

V_CC(A)= 3.6 V; V_CC(B)= 0 V

V_CC(A)= 0 V; V_CC(B)= 3.6 V

B port; V_I= 0 V or V_CCI; I_O= 0 A

V_CC(A)= 0.8 V to 3.6 V;

-

8

-

50

-

µA

−2

−12

-

10

8

-

55

50

µA

V

_CC(B)= 0.8 V to 3.6 V

V_CC(A)= 1.1 V to 3.6 V;

_CC(B)= 1.1 V to 3.6 V

V

V_CC(A)= 3.6 V; V_CC(B)= 0 V

V_CC(A)= 0 V; V_CC(B)= 3.6 V

A plus B port (I_CC(A)+ I_CC(B));

−2

-

−12

-

µA

8

-

50

70

-

20

I_O= 0 A; V_I= 0 V or V_CCI

;

V

_CC(A)= 0.8 V to 3.6 V;

_CC(B)= 0.8 V to 3.6 V

A plus B port (I_CC(A)+ I_CC(B));

I_O= 0 A; V_I= 0 V or V_CCI

-

16

-

65

µA

;

V

_CC(A)= 1.1 V to 3.6 V;

_CC(B)= 1.1 V to 3.6 V

[1] V_CCOis the supply voltage associated with the output port.

[2] V_CCIis the supply voltage associated with the data input port.

[3] For I/O ports, the parameter I_OZincludes the input leakage current.

Table 8.

V_CC(A)

Typical total supply current (I_CC(A)+ I_CC(B)

)

V_CC(B)

Unit

0 V

0

0.8 V

0.1

0.3

1.6

1.2 V

0.1

0.8

1.5 V

0.1

0.4

1.8 V

2.5 V

0.1

0.3

0.1

3.3 V

0.1

1.6

0.8

0.4

0.2

0.1

0 V

0.1

0.2

µA

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.1

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

8 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

10. Dynamic characteristics

Table 9.

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6

Typical dynamic characteristics at V_CC(A)= 0.8 V and T_amb= 25 °C ^[1]

Symbol Parameter

Conditions

V_CC(B)

1.5 V

Unit

0.8 V

14.4

16.2

17.6

21.9

22.2

1.2 V

7.0

1.8 V

6.0

2.5 V

5.9

3.3 V

6.0

t_pd

t_dis

t_en

propagation delay An to Bn

6.2

12.1

16.2

9.0

ns

Bn to An

OE to An

OE to Bn

OE to An

OE to Bn

12.4

16.2

10.0

21.9

11.1

11.9

16.2

9.1

11.8

16.2

8.7

11.8

16.2

9.3

disable time

enable time

21.9

9.8

21.9

9.4

21.9

9.4

21.9

9.6

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH

.

Table 10. Typical dynamic characteristics at V_CC(B)= 0.8 V and T_amb= 25 °C ^[1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6

Symbol Parameter

Conditions

V_CC(A)

1.5 V

Unit

0.8 V

14.4

16.2

17.6

21.9

22.2

1.2 V

12.4

7.0

1.8 V

11.9

6.0

2.5 V

11.8

5.9

3.3 V

11.8

6.0

t_pd

t_dis

t_en

propagation delay An to Bn

12.1

6.2

ns

Bn to An

OE to An

OE to Bn

OE to An

OE to Bn

disable time

enable time

5.9

4.4

4.2

3.1

3.5

14.2

6.4

13.7

4.4

13.6

3.5

13.3

2.6

13.1

2.3

17.7

17.2

17.0

16.8

16.7

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH

.

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

9 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

Table 11. Typical power dissipation capacitance at V_CC(A)= V_CC(B)and T_amb= 25 °C ^[1][2]

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

V_CC(A)= V_CC(B)

Unit

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

C_PD

power dissipation A port: (direction An to

0.2

0.3

0.4

0.5

pF

capacitance

Bn); output enabled

A port: (direction An to

Bn); output disabled

0.2

9

0.2

9

0.2

10

0.3

10

0.4

11

0.5

13

A port: (direction Bn to

An); output enabled

A port: (direction Bn to

An); output disabled

0.6

9

0.6

9

0.6

10

0.7

10

0.7

11

0.8

13

B port: (direction An to

Bn); output enabled

B port: (direction An to

Bn); output disabled

0.6

0.2

0.6

0.2

0.6

0.2

0.7

0.3

0.7

0.4

0.8

0.5

B port: (direction Bn to

An); output enabled

B port: (direction Bn to

An); output disabled

[1] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

[2] f_i= 10 MHz; V_I= GND to V_CC; t_r= t_f= 1 ns; C_L= 0 pF; R_L= ∞ Ω.

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

10 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C ^[1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.

Symbol Parameter

Conditions

V_CC(B)

Unit

1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

V_CC(A)= 1.1 V to 1.3 V

t_pd

t_dis

t_en

propagation An to Bn

0.5

1.1

9.0

0.5

1.1

6.7

8.5

0.5

1.1

5.8

8.3

0.5

1.1

1.0

4.9

8.0

0.5

1.1

1.0

4.8 ns

7.8 ns

11.8 ns

8.9 ns

14.4 ns

7.3 ns

delay

Bn to An

disable time OE to An

OE to Bn

11.8

12.3

14.4

14.2

11.8

9.5

11.8

9.4

11.8

8.0

enable time OE to An

OE to Bn

14.4

10.4

14.4

9.0

14.4

7.7

V_CC(A)= 1.4 V to 1.6 V

t_pd

t_dis

t_en

propagation An to Bn

delay

0.5

1.1

8.5

6.7

0.5

1.1

5.6

8.6

8.4

8.7

8.1

0.5

1.1

4.7

5.3

8.6

7.6

8.7

7.1

0.5

1.1

1.0

4.4

5.2

8.6

7.2

8.7

5.6

0.5

1.1

1.0

4.1 ns

5.0 ns

8.6 ns

7.8 ns

8.7 ns

5.2 ns

Bn to An

disable time OE to An

OE to Bn

8.6

11.2

8.7

enable time OE to An

OE to Bn

12.8

V_CC(A)= 1.65 V to 1.95 V

t_pd

t_dis

t_en

propagation An to Bn

delay

0.5

1.0

1.1

8.3

5.8

0.5

1.0

1.1

5.3

4.7

7.1

7.8

6.8

8.2

0.5

1.0

4.5

7.1

6.9

6.8

6.7

0.5

1.0

0.5

3.8

4.3

7.1

6.0

6.8

5.1

0.5

1.0

0.5

3.5 ns

4.1 ns

7.1 ns

5.8 ns

6.8 ns

4.5 ns

Bn to An

disable time OE to An

OE to Bn

7.1

10.9

6.8

enable time OE to An

OE to Bn

12.4

V_CC(A)= 2.3 V to 2.7 V

t_pd

t_dis

t_en

propagation An to Bn

delay

0.5

1.1

8.0

4.9

0.5

1.1

5.2

4.4

5.1

7.1

4.8

7.9

0.5

4.3

3.8

5.1

6.3

4.8

6.4

0.5

3.3

5.1

4.8

4.6

0.5

2.9 ns

3.1 ns

5.1 ns

5.2 ns

4.8 ns

4.0 ns

Bn to An

disable time OE to An

OE to Bn

5.1

10.4

4.8

enable time OE to An

OE to Bn

11.9

V_CC(A)= 3.0 V to 3.6 V

t_pd

t_dis

t_en

propagation An to Bn

delay

0.5

1.1

7.8

4.8

0.5

1.1

5.0

4.1

4.9

6.9

4.0

7.8

0.5

4.1

3.5

4.9

6.0

4.0

6.2

0.5

3.1

2.9

4.9

4.8

4.0

4.5

0.5

2.7 ns

4.9 ns

5.0 ns

4.0 ns

3.9 ns

Bn to An

disable time OE to An

OE to Bn

4.9

10.1

4.0

enable time OE to An

OE to Bn

11.7

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH

.

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

11 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C ^[1]

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6

Symbol Parameter

Conditions

V_CC(B)

Unit

1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

V_CC(A)= 1.1 V to 1.3 V

t_pd

t_dis

t_en

propagation An to Bn

0.5

1.1

9.9

0.5

1.1

7.4

9.4

0.5

1.1

6.4

9.2

0.5

1.1

1.0

5.4

8.8

0.5

1.1

1.0

5.3 ns

8.6 ns

13.0 ns

9.8 ns

15.9 ns

8.1 ns

delay

Bn to An

disable time OE to An

OE to Bn

13.0

13.6

15.9

15.7

13.0

10.5

15.9

11.5

13.0

10.4

15.9

9.9

13.0

8.8

enable time OE to An

OE to Bn

15.9

8.5

V_CC(A)= 1.4 V to 1.6 V

t_pd

t_dis

t_en

propagation An to Bn

delay

0.5

1.1

9.4

7.4

0.5

1.1

6.2

9.5

9.3

9.6

9.0

0.5

1.1

5.2

5.9

9.5

8.4

9.6

7.9

0.5

1.1

1.0

4.9

5.8

9.5

8.0

9.6

6.2

0.5

1.1

1.0

4.6 ns

5.5 ns

9.5 ns

8.6 ns

9.6 ns

5.8 ns

Bn to An

disable time OE to An

OE to Bn

9.5

12.4

9.6

enable time OE to An

OE to Bn

14.1

V_CC(A)= 1.65 V to 1.95 V

t_pd

t_dis

t_en

propagation An to Bn

delay

0.5

1.0

1.1

9.2

6.4

0.5

1.0

1.1

5.9

5.2

7.9

8.6

7.5

9.1

0.5

1.0

5.0

7.9

7.6

7.5

7.4

0.5

1.0

0.5

4.2

4.8

7.9

6.6

7.5

5.7

0.5

1.0

0.5

3.9 ns

4.6 ns

7.9 ns

6.4 ns

7.5 ns

5.0 ns

Bn to An

disable time OE to An

OE to Bn

7.9

12.0

7.5

enable time OE to An

OE to Bn

13.7

V_CC(A)= 2.3 V to 2.7 V

t_pd

t_dis

t_en

propagation An to Bn

delay

0.5

1.1

8.8

5.4

0.5

1.1

5.8

4.9

5.7

7.9

5.3

8.7

0.5

4.8

4.2

5.7

7.0

5.3

7.1

0.5

3.7

5.7

5.3

5.1

0.5

3.2 ns

3.5 ns

5.7 ns

5.8 ns

5.3 ns

4.4 ns

Bn to An

disable time OE to An

OE to Bn

5.7

11.5

5.3

enable time OE to An

OE to Bn

13.1

V_CC(A)= 3.0 V to 3.6 V

t_pd

t_dis

t_en

propagation An to Bn

delay

0.5

1.1

8.6

5.3

0.5

1.1

5.5

4.6

5.4

7.6

4.4

8.6

0.5

4.6

3.9

5.4

6.6

4.4

6.9

0.5

3.5

3.2

5.4

5.3

4.4

5.0

0.5

3.0 ns

5.4 ns

5.5 ns

4.4 ns

4.3 ns

Bn to An

disable time OE to An

OE to Bn

5.4

11.2

4.4

enable time OE to An

OE to Bn

12.9

[1] t_pdis the same as t_PLHand t_PHL; t_disis the same as t_PLZand t_PHZ; t_enis the same as t_PZLand t_PZH

.

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

12 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

11. Waveforms

V

I

V

An, Bn input

GND

M

t

PLH

PHL

V

OH

V

Bn, An output

M

V

OL

001aai475

Measurement points are given in Table 14.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 5. The data input (An, Bn) to output (Bn, An) propagation delay times

V

I

OE input

V

M

t

GND

t

PLZ

PZL

V

CCO

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

001aai474

Measurement points are given in Table 14.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 6. Enable and disable times

Table 14. Measurement points

Supply voltage

V_CC(A), V_CC(B)

0.8 V to 1.6 V

1.65 V to 2.7 V

3.0 V to 3.6 V

Input^[1]

Output^[2]

V_M

V_X

V_OL+ 0.1 V

V_Y

0.5V_CCI

0.5V_CCO

V

_OH− 0.1 V

V_OL+ 0.15 V

V_OL+ 0.3 V

_OH− 0.15 V

_OH− 0.3 V

[1] V_CCIis the supply voltage associated with the data input port.

[2] V_CCOis the supply voltage associated with the output port.

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

13 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

V

CC

R

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 15.

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance.

V_EXT= External voltage for measuring switching times.

Fig 7. Load circuit for switching times

Table 15. Test data

Supply voltage

V_CC(A), V_CC(B)

0.8 V to 1.6 V

1.65 V to 2.7 V

3.0 V to 3.6 V

Input

V_I^[1]

Load

C_L

V_EXT

[3]

∆t/∆V^[2]

R_L

t_PLH, t_PHL

open

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

2V_CCO

V_CCI

≤1.0 ns/V

≤ 1.0 ns/V

15 pF

2 kΩ

open

GND

2V_CCO

open

GND

2V_CCO

[1] V_CCIis the supply voltage associated with the data input port.

[2] dV/dt ≥ 1.0 V/ns

[3] V_CCOis the supply voltage associated with the output port.

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

14 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

12. Typical propagation delay characteristics

001aai476

001aai477

24

21

(1)

(2)

(3)

(4)

(5)

(6)

t

pd

(ns)

t

pd

(1)

(ns)

20

17

16

12

8

13

(2)

(3)

(4)

(5)

(6)

4

9

0

20

40

60

0

20

40

60

C

L

(pF)

C (pF)

L

a. Propagation delay (An to Bn); V_CC(A)= 0.8 V

b. Propagation delay (An to Bn); V_CC(B)= 0.8 V

(1) V_CC(B)= 0.8 V.

(2) V_CC(B)= 1.2 V.

(3) V_CC(B)= 1.5 V.

(4) V_CC(B)= 1.8 V.

(5) V_CC(B)= 2.5 V.

(6) V_CC(B)= 3.3 V.

(1) V_CC(A)= 0.8 V.

(2) V_CC(A)= 1.2 V.

(3) V_CC(A)= 1.5 V.

(4) V_CC(A)= 1.8 V.

(5) V_CC(A)= 2.5 V.

(6) V_CC(A)= 3.3 V.

Fig 8. Typical propagation delay versus load capacitance; T_amb= 25 °C

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

15 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

001aai478

(1)

001aai491

7

t

PHL

PLH

(ns)

(1)

(2)

(3)

5

3

1

5

3

1

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

a. LOW to HIGH propagation delay (An to Bn);

b. HIGH to LOW propagation delay (An to Bn);

V_CC(A)= 1.2 V

001aai479

(1)

001aai480

7

5

3

1

7

t

PHL

(ns)

PLH

(ns)

(1)

5

3

1

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

c. LOW to HIGH propagation delay (An to Bn);

_CC(A)= 1.5 V

d. HIGH to LOW propagation delay (An to Bn);

V_CC(A)= 1.5 V

V

(1) V_CC(B)= 1.2 V.

(2) V_CC(B)= 1.5 V.

(3) V_CC(B)= 1.8 V.

(4) V_CC(B)= 2.5 V.

(5) V_CC(B)= 3.3 V.

Fig 9. Typical propagation delay versus load capacitance; T_amb= 25 °C

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

16 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

001aai481

(1)

001aai482

7

t

PHL

PLH

(ns)

(1)

5

3

1

5

3

1

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

a. LOW to HIGH propagation delay (An to Bn);

b. HIGH to LOW propagation delay (An to Bn);

V_CC(A)= 1.8 V

001aai483

(1)

001aai486

7

5

3

1

7

t

PHL

(ns)

PLH

(ns)

(1)

5

3

1

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

c. LOW to HIGH propagation delay (An to Bn);

_CC(A)= 2.5 V

d. HIGH to LOW propagation delay (An to Bn);

V_CC(A)= 2.5 V

V

(1) V_CC(B)= 1.2 V.

(2) V_CC(B)= 1.5 V.

(3) V_CC(B)= 1.8 V.

(4) V_CC(B)= 2.5 V.

(5) V_CC(B)= 3.3 V.

Fig 10. Typical propagation delay versus load capacitance; T_amb= 25 °C

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

17 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

001aai485

(1)

001aai484

7

t

PHL

(ns)

PLH

(ns)

(1)

5

3

1

5

3

1

(2)

(3)

(2)

(3)

(4)

(5)

(4)

(5)

0

20

40

60

0

20

40

60

C

L

(pF)

C

L

(pF)

a. LOW to HIGH propagation delay (An to Bn);

_CC(A)= 3.3 V

b. HIGH to LOW propagation delay (An to Bn);

V_CC(A)= 3.3 V

V

(1) V_CC(B)= 1.2 V.

(2) V_CC(B)= 1.5 V.

(3) V_CC(B)= 1.8 V.

(4) V_CC(B)= 2.5 V.

(5) V_CC(B)= 3.3 V.

Fig 11. Typical propagation delay versus load capacitance; T_amb= 25 °C

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

18 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

13. Package outline

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

D

E

A

X

c

H

v

M

A

y

E

Z

13

24

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

7.9

7.7

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT355-1

MO-153

Fig 12. Package outline SOT355-1 (TSSOP24)

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

19 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;

no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm

SOT815-1

D

B

A

E

1

c

detail X

terminal 1

index area

C

e

1

terminal 1

index area

y

v

M

C

A B

C

1

e

b

w

M

2

11

L

12

13

1

e

E

h

2

24

23

14

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

D

E

h

e

L

v

w

y

1

2

1

h

max.

0.05 0.30

0.00 0.18

5.6

5.4

4.25

3.95

3.6

3.4

2.25

1.95

0.5

0.3

mm

1

0.2

0.5

4.5

1.5

0.1

0.05 0.05

0.1

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-04-29

SOT815-1

- - -

Fig 13. Package outline SOT815-1 (DHVQFN24)

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

20 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

14. Abbreviations

Table 16. Abbreviations

Acronym

CDM

Description

Charged Device Model

Complementary Metal Oxide Semiconductor

Device Under Test

CMOS

DUT

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

15. Revision history

Table 17. Revision history

Document ID

74AVC8T245_2

Modiﬁcations:

Release date

20090428

Data sheet status

Change notice

Supersedes

Product data sheet

-

74AVC8T245_1

• Section 5 “Pinning information”:

Changed: pin names changed in pin description table.

74AVC8T245_1

20080711

Product data sheet

-

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

21 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

74AVC8T245_2

Product data sheet

Rev. 02 — 28 April 2009

22 of 23

74AVC8T245

NXP Semiconductors

8-bit dual supply translating transceiver; 3-state

18. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Typical propagation delay characteristics. . . 15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

7

8

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 22

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 28 April 2009

Document identifier: 74AVC8T245_2


型号：	74AVC8T245PW,118
厂家：	NXP
描述：	74AVC8T245 - 8-bit dual supply translating transceiver with configurable voltage translation; 3-state TSSOP2 24-Pin
文件：	总23页 (文件大小：112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AVC8T245PW,118 [NXP]

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