74AVCH16836DGG [NXP]
IC AVC SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56, Bus Driver/Transceiver;
| 型号： | 74AVCH16836DGG |
| 厂家： | 
NXP |
| 描述： | IC AVC SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56, Bus Driver/Transceiver 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AVC16836; 74AVCH16836
20-bit universal bus driver; 3-state
1998 Dec 07
Objective specification
File under Integrated Circuits, IC24
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
FEATURES
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns; CL = 30 pF.
• Wide supply voltage range of 1.2 V to
3.6 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL UNIT
• Complies with JEDEC standard
no. 8-1A/5/7
tPHL/tPLH
propagation delay VCC = 1.8 V
An to Yn
2.6
2.0
1.7
3.0
2.4
2.0
5.0
ns
ns
ns
ns
ns
ns
pF
V
CC = 2.5 V
CC = 3.3 V
• CMOS low power consumption
• Input/Output tolerant up to 3.6 V
V
tPHL/tPLH
propagation delay VCC = 1.8 V(3)
• DCO (Dynamic Controlled Output)
Circuit dynamically changes output
impedance, resulting in noise reduction
without speed degradation
LE/CP to Yn
V
V
CC = 2.5 V(3)
CC = 3.3 V(3)
CI
input capacitance
CPD
power dissipation notes 1 and 2
capacitance per
• Low inductance multiple VCC and GND
pins for minimize noise and ground
bounce.
outputs enabled
25
6
pF
pF
buffer
output disabled
• All data inputs have bushold.
(only 74AVCH16836)
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF; VCC = supply voltage in V;
∑ (CL × VCC2 × fo) = sum of outputs.
• Power off disables 74AVC16836;
74AVCH16836 outputs, permitting Live
Insertion.
DESCRIPTION
The 74AVC(H)16836 is a 20-bit universal
bus driver. Data flow is controlled by output
enable (OE), latch enable (LE) and clock
inputs (CP). Incorporates bushold data
inputs which eliminate the need for
external pull-up resistors to hold unused
inputs.
2. The condition is VI = GND to VCC.
3. For type with bushold.
MNA273
0
handbook, halfpage
I
OH
(mA)
−100
−200
−300
−400
−400
1.8 V
This product is designed to have an
extremely fast propagation delay and a
minimum amount of power consumption.
2.5 V
3.3 V
To ensure the high-impedance output state
during power up or power down, OE should
be tied to VCC through a pullup resistor
(Live insertion).
PMOS
0
1
2
3
4
(V)
V
OH
MNA274
handbook, halfpage
A Dynamic Controlled Output (DCO)
circuitry is implemented to support
termination line drive during transient. See
Fig.1 for typical curves.
V
OL
(mA)
−300
3.3 V
−200
−100
2.5 V
1.8 V
NMOS
0
0
1
2
3
4
(V)
V
OL
Fig.1 Typical curves.
1998 Dec 07
2
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
FUNCTION TABLE
INPUTS(1)
OUTPUTS
OE
LE
CP
An
H
L
L
L
L
L
L
X
L
X
X
X
↑
X
L
Z
L
L
H
L
H
L
H
H
H
H
↑
H
X
X
H
(2)
H
L
Y0
(3)
Y0
Notes
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH level transition.
2. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE
goes low.
3. Output level before the indicated steady-state input conditions were established.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE RANGE
−40 to +85 °C
PINS
56
PACKAGE
TSSOP
MATERIAL
plastic
CODE
74AVC16836DGG
74AVCH16836DGG
SOT364-1
SOT364-1
−40 to +85 °C
56
TSSOP
plastic
PINNING
PIN
SYMBOL
DESCRIPTION
28
n.c.
no connection
data outputs
2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, Y0 to Y19
17, 19, 20, 21, 23, 24, 26, 27
4, 11, 18, 25, 29, 32, 39, 46, 53
GND
VCC
OE
ground (0 V)
7, 22, 35 and 50
positive supply voltage
1
output enable input (active LOW)
latch enable input (active LOW)
clock input
29
56
LE
CP
55, 54, 52, 51, 49, 48, 47, 45, 44, 43, A0 to A19
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
data inputs
1998 Dec 07
3
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
1
handbook, halfpage
OE
CP
LE
EN1
2C3
OE
1
2
56 CP
56
29
Y
0
A
A
55
54
0
1
C3
G2
Y
1
3
GND
4
53 GND
Y
2
5
52
51
50
49
48
47
A
A
V
A
A
A
2
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
2
Y
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
Y
3
6
3
3
Y
1
1
V
7
CC
CC
4
5
Y
2
2
Y
4
8
6
Y
3
Y
5
9
1
3 D
1
5
3
8
Y
6
10
6
Y
4
4
GND 11
46 GND
9
Y
5
5
Y
Y
Y
12
13
14
15
16
17
45
44
43
42
41
40
A
A
A
A
A
A
7
8
9
7
10
12
13
14
15
16
17
19
20
21
23
Y
6
6
8
Y
7
7
9
16836
Y
8
Y
10
11
12
10
11
12
8
Y
Y
Y
9
9
Y
10
10
11
12
13
14
GND 18
39 GND
Y
Y
Y
11
12
13
14
Y
Y
Y
19
20
21
22
23
24
38
37
36
35
34
33
A
A
A
V
A
A
13
14
15
13
14
15
CC
16
17
V
A
A
Y
Y
CC
Y
16
17
15
15
16
Y
A
Y
Y
Y
16
17
18
GND 25
32 GND
33
31
30
A
17
24
26
Y
Y
26
27
A
A
31
30
18
19
18
19
A
18
n.c. 28
29 LE
27
A
19
MNA275
Y
19
Fig.2 Pin configuration.
Fig.3 IEEE/IEC logic symbol
handbook, halfpage
OE
V
handbook, halfpage
CC
CP
LE
data
input
to internal circuit
A
0
D
LE
Y
0
MNA278
CP
MNA277
Fig.4 Logic diagram
Fig.5 Bushold circuit
1998 Dec 07
4
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
VCC
DC supply voltage
according JEDEC Low Voltage Standards
1.65
2.3
3.0
1.2
0
1.95
2.7
3.6
3.6
3.6
3.6
VCC
+85
30
V
V
V
VCC
VI
DC supply voltage (for low-voltage applications)
DC input voltage range
V
V
VO
DC output voltage range; output 3-state
DC output voltage range; output High or Low state
operating ambient temperature range
input rise and fall times
0
V
VO
0
V
Tamb
tr, tf
in free air
VCC = 1.65 to 2.3 V
−40
0
°C
ns/V
ns/V
ns/V
VCC = 2.3 to 3.0 V
CC = 3.0 to 3.6 V
0
20
V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
−
MAX.
+4.6
UNIT
V
VCC
IIK
DC input diode current
DC input voltage
VI < 0
−50
mA
V
VI
for inputs; note 1
VO > VCC or VO < 0
note 1
−0.5
−
4.6
IOK
VO
DC output diode current
±50
mA
V
DC output voltage; output
High or Low state
−0.5
VCC + 0.5
VO
IO
DC output voltage; output
3-state
note 1
−0.5
4.6
V
DC output source or sink
current
VO = 0 to VCC
−
±50
mA
IGND, ICC DC VCC or GND current
−
±100
mA
Tstg
Ptot
storage temperature range
−65
+150
°C
power dissipation per package
plastic thin-medium-shrink
(TSSOP)
for temperature range: −40 to +125 °C;
above +55 °C derate linearly with 8 mW/K
−
600
mW
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Dec 07
5
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
DC CHARACTERISTICS
Family 74AVC
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
VCC (V)
T
amb = −40 to +85 °C
TYP.(1)
MAX.
SYMBOL
PARAMETER
UNIT
OTHER
VI (V)
MIN.
VIH
HIGH level input
voltage
1.2
VCC
−
−
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
1.2
0.65VCC 0.9
−
1.7
2.0
−
1.2
1.5
−
−
−
VIL
LOW level input
voltage
GND
0.35 VCC
0.7
0.8
−
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
−
0.9
1.2
1.5
−
−
VOH
HIGH level output IO = −100 µA 1.65 to 3.6
voltage
VIH or VIL
V
V
V
V
−
−
−
−
−
CC−0.20 VCC
IO = −4 mA
IO = −8 mA
1.65
2.3
CC−0.45 VCC−0.10
−
CC−0.55 VCC−0.28
−
IO = −12 mA 3.0
CC−0.70 VCC−0.32
−
VOL
LOW level output
voltage
IO = 100 µA
IO = 4 mA
IO = 8 mA
IO = 12 mA
1.65 to 3.6
VIH or VIL
GND
0.10
0.26
0.36
0.1
0.20
0.45
0.55
0.70
2.5
1.65
2.3
3.0
II
input leakage
current per pin
1.65 to 3.6
VCC or GND
IOFF
power off leakage VI or
0
−
−
0.1
0.1
±10
µA
µA
current
VO = 3.6
IIHZ/IILZ
input current for
common I/O pins
1.65 to 3.6
VCC or GND
VIH or VIL
12.5
IOZ
3-state output
VO = VCC or
1.65 to 2.7
3.0 to 3.6
1.65 to 2.7
3.0 to 3.6
−
−
−
−
0.1
0.1
0.1
0.2
5
µA
µA
µA
µA
OFF−state current GND
10
20
40
ICC
quiescent supply
current
IO = 0
VCC or GND
Note
1. All typical values are measured at Tamb = 25 °C.
1998 Dec 07
6
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
Optional: bushold specification for 74AVCH16836 only
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
OTHER VCC (V)
see note 2 1.65
Tamb = −40 to +85 °C
MIN. MAX.
TYP.(1)
25
SYMBOL
PARAMETER
UNIT
VI (V)
IBHL
bushold LOW sustaining
current
0.35 VCC
0.7 V
−
−
−
−
−
−
−
−
−
−
−
−
−
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
2.3
45
−
−
−
−
−
−
−
−
−
−
−
3.0
0.8 V
75
IBHH
bushold HIGH sustaining
current
1.65
2.3
0.65 VCC
1.7 V
−25
−45
−75
200
300
450
−200
−300
−450
3.0
2.0 V
IBHLO
bushold LOW overdrive
current
1.95
2.7
3.6
IBHHO
bushold HIGH overdrive
current
1.95
2.7
3.6
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Valid for data inputs of bushold parts.
1998 Dec 07
7
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
AC CHARACTERISTICS
Type 74AVC16836
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF.
TEST CONDITIONS
Tamb = −40 to +85 °C
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC (V)
1.2
1.65 to 1.95 1.0
MIN. TYP.(1) MAX.
tPHL/tPLH
propagation delay An to Yn
see Figs. 6 and 12
−
5.2
2.6
2.0
1.7
6.0
3.0
2.4
2.0
5.5
2.8
2.2
1.9
6.0
3.5
2.8
2.5
6.0
4.0
2.4
2.5
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
3.0
2.5
−
2.3 to 2.7
3.0 to 3.6
1.2
0.8
0.7
−
tPHL/tPLH
propagation delay LE to Yn
propagation delay CP to Yn
see Figs. 7 and 12
see Figs. 8 and 12
see Figs. 11 and 12
see Figs. 11 and 12
see Figs. 8 and 12
see Figs. 7 and 12
see Figs. 10 and 12
see Figs. 9 and 12
1.65 to 1.95 1.0
5.5
3.6
3.0
−
2.3 to 2.7
3.0 to 3.6
1.2
0.8
0.7
−
t
PHL/tPLH
1.65 to 1.95 0.9
5.2
3.3
2.9
−
2.3 to 2.7
3.0 to 3.6
1.2
0.8
0.7
−
tPZH/tPZL
3-state output enable time
OE to Yn
1.65 to 1.95 1.5
6.0
5.0
4.5
−
2.3 to 2.7
3.0 to 3.6
1.2
1.0
1.0
−
t
PHZ/tPLZ
3-state output disable time
OE to Yn
1.65 to 1.95 1.5
6.0
4.5
4.0
−
2.3 to 2.7
3.0 to 3.6
1.2
1.0
1.0
−
tW
CP pulse width HIGH or LOW
LE pulse width LOW
1.65 to 1.95 2.0
−
−
2.3 to 2.7
3.0 to 3.6
1.2
1.2
1.0
−
−
−
−
−
tW
−
−
1.65 to 1.95 2.0
−
−
2.3 to 2.7
3.0 to 3.6
1.2
1.2
1.0
−
−
−
−
−
tSU
Set-up time An to CP
Set-up time An to LE
−
−
1.65 to 1.95 0.5
−
−
2.3 to 2.7
3.0 to 3.6
1.2
0.4
0.3
−
−
−
−
−
tSU
−
−
1.65 to 1.95 0.5
−
−
2.3 to 2.7
3.0 to 3.6
0.4
0.3
−
−
−
−
1998 Dec 07
8
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
TEST CONDITIONS
WAVEFORMS VCC (V)
1.2
1.65 to 1.95 0.5
T
amb = −40 to +85 °C
SYMBOL
th
PARAMETER
hold time An to CP
UNIT
MIN. TYP.(1) MAX.
see Figs. 10 and 12
see Figs. 9 and 12
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.3 to 2.7
3.0 to 3.6
1.2
0.4
0.3
−
th
hold time An to LE
1.65 to 1.95 0.5
2.3 to 2.7
3.0 to 3.6
1.2
0.4
0.3
−
fmax
maximum clock pulse frequency see Figs. 8 and 12
1.65 to 1.95 250
2.3 to 2.7
3.0 to 3.6
400
500
Notes
1. All typical values are measured at Tamb = 25 °C and VCC = 1.8 V; VCC = 2.5 V; VCC = 3.3 V.
Type 74AVCH16836
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF.
TEST CONDITIONS
WAVEFORMS CC (V)
T
amb = −40 to +85 °C
SYMBOL
PARAMETER
UNIT
V
MIN. TYP.(1) MAX.
tPHL/tPLH
propagation delay An to Yn
see Figs. 6 and 12
see Figs. 7 and 12
see Figs. 8 and 12
see Figs. 11 and 12
see Figs. 11 and 12
1.2
−
5.2
2.6
2.0
1.7
6.0
3.0
2.4
2.0
5.5
2.8
2.2
1.9
6.0
3.5
2.8
2.5
6.0
4.0
2.4
2.5
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.65 to 1.95 1.0
4.6
3.1
2.6
−
2.3 to 2.7
3.0 to 3.6
1.2
0.8
0.7
−
tPHL/tPLH
propagation delay LE to Yn
propagation delay CP to Yn
1.65 to 1.95 1.0
5.5
3.6
3.0
−
2.3 to 2.7
3.0 to 3.6
1.2
0.8
0.7
−
tPHL/tPLH
1.65 to 1.95 0.9
5.2
3.3
2.9
−
2.3 to 2.7
3.0 to 3.6
1.2
0.8
0.7
−
tPZH/tPZL
3-state output enable time
OE to nYn
1.65 to 1.95 1.5
6.0
5.0
4.5
−
2.3 to 2.7
3.0 to 3.6
1.2
1.0
1.0
−
tPHZ/tPLZ
3-state output disable time
OE to nYn
1.65 to 1.95 1.5
6.0
4.5
4.0
2.3 to 2.7
3.0 to 3.6
1.0
1.0
1998 Dec 07
9
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
TEST CONDITIONS
WAVEFORMS VCC (V)
1.2
1.65 to 1.95 2.0
T
amb = −40 to +85 °C
SYMBOL
tW
PARAMETER
UNIT
MIN. TYP.(1) MAX.
CP pulse width HIGH or LOW
see Figs. 8 and 12
see Figs. 7 and 12
see Figs. 10 and 12
see Figs. 9 and 12
see Figs. 10 and 12
see Figs. 9 and 12
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.3 to 2.7
3.0 to 3.6
1.2
1.2
1.0
−
tW
LE pulse width LOW
Set-up time An to CP
Set-up time An to LE
hold time An to CP
hold time An to LE
1.65 to 1.95 2.0
2.3 to 2.7
3.0 to 3.6
1.2
1.2
1.0
−
tSU
tSU
th
1.65 to 1.95 0.5
2.3 to 2.7
3.0 to 3.6
1.2
0.4
0.3
−
1.65 to 1.95 0.5
2.3 to 2.7
3.0 to 3.6
1.2
0.4
0.3
−
1.65 to 1.95 0.5
2.3 to 2.7
3.0 to 3.6
1.2
0.4
0.3
−
th
1.65 to 1.95 0.5
2.3 to 2.7
3.0 to 3.6
1.2
0.4
0.3
−
fmax
maximum clock pulse frequency see Figs. 8 and 12
1.65 to 1.95 250
2.3 to 2.7
3.0 to 3.6
400
500
Notes
1. All typical values are measured at Tamb = 25 °C and VCC = 1.8 V,VCC = 2.5 V,VCC = 3.3 V.
1998 Dec 07
10
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
AC WAVEFORMS
V
I
V
handbook, halfpage
I
LE INPUT
V
V
M
t
M
t
V
A
INPUT
M
n
GND
GND
t
W
t
t
PLH
PHL
PHL
PLH
(4)
V
V
OH
OH
V
V
Y
OUTPUT
V
Y OUTPUT
n
M
M
n
(4)
V
MNA266
OL
MNA280
OL
Fig.7 Latch enable input (LE) pulse width, the
latch enable input to output (Yn)
propagation delays
Fig.6 The input (An) to output (Yn) propagation
delay.
1/f
V
I
max
V
I
V
V
V
A
INPUT
M
M
t
M
t
n
CP INPUT
V
V
M
t
M
t
GND
GND
t
h
h
t
W
t
SU
SU
PHL
PLH
V
I
V
OH
V
V
M
LE INPUT
V
M
Y
OUTPUT
M
n
V
GND
OL
MNA281
MNA282
Fig.8 The clock (CP) to Yn propagation delays,
the clock pulse width and maximum clock
frequency
Fig.9 The data set-up time and hold times for the
An input to the LE input
1998 Dec 07
11
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
V
I
V
I
V
V
CP INPUT
OE INPUT
M
M
GND
GND
t
t
PZL
t
t
su
PLZ
su
V
t
t
h
CC
OL
h
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
I
V
M
V
V
A
INPUT
V
X
M
n
t
t
PHZ
GND
PZH
V
OH
V
Y
OUTPUT
V
HIGH-to-OFF
OFF-to-HIGH
M
V
OH
GND
V
Y
OUTPUT
M
n
outputs
enabled
outputs
enabled
outputs
disabled
V
OL
MNA283
MNA284
Fig.10 The data set-up time and hold times for the
An input to the clock CP input.
Fig.11 The 3-state enable and disable times.
NOTES: VCC = 2.3 to 2.7 V range and VCC < 2.3 V
1. VM = 0.5 VCC
2V
handbook, halfpage
S1
CC
open
GND
2. VX = VOL + 150 mV
3. VY = VOH - 150 mV
4. VI = VCC
V
CC
R
load
V
V
O
I
PULSE
D.U.T.
GENERATOR
5. VOL and VOH are typical output voltage drop that occur
with the output load.
R
C
load
R
L
T
MNA285
NOTES: VCC = 3.0 to 3.6 V range
1. VM = 0.5 VCC
2. VX = VOL + 300 mV
3. VY = VOH - 300 mV
4. VI = 2.7 V
TEST
SWITCH
VCC
< 2.3 V
VI
RLOAD
t
PLH/tPHL Open
PLZ/tPZL 2VCC
VCC 1000Ω
t
2.3 - 2.7 V VCC 500Ω
3.0 - 3.6 V 2.7 V 500Ω
5. VOL and VOH are typical output voltage drop that occur
with the output load.
tPHZ/tPZH GND
Fig.12 Load circuitry for switching times.
1998 Dec 07
12
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
PACKAGE OUTLINE
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.25
0.5
1.0
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-02-03
95-02-10
SOT364-1
MO-153EE
1998 Dec 07
13
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1998 Dec 07
14
Philips Semiconductors
Objective specification
20-bit universal bus driver; 3-state
74AVC16836; 74AVCH16836
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
not suitable(2)
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Dec 07
15
Philips Semiconductors – a worldwide company
Argentina: see South America
Middle East: see Italy
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Fax. +43 160 101 1210
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
Norway: Box 1, Manglerud 0612, OSLO,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belgium: see The Netherlands
Brazil: see South America
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Portugal: see Spain
Romania: see Italy
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Colombia: see South America
Czech Republic: see Austria
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Slovakia: see Austria
Slovenia: see Italy
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
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Tel. +27 11 470 5911, Fax. +27 11 470 5494
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Spain: Balmes 22, 08007 BARCELONA,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245112/00/01/pp16
Date of release: 1998 Dec 07
Document order number: 9397 740 04918
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