74AVCH1T45GM [NXP]
Dual supply translating transceiver; 3-state; 双电源转换收发器;三态
| 型号： | 74AVCH1T45GM |
| 厂家： | 
NXP |
| 描述： | Dual supply translating transceiver; 3-state |
| 文件： | 总22页 (文件大小：797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AVCH1T45
Dual supply translating transceiver; 3-state
Rev. 01 — 25 October 2007
Product data sheet
1. General description
The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level
translation. It features two data input-output ports (A and B), a direction control input (DIR)
and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any
voltage between 0.8 V and 3.6 V making the device suitable for translating between any of
the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are
referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission
from A to B and a LOW on DIR allows transmission from B to A.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
The 74AVCH1T45 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features
■ Wide supply voltage range:
◆ VCC(A): 0.8 V to 3.6 V
◆ VCC(B): 0.8 V to 3.6 V
■ High noise immunity
■ Complies with JEDEC standards:
◆ JESD8-12 (0.8 V to 1.3 V)
◆ JESD8-11 (0.9 V to 1.65 V)
◆ JESD8-7 (1.2 V to 1.95 V)
◆ JESD8-5 (1.8 V to 2.7 V)
◆ JESD8-B (2.7 V to 3.6 V)
■ ESD protection:
◆ HBM JESD22-A114E Class 3B exceeds 8000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101C exceeds 1000 V
■ Maximum data rates:
◆ 500 Mbit/s (1.8 V to 3.3 V translation)
◆ 320 Mbit/s (< 1.8 V to 3.3 V translation)
◆ 320 Mbit/s (translate to 2.5 V or 1.8 V)
◆ 280 Mbit/s (translate to 1.5 V)
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
◆ 240 Mbit/s (translate to 1.2 V)
■ Suspend mode
■ Bus hold on data inputs
■ Latch-up performance exceeds 100 mA per JESD 78 Class II
■ Inputs accept voltages up to 3.6 V
■ Low noise overshoot and undershoot < 10 % of VCC
■ IOFF circuitry provides partial Power-down mode operation
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVCH1T45GW
74AVCH1T45GM
−40 °C to +125 °C
−40 °C to +125 °C
SC-88
plastic surface-mounted package; 6 leads
SOT363
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
Marking code
74AVCH1T45GW
74AVCH1T45GM
K5
K5
5. Functional diagram
5
DIR
DIR
A
3
A
4
B
B
V
V
CC(B)
CC(A)
V
V
CC(A)
CC(B)
001aag886
001aag885
Fig 1. Logic symbol
Fig 2. Logic diagram
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
2 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
6. Pinning information
6.1 Pinning
74AVCH1T45
74AVCH1T45
V
1
2
3
6
5
4
V
CC(B)
CC(A)
GND
1
2
3
6
5
4
V
V
CC(B)
CC(A)
GND
DIR
B
DIR
B
A
A
001aag888
Transparent top view
001aag887
Fig 3. Pin configuration SOT363
Fig 4. Pin configuration SOT886
6.2 Pin description
Table 3.
Symbol
VCC(A)
GND
A
Pin description
Pin
1
Description
supply voltage port A and DIR
ground (0 V)
2
3
data input or output
data input or output
direction control
B
4
DIR
5
VCC(B)
6
supply voltage port B
7. Functional description
Table 4.
Function table[1]
Supply voltage
VCC(A), VCC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
GND[4]
Input
DIR[2]
Input/output[3]
A
B
L
A = B
input
Z
input
B = A
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The DIR input circuit is referenced to VCC(A)
.
[3] The input circuit of the data I/O is always active.
[4] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
3 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
−0.5
−0.5
−50
−0.5
−50
−0.5
−0.5
-
Max
+4.6
+4.6
-
Unit
V
supply voltage port A
supply voltage port B
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1][2][3]
[1]
VO
Active mode
VCCO + 0.5
+4.6
±50
100
-
Suspend or 3-state mode
VO = 0 V to VCC
ICC(A) or ICC(B)
V
IO
output current
mA
mA
mA
°C
mW
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
250
[4]
Tamb = −40 °C to +125 °C
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
0.8
0.8
0
Max
3.6
Unit
V
supply voltage port A
supply voltage port B
input voltage
3.6
V
3.6
V
[1]
[2]
VO
output voltage
Active mode
0
VCCO
3.6
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
−40
-
+125
5
°C
ns/V
∆t/∆V
input transition rise and fall rate
VCCI = 0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
4 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VOH
HIGH-level output
VI = VIH or VIL
voltage
IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V
VI = VIH or VIL
-
0.69
0.07
-
-
V
VOL
LOW-level output
voltage
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
-
-
V
II
input leakage
current
DIR input; VI = 0 V to 3.6 V;
±0.025 ±0.25
µA
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
IBHH
IBHLO
IBHHO
IOZ
bus hold LOW
current
A or B port;
VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V
-
-
-
-
-
-
-
-
-
26
-
µA
µA
µA
µA
µA
µA
µA
pF
pF
bus hold HIGH
current
A or B port;
VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V
−24
28
-
[1]
[1]
[2]
bus hold LOW
overdrive current
A or B port; VCC(A) = VCC(B) = 1.2 V
-
bus hold HIGH
overdrive current
A or B port; VCC(A) = VCC(B) = 1.2 V
−26
±0.5
±0.1
±0.1
1
-
OFF-state output
current
A or B port; VO = 0 V or VCCO
;
±2.5
±1
±1
-
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IOFF
power-off leakage
current
A port; VI or VO = 0 V to 3.6 V;
CC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
V
B port; VI or VO = 0 V to 3.6 V;
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
V
CI
input capacitance
DIR input; VI = 0 V or 3.3 V;
CC(A) = VCC(B) = 3.3 V
V
CI/O
input/output
capacitance
A and B port; suspend mode;
VO = 3.3 V or 0 V;
4
-
V
CC(A) = VCC(B) = 3.3 V
Tamb = −40 °C to +85 °C
[3]
VIH
HIGH-level input
voltage
data input
VCCI = 0.8 V
0.70 × VCCI
-
-
-
-
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.65 × VCCI
1.6
2
VCCI = 0.8 V
0.70 × VCC(A)
-
-
-
-
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
0.65 × VCC(A)
1.6
2
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
5 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[3]
VIL
LOW-level input
data input
voltage
VCCI = 0.8 V
-
-
-
-
-
-
-
-
0.30 × VCCI
0.35 × VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.9
VCCI = 0.8 V
-
-
-
-
-
-
-
-
0.30 × VCC(A)
0.35 × VCC(A)
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VI = VIH or VIL
0.9
VOH
HIGH-level output
voltage
[2]
IO = −100 µA;
VCCO − 0.1
-
-
V
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IO = −3 mA; VCC(A) = VCC(B) = 1.1 V
IO = −6 mA; VCC(A) = VCC(B) = 1.4 V
IO = −8 mA; VCC(A) = VCC(B) = 1.65 V
IO = −9 mA; VCC(A) = VCC(B) = 2.3 V
IO = −12 mA; VCC(A) = VCC(B) = 3.0 V
VI = VIH or VIL
0.85
1.05
1.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
1.75
2.3
VOL
LOW-level output
voltage
IO = 100 µA;
-
-
0.1
V
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
IO = 8 mA; VCC(A) = VCC(B) = 1.65 V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
IO = 12 mA; VCC(A) = VCC(B) = 3.0 V
DIR input; VI = 0 V to 3.6 V;
-
-
-
-
-
-
-
-
-
-
-
-
0.25
0.35
0.45
0.55
0.7
V
V
V
V
V
II
input leakage
current
±1
µA
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
bus hold LOW
current
A or B port
VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V
VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V
VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V
VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V
A or B port
15
-
-
-
-
-
-
-
-
µA
µA
µA
µA
25
45
100
IBHH
bus hold HIGH
current
VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V
VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V
VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V
VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V
−15
−25
−45
−100
-
-
-
-
-
-
-
-
µA
µA
µA
µA
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
6 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
[1]
[2]
IBHLO
bus hold LOW
overdrive current
A or B port
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port
125
200
300
500
-
-
-
-
-
-
-
-
µA
µA
µA
µA
IBHHO
bus hold HIGH
overdrive current
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port; VO = 0 V or VCCO
−125
−200
−300
−500
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
-
-
-
IOZ
OFF-state output
current
;
±5
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
A port; VI or VO = 0 V to 3.6 V;
CC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
IOFF
power-off leakage
current
-
-
-
-
±5
±5
µA
µA
V
V
[3]
ICC
supply current
A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
8
8
-
µA
µA
µA
-
-
VCC(A) = 0 V; VCC(B) = 3.6 V
−2
0
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
8
µA
µA
µA
µA
−2
-
0
-
-
VCC(A) = 0 V; VCC(B) = 3.6 V
8
A plus B port (ICC(A) + ICC(B)); IO = 0 A;
-
-
16
VI = 0 V or VCCI
;
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
Tamb = −40 °C to +125 °C
[3]
VIH
HIGH-level input
voltage
data input
VCCI = 0.8 V
0.70 × VCCI
-
-
-
-
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.65 × VCCI
1.6
2
VCCI = 0.8 V
0.70 × VCC(A)
-
-
-
-
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
0.65 × VCC(A)
1.6
2
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
7 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[3]
VIL
LOW-level input
data input
voltage
VCCI = 0.8 V
-
-
-
-
-
-
-
-
0.30 × VCCI
0.35 × VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.9
VCCI = 0.8 V
-
-
-
-
-
-
-
-
0.30 × VCC(A)
0.35 × VCC(A)
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VI = VIH or VIL
0.9
VOH
HIGH-level output
voltage
[2]
IO = −100 µA;
VCCO − 0.1
-
-
V
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IO = −3 mA; VCC(A) = VCC(B) = 1.1 V
IO = −6 mA; VCC(A) = VCC(B) = 1.4 V
IO = −8 mA; VCC(A) = VCC(B) = 1.65 V
IO = −9 mA; VCC(A) = VCC(B) = 2.3 V
IO = −12 mA; VCC(A) = VCC(B) = 3.0 V
VI = VIH or VIL
0.85
1.05
1.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
1.75
2.3
VOL
LOW-level output
voltage
IO = 100 µA;
-
-
0.1
V
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
IO = 8 mA; VCC(A) = VCC(B) = 1.65 V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
IO = 12 mA; VCC(A) = VCC(B) = 3.0 V
DIR input; VI = 0 V to 3.6 V;
-
-
-
-
-
-
-
-
-
-
-
-
0.25
0.35
0.45
0.55
0.7
V
V
V
V
V
II
input leakage
current
±1.5
µA
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
bus hold LOW
current
A or B port
VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V
VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V
VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V
VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V
A or B port
15
25
45
90
-
-
-
-
-
-
-
-
µA
µA
µA
µA
IBHH
bus hold HIGH
current
VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V
VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V
VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V
VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V
−15
−25
−45
−100
-
-
-
-
-
-
-
-
µA
µA
µA
µA
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
8 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
[1]
[2]
IBHLO
bus hold LOW
overdrive current
A or B port
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port
125
200
300
500
-
-
-
-
-
-
-
-
µA
µA
µA
µA
IBHHO
bus hold HIGH
overdrive current
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port; VO = 0 V or VCCO
−125
−200
−300
−500
-
-
-
-
-
-
-
µA
µA
µA
µA
µA
-
-
-
IOZ
OFF-state output
current
;
±7.5
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
A port; VI or VO = 0 V to 3.6 V;
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
CC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
IOFF
power-off leakage
current
-
-
-
-
±35
±35
µA
µA
V
V
[3]
ICC
supply current
A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
12
12
-
µA
µA
µA
-
-
VCC(A) = 0 V; VCC(B) = 3.6 V
−8
0
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
-
-
12
-
µA
µA
µA
µA
−8
-
0
-
VCC(A) = 0 V; VCC(B) = 3.6 V
12
24
A plus B port (ICC(A) + ICC(B)); IO = 0 A;
-
-
VI = 0 V or VCCI
;
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
[1] In order to guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to
VIH
.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCI is the supply voltage associated with the data input port.
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
9 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
11. Dynamic characteristics
Table 8.
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1]
Symbol Parameter
Conditions
VCC(B)
1.5 V
Unit
0.8 V
15.8
15.8
12.2
11.7
27.5
28.0
1.2 V
8.4
1.8 V
8.0
2.5 V
8.7
3.3 V
9.5
tpd
tdis
ten
propagation delay A to B
8.0
12.4
12.2
7.6
ns
ns
ns
ns
ns
ns
B to A
12.7
12.2
7.9
12.2
12.2
8.2
12.0
12.2
8.7
11.8
12.2
10.2
22.0
21.7
disable time
enable time
DIR to A
DIR to B
DIR to A
DIR to B
20.6
20.6
20.0
20.2
20.4
20.2
20.7
20.9
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 9.
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1]
Symbol Parameter
Conditions
VCC(A)
1.5 V
Unit
0.8 V
15.8
15.8
12.2
11.7
27.5
28.0
1.2 V
12.7
8.4
1.8 V
12.2
8.0
2.5 V
12.0
8.7
3.3 V
11.8
9.5
tpd
tdis
ten
propagation delay A to B
12.4
8.0
ns
ns
ns
ns
ns
ns
B to A
disable time
enable time
DIR to A
DIR to B
DIR to A
DIR to B
4.9
3.8
3.7
2.8
3.4
9.2
9.0
8.8
8.7
8.6
17.6
17.6
17.0
16.2
16.8
15.9
17.4
14.8
18.1
15.2
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) and VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
CPD
power dissipation A port: (direction A to B);
1
2
2
2
2
2
pF
pF
capacitance
B port: (direction B to A)
A port: (direction B to A);
B port: (direction A to B)
9
11
11
12
14
17
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
10 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 11. Dynamic characteristics for temperature range −40 °C to +85 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation A to B
1.0
1.0
2.2
2.2
-
9.0
9.0
0.7
0.8
2.2
1.8
-
6.8
8.0
0.6
0.7
2.2
2.0
-
6.1
7.7
0.5
0.6
2.2
1.7
-
5.7
7.2
0.5
0.5
2.2
2.4
-
6.1 ns
7.1 ns
8.8 ns
7.2 ns
14.3 ns
14.9 ns
delay
B to A
disable time DIR to A
DIR to B
8.8
8.8
8.8
8.8
8.4
6.7
6.9
6.2
enable time DIR to A
DIR to B
17.4
17.8
14.7
15.6
14.6
14.9
13.4
14.5
-
-
-
-
-
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.6
2.0
-
8.0
6.8
0.7
0.8
1.6
1.8
-
5.4
5.4
0.6
0.7
1.6
1.6
-
4.6
5.1
0.5
0.6
1.6
1.2
-
3.7
4.7
6.3
4.8
9.5
10.0
0.5
0.5
1.6
1.7
-
3.5 ns
4.5 ns
6.3 ns
5.5 ns
10.0 ns
9.8 ns
B to A
disable time DIR to A
DIR to B
6.3
6.3
6.3
7.6
5.9
6.0
enable time DIR to A
DIR to B
14.4
14.3
11.3
11.7
11.1
10.9
-
-
-
-
-
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.6
1.8
-
7.7
6.1
0.6
0.7
1.6
1.8
-
5.1
4.6
0.5
0.5
1.6
1.4
-
4.3
4.4
5.5
5.8
10.2
9.8
0.5
0.5
1.6
1.0
-
3.4
3.9
5.5
4.5
8.4
8.9
0.5
0.5
1.6
1.5
-
3.1 ns
3.7 ns
5.5 ns
5.2 ns
8.9 ns
8.6 ns
B to A
disable time DIR to A
DIR to B
5.5
5.5
7.8
5.7
enable time DIR to A
DIR to B
13.9
13.2
10.3
10.6
-
-
-
-
-
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.5
1.7
-
7.2
5.7
0.5
0.6
1.5
2.0
-
4.7
3.8
4.2
5.2
9.0
8.9
0.5
0.5
1.5
1.5
-
3.9
3.4
4.2
5.1
8.5
8.1
0.5
0.5
1.5
0.6
-
3.0
3.0
4.2
4.2
7.2
7.2
0.5
0.5
1.5
1.1
-
2.6 ns
2.8 ns
4.2 ns
4.8 ns
7.6 ns
6.8 ns
B to A
disable time DIR to A
DIR to B
4.2
7.3
enable time DIR to A
DIR to B
13.0
11.4
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.5
1.7
-
7.1
6.1
0.5
0.6
1.5
0.7
-
4.5
3.6
4.7
5.5
9.1
9.2
0.5
0.5
1.5
0.6
-
3.7
3.1
4.7
5.5
8.6
8.4
0.5
0.5
1.5
0.7
-
2.8
2.6
4.7
4.1
6.7
7.5
0.5
0.5
1.5
1.7
-
2.4 ns
2.4 ns
4.7 ns
4.7 ns
7.1 ns
7.1 ns
B to A
disable time DIR to A
DIR to B
4.7
7.2
enable time DIR to A
DIR to B
13.3
11.8
-
-
-
-
-
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
11 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range −40 °C to +125 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation A to B
1.0
1.0
2.2
2.2
-
9.9
9.9
0.7
0.8
2.2
1.8
-
7.5
8.8
0.6
0.7
2.2
2.0
-
6.8
8.5
0.5
0.6
2.2
1.7
-
6.3
8.0
0.5
0.5
2.2
2.4
-
6.8 ns
7.9 ns
9.7 ns
8.0 ns
15.9 ns
16.5 ns
delay
B to A
disable time DIR to A
DIR to B
9.7
9.7
9.7
9.7
9.2
7.4
7.6
6.9
enable time DIR to A
DIR to B
19.1
19.6
16.2
17.2
16.1
16.5
14.9
16.0
-
-
-
-
-
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.6
2.0
-
8.8
7.5
0.7
0.8
1.6
1.8
-
6.0
6.0
0.6
0.7
1.6
1.6
-
5.1
5.7
0.5
0.6
1.6
1.2
-
4.1
5.2
0.5
0.5
1.6
1.7
-
3.9 ns
5.0 ns
7.0 ns
6.1 ns
11.1 ns
10.9 ns
B to A
disable time DIR to A
DIR to B
7.0
7.0
7.0
7.0
8.3
6.5
6.6
5.3
enable time DIR to A
DIR to B
15.8
15.8
12.5
13.0
12.3
12.7
10.5
11.1
-
-
-
-
-
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.6
1.8
-
8.5
6.8
0.6
0.7
1.6
1.8
-
5.7
5.1
0.5
0.5
1.6
1.4
-
4.8
4.9
0.5
0.5
1.6
1.0
-
3.8
4.3
6.1
5.0
9.3
9.9
0.5
0.5
1.6
1.5
-
3.5 ns
4.1 ns
6.1 ns
5.8 ns
9.9 ns
9.6 ns
B to A
disable time DIR to A
DIR to B
6.1
6.1
6.1
8.6
6.3
6.4
enable time DIR to A
DIR to B
15.4
14.6
11.4
11.8
11.3
10.9
-
-
-
-
-
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.5
1.7
-
8.0
6.3
0.5
0.6
1.5
2.0
-
5.2
4.2
4.7
5.8
10.0
9.9
0.5
0.5
1.5
1.5
-
4.3
3.8
4.7
5.7
9.5
9.0
0.5
0.5
1.5
0.6
-
3.3
3.3
4.7
4.7
8.0
8.0
0.5
0.5
1.5
1.1
-
2.9 ns
3.1 ns
4.7 ns
5.3 ns
8.4 ns
7.6 ns
B to A
disable time DIR to A
DIR to B
4.7
8.0
enable time DIR to A
DIR to B
14.3
12.7
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.5
1.7
-
7.9
6.8
0.5
0.6
1.5
0.7
-
5.0
4.0
0.5
0.5
1.5
0.6
-
4.1
3.5
5.2
6.1
9.6
9.3
0.5
0.5
1.5
0.7
-
3.1
2.9
5.2
4.6
7.5
8.3
0.5
0.5
1.5
1.7
-
2.7 ns
2.7 ns
5.2 ns
5.2 ns
7.9 ns
7.9 ns
B to A
disable time DIR to A
DIR to B
5.2
5.2
7.9
6.0
enable time DIR to A
DIR to B
14.7
13.1
10.1
10.2
-
-
-
-
-
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
12 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
12. Waveforms
V
I
V
M
A, B input
GND
t
t
PLH
PHL
V
OH
B, A output
V
M
001aae967
V
OL
Measurement points are given in Table 13.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 5. The data input (A, B) to output (B, A) propagation delay times
V
I
DIR input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae968
Measurement points are given in Table 13.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 6. Enable and disable times
Table 13. Measurement points
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input[1]
Output[2]
VM
VM
VX
VOL + 0.1 V
VY
0.5 × VCCI
0.5 × VCCI
0.5 × VCCI
0.5 × VCCO
0.5 × VCCO
0.5 × VCCO
V
V
V
OH − 0.1 V
VOL + 0.15 V
VOL + 0.3 V
OH − 0.15 V
OH − 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
13 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 14.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
Table 14. Test data
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
VI[1]
Load
CL
VEXT
[2]
∆t/∆V
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2 × VCCO
2 × VCCO
2 × VCCO
VCCI
VCCI
VCCI
≤ 1.0 ns/V
≤ 1.0 ns/V
≤ 1.0 ns/V
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
open
GND
open
GND
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
14 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 8 is an example of the 74AVCH1T45 being used in an
unidirectional logic level-shifting application.
74AVCH1T45
VCC1
VCC1
VCC2
VCC2
V
V
CC(B)
CC(A)
GND
A
1
2
3
6
5
4
DIR
B
system-1
system-2
001aag889
Fig 8. Unidirectional logic level-shifting application
Table 15. Description unidirectional logic level-shifting application
Pin
1
Name
VCC(A)
GND
A
Function
VCC1
GND
OUT
DIR
Description
supply voltage of system-1 (0.8 V to 3.6 V)
device GND
2
3
output level depends on VCC1 voltage
the GND (LOW level) determines B port to A port direction
input threshold value depends on VCC2 voltage
supply voltage of system-2 (0.8 V to 3.6 V)
4
DIR
5
B
IN
6
VCC(B)
VCC2
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
15 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 9 shows the 74AVCH1T45 being used in a bidirectional logic level-shifting
application. Since the device does not have an output enable pin, the system designer
should take precautions to avoid bus contention between system-1 and system-2 when
changing directions.
74AVCH1T45
VCC1 VCC1
I/O-1
VCC2 VCC2
I/O-2
V
V
CC(B)
CC(A)
GND
A
1
2
3
6
5
4
DIR
B
DIR CTRL
system-1
system-2
001aag890
Fig 9. Bidirectional logic level-shifting application
Table 16 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
Table 16. Description bidirectional logic level-shifting application[1]
State DIR CTRL I/O-1
I/O-2
input
Z
Description
1
2
H
H
output
Z
system-1 data to system-2
system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
3
4
L
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on bus hold.
input
output
system-2 data to system-1
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
74AVCH1T45_1
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Product data sheet
Rev. 01 — 25 October 2007
16 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
13.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 17. Typical total supply current (ICC(A) + ICC(B)
)
VCC(A)
VCC(B)
0 V
0
Unit
0.8 V
0.1
0.1
0.1
0.1
0.1
0.7
2.3
1.2 V
0.1
0.1
0.1
0.1
0.1
0.3
1.4
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.9
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.5
2.5 V
0.1
0.7
0.3
0.1
0.1
0.1
0.1
3.3 V
0.1
2.3
1.4
0.9
0.5
0.1
0.1
0 V
µA
µA
µA
µA
µA
µA
µA
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.1
0.1
0.1
0.1
0.1
0.1
13.4 Enable times
Calculate the enable times for the 74AVCH1T45 using the following formulas:
• ten (DIR to A) = tdis (DIR to B) + tpd (B to A)
• ten (DIR to B) = tdis (DIR to A) + tpd (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time
the DIR bit is switched until an output is expected. For example, if the 74AVCH1T45
initially is transmitting from A to B, then the DIR bit is switched, the B port of the device
must be disabled before presenting it with an input. After the B port has been disabled, an
input signal applied to it appears on the corresponding A port after the specified
propagation delay.
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
17 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
14. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 10. Package outline SOT363 (SC-88)
74AVCH1T45_1
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Product data sheet
Rev. 01 — 25 October 2007
18 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 11. Package outline SOT886 (XSON6)
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
19 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
15. Abbreviations
Table 18. Abbreviations
Acronym
CDM
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
CMOS
DUT
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
16. Revision history
Table 19. Revision history
Document ID
Release date
20071025
Data sheet status
Change notice
Supersedes
74AVCH1T45_1
Product data sheet
-
-
74AVCH1T45_1
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Product data sheet
Rev. 01 — 25 October 2007
20 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
17.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
21 of 22
74AVCH1T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
Application information. . . . . . . . . . . . . . . . . . 15
Unidirectional logic level-shifting application. . 15
Bidirectional logic level-shifting application. . . 16
Power-up considerations . . . . . . . . . . . . . . . . 17
Enable times. . . . . . . . . . . . . . . . . . . . . . . . . . 17
13.1
13.2
13.3
13.4
14
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 October 2007
Document identifier: 74AVCH1T45_1
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