74AVCH4T245PW [NXP]
4-bit dual supply translating transceiver with configurable voltage translation; 3-state; 4位双电源转换收发器可配置电压转换;三态
| 型号： | 74AVCH4T245PW |
| 厂家： | 
NXP |
| 描述： | 4-bit dual supply translating transceiver with configurable voltage translation; 3-state |
| 文件： | 总26页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AVCH4T245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 01 — 6 August 2009
Product data sheet
1. General description
The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level
translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It
features two data input-output ports (nAn and nBn), a direction control input (nDIR), a
output enable input (nOE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and
VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable
for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to
VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows
transmission from nBn to nAn. The output enable input (nOE) can be used to disable the
outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B outputs are in the high-impedance OFF-state. The bus hold
circuitry on the powered-up side always stays active.
The 74AVCH4T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features
I Wide supply voltage range:
N VCC(A): 0.8 V to 3.6 V
N VCC(B): 0.8 V to 3.6 V
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3B exceeds 8000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Maximum data rates:
N 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
N 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
N 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
N 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
N 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
N 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
I Suspend mode
I Bus hold on data inputs
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVCH4T245D
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AVCH4T245PW −40 °C to +125 °C
74AVCH4T245BQ −40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
4. Functional diagram
13
1B1
12
1B2
11
2B1
10
2B2
V
V
CC(B)
CC(A)
1OE
2OE
15
2
14
3
1DIR
2DIR
1A1
4
1A2
2A1
2A2
001aak280
5
6
7
Fig 1. Logic symbol
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
2 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
DIR
A1
OE
B1
B2
A2
V
CC(A)
V
CC(B)
001aak281
Fig 2. Logic diagram (one 2-bit transceiver)
5. Pinning information
5.1 Pinning
74AVCH4T245
1
16
15
14
13
12
11
10
9
V
V
CC(B)
CC(A)
1DIR
2
3
4
5
6
7
8
1OE
2OE
1B1
1B2
2B1
2B2
GND
2DIR
1A1
1A2
2A1
2A2
GND
001aak288
Fig 3. Pin configuration SOT109-1 (SO16)
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
3 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
74AVCH4T245
terminal 1
index area
74AVCH4T245
2
3
4
5
6
7
15
14
13
12
11
10
1DIR
2DIR
1A1
1A2
2A1
2A2
1OE
2OE
1B1
1B2
2B1
2B2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
CC(B)
CC(A)
1DIR
1OE
2OE
1B1
1B2
2B1
2B2
GND
2DIR
1A1
1A2
2A1
2A2
GND
(1)
GND
001aak289
Transparent top view
001aak287
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SOT403-1 (TSSOP16)
Fig 5. Pin configuration SOT763-1 (DHVQFN16)
5.2 Pin description
Table 2.
Symbol
VCC(A)
Pin description
Pin
Description
supply voltage A (nAn, nOE and nDIR inputs are referenced to VCC(A)
1
)
1DIR, 2DIR 2, 3
direction control
1A1, 1A2
2A1, 2A2
GND[1]
4, 5
data input or output
6, 7
data input or output
8, 9
ground (0 V)
2B2, 2B1
1B2, 1B1
2OE, 1OE
VCC(B)
10, 11
12, 13
14, 15
16
data input or output
data input or output
output enable input (active LOW)
supply voltage B (nBn inputs are referenced to VCC(B)
)
[1] All GND pins must be connected to ground (0 V).
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
4 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
6. Functional description
Table 3.
Function table[1]
Supply voltage
VCC(A), VCC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND[3]
Input
nOE[2]
Input/output[3]
nAn[2]
nDIR[2]
nBn[2]
L
L
nAn = nBn
input
L
H
X
X
input
Z
nBn = nAn
H
X
Z
Z
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The nAn, nDIR and nOE input circuit is referenced to VCC(A); The nBn input circuit is referenced to VCC(B)
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
−0.5
−0.5
−50
−0.5
−50
−0.5
−0.5
-
Max
+4.6
+4.6
-
Unit
V
supply voltage A
supply voltage B
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1][2][3]
[1]
VO
Active mode
VCCO + 0.5
+4.6
±50
100
-
Suspend or 3-state mode
VO = 0 V to VCCO
ICC(A) or ICC(B)
V
[2]
IO
output current
mA
mA
mA
°C
mW
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
500
[4]
Tamb = −40 °C to +125 °C
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For SO16 package: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 package: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN16 package: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
5 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
8. Recommended operating conditions
Table 5.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
0.8
0.8
0
Max
3.6
Unit
V
supply voltage A
supply voltage B
input voltage
3.6
V
3.6
V
[1]
[2]
VO
output voltage
Active mode
0
VCCO
3.6
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
−40
-
+125
5
°C
ns/V
∆t/∆V
input transition rise and fall rate
VCCI = 0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
9. Static characteristics
Table 6.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Typical static characteristics at Tamb = 25 °C[1][2]
Symbol Parameter Conditions
HIGH-level output voltage VI = VIH or VIL
IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V
VI = VIH or VIL
Min
Typ
0.69
0.07
Max
Unit
VOH
VOL
II
-
-
-
V
V
LOW-level output voltage
input leakage current
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
-
-
nDIR, nOE input; VI = 0 V or 3.6 V;
±0.025 ±0.25 µA
VCC(A) = VCC(B) = 0.8 V to 3.6 V
[3]
[4]
[5]
IBHL
bus hold LOW current
bus hold HIGH current
A or B port; VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V
A or B port; VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V
A or B port; VCC(A) = VCC(B) = 1.2 V
-
-
-
26
-
-
-
µA
µA
µA
IBHH
IBHLO
−24
27
bus hold LOW overdrive
current
[6]
[7]
[7]
[7]
IBHHO
IOZ
bus hold HIGH overdrive
current
A or B port; VCC(A) = VCC(B) = 1.2 V
-
-
-
-
-
-
−26
-
µA
µA
µA
µA
µA
µA
OFF-state output current
A or B port; VO = 0 V or VCCO
CC(A) = VCC(B) = 3.6 V
;
±0.5
±0.5
±0.5
±0.1
±0.1
±2.5
±2.5
±2.5
±1
V
suspend mode A port; VO = 0 V or VCCO
CC(A) = 3.6 V; VCC(B) = 0 V
;
;
V
suspend mode B port; VO = 0 V or VCCO
CC(A) = 0 V; VCC(B) = 3.6 V
V
IOFF
power-off leakage current A port; VI or VO = 0 V to 3.6 V;
CC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
V
B port; VI or VO = 0 V to 3.6 V;
±1
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
6 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 6.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Typical static characteristics at Tamb = 25 °C[1][2] …continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
CI
input capacitance
nDIR, nOE input; VI = 0 V or 3.3 V;
-
1.0
-
pF
V
CC(A) = VCC(B) = 3.3 V
A and B port; VO = 3.3 V or 0 V;
CC(A) = VCC(B) = 3.3 V
CI/O
input/output capacitance
-
4.0
-
pF
V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND
and then raising it to VIL max.
[4] The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC
and then lowering it to VIH min.
[5] An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6] An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7] For I/O ports, the parameter IOZ includes the input leakage current.
Table 7.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Static characteristics [1][2]
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
VIH
HIGH-level
data input
input voltage
VCCI = 0.8 V
0.70VCCI
0.65VCCI
1.6
-
-
-
-
0.70VCCI
0.65VCCI
1.6
-
-
-
-
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
nDIR, nOE input
V
V
V
2
2
VCC(A) = 0.8 V
0.70VCC(A)
-
-
-
-
0.70VCC(A)
-
-
-
-
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
data input
0.65VCC(A)
0.65VCC(A)
1.6
2
1.6
2
VIL
LOW-level
input voltage
VCCI = 0.8 V
-
-
-
-
0.30VCCI
0.35VCCI
0.7
-
-
-
-
0.30VCCI
0.35VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
nDIR, nOE input
0.8
0.8
VCC(A) = 0.8 V
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
0.8
0.8
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
7 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
[1][2]
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
VOH
HIGH-level
output
voltage
VI = VIH or VIL
IO = −100 µA;
V
V
CCO − 0.1
0.85
1.05
1.2
-
-
-
-
-
-
V
CCO − 0.1
0.85
1.05
1.2
-
-
-
-
-
-
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IO = −3 mA;
CC(A) = VCC(B) = 1.1 V
IO = −6 mA;
CC(A) = VCC(B) = 1.4 V
IO = −8 mA;
CC(A) = VCC(B) = 1.65 V
IO = −9 mA;
CC(A) = VCC(B) = 2.3 V
IO = −12 mA;
CC(A) = VCC(B) = 3.0 V
V
V
V
V
V
V
V
V
1.75
2.3
1.75
2.3
V
V
VOL
LOW-level
output
voltage
VI = VIH or VIL
IO = 100 µA;
-
-
-
-
-
-
-
0.1
0.25
0.35
0.45
0.55
0.7
-
-
-
-
-
-
-
0.1
0.25
0.35
0.45
0.55
0.7
V
V
CC(A) = VCC(B) = 0.8 V to 3.6 V
IO = 3 mA;
V
V
CC(A) = VCC(B) = 1.1 V
IO = 6 mA;
CC(A) = VCC(B) = 1.4 V
IO = 8 mA;
CC(A) = VCC(B) = 1.65 V
IO = 9 mA;
CC(A) = VCC(B) = 2.3 V
IO = 12 mA;
CC(A) = VCC(B) = 3.0 V
inputleakage nDIR, nOE input; VI = 0 V or 3.6 V;
V
V
V
V
V
V
V
V
II
±1
±5
µA
current
VCC(A) = VCC(B) = 0.8 V to 3.6 V
[3]
IBHL
bus hold
A or B port
LOW current
VI = 0.49 V;
15
25
-
-
-
-
15
25
45
90
-
-
-
-
µA
µA
µA
µA
V
CC(A) = VCC(B) = 1.4 V
VI = 0.58 V;
V
CC(A) = VCC(B) = 1.65 V
VI = 0.70 V;
CC(A) = VCC(B) = 2.3 V
VI = 0.80 V;
CC(A) = VCC(B) = 3.0 V
45
V
100
V
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
8 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
[1][2]
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
[4]
IBHH
bus hold
HIGH current
A or B port
VI = 0.91 V;
−15
−25
-
-
-
-
−15
−25
-
-
-
-
µA
V
CC(A) = VCC(B) = 1.4 V
VI = 1.07 V;
µA
µA
µA
V
CC(A) = VCC(B) = 1.65 V
VI = 1.60 V;
CC(A) = VCC(B) = 2.3 V
VI = 2.00 V;
CC(A) = VCC(B) = 3.0 V
−45
−45
V
−100
−100
V
[5]
IBHLO
IBHHO
IOZ
bus hold
LOW
overdrive
current
A or B port
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port
125
200
300
500
-
-
-
-
125
200
300
500
-
-
-
-
µA
µA
µA
µA
[6]
bus hold
HIGH
overdrive
current
VCC(A) = VCC(B) = 1.6 V
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
A or B port; VO = 0 V or VCCO
−125
−200
−300
−500
-
-
-
−125
−200
−300
−500
-
-
µA
µA
µA
µA
µA
-
-
-
-
-
[7]
[7]
OFF-state
output
current
;
±5
±30
V
CC(A) = VCC(B) = 3.6 V
suspend mode A port;
VO = 0 V or VCCO; VCC(A) = 3.6 V;
CC(B) = 0 V
-
-
-
-
±5
±5
±5
±5
-
-
-
-
±30
±30
±30
±30
µA
µA
µA
µA
V
[7]
suspend mode B port;
VO = 0 V or VCCO; VCC(A) = 0 V;
V
CC(B) = 3.6 V
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
V
V
CC(A) = 0 V;
CC(B) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
V
V
CC(B) = 0 V;
CC(A) = 0.8 V to 3.6 V
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
9 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
[1][2]
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C
Unit
Min
Max
Min
Max
ICC
supply
current
A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
-
-
10
8
-
-
55
50
µA
V
CC(B) = 0.8 V to 3.6 V
VCC(A) = 1.1 V to 3.6 V;
CC(B) = 1.1 V to 3.6 V
µA
V
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
-
8
-
-
50
-
µA
µA
−2
−12
-
-
10
8
-
-
55
50
µA
µA
V
CC(B) = 0.8 V to 3.6 V
VCC(A) = 1.1 V to 3.6 V;
CC(B) = 1.1 V to 3.6 V
V
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
A plus B port (ICC(A) + ICC(B));
−2
-
-
−12
-
µA
µA
µA
8
-
-
50
70
-
20
IO = 0 A; VI = 0 V or VCCI
;
V
V
CC(A) = 0.8 V to 3.6 V;
CC(B) = 0.8 V to 3.6 V
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI
-
16
-
65
µA
;
V
V
CC(A) = 1.1 V to 3.6 V;
CC(B) = 1.1 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND
and then raising it to VIL max.
[4] The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC
and then lowering it to VIH min.
[5] An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6] An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7] For I/O ports, the parameter IOZ includes the input leakage current.
Table 8.
VCC(A)
Typical total supply current (ICC(A) + ICC(B)
)
VCC(B)
Unit
0 V
0
0.8 V
0.1
0.1
0.1
0.1
0.1
0.3
1.6
1.2 V
0.1
0.1
0.1
0.1
0.1
0.1
0.8
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.4
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.2
2.5 V
0.1
0.3
0.1
0.1
0.1
0.1
0.1
3.3 V
0.1
1.6
0.8
0.4
0.2
0.1
0.1
0 V
µA
µA
µA
µA
µA
µA
µA
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.1
0.1
0.1
0.1
0.1
0.1
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
10 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
Table 9.
Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) = VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
CPD
power dissipation A port: (direction nAn to
0.2
0.2
0.2
0.2
0.3
0.4
pF
pF
pF
pF
pF
pF
pF
pF
capacitance
nBn); output enabled
A port: (direction nAn to
nBn); output disabled
0.2
9.5
0.6
9.5
0.6
0.2
0.2
0.2
9.7
0.6
9.7
0.6
0.2
0.2
0.2
9.8
0.6
9.8
0.6
0.2
0.2
0.2
9.9
0.6
9.9
0.6
0.2
0.2
0.3
10.7
0.7
0.4
11.9
0.7
A port: (direction nBn to
nAn); output enabled
A port: (direction nBn to
nAn); output disabled
B port: (direction nAn to
nBn); output enabled
10.7
0.7
11.9
0.7
B port: (direction nAn to
nBn); output disabled
B port: (direction nBn to
nAn); output enabled
0.3
0.4
B port: (direction nBn to
nAn); output disabled
0.3
0.4
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
11 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 10. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
VCC(B)
1.5 V
Unit
0.8 V
14.5
14.5
14.3
17.0
18.2
19.2
1.2 V
7.3
1.8 V
6.2
2.5 V
5.9
3.3 V
6.0
tpd
tdis
ten
propagation delay nAn to nBn
nBn to nAn
6.5
12.4
14.3
9.0
ns
ns
ns
ns
ns
ns
12.7
14.3
9.9
12.3
14.3
9.4
12.1
14.3
9.0
12.0
14.3
9.7
disable time
nOE to nAn
nOE to nBn
nOE to nAn
nOE to nBn
enable time
18.2
10.7
18.2
9.8
18.2
9.6
18.2
9.7
18.2
10.2
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
Table 11. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter Conditions VCC(A)
1.5 V
Unit
0.8 V
14.5
14.5
14.3
17.0
18.2
19.2
1.2 V
12.7
7.3
1.8 V
12.3
6.2
2.5 V
12.1
5.9
3.3 V
12.0
6.0
tpd
tdis
ten
propagation delay nAn to nBn
nBn to nAn
12.4
6.5
ns
ns
ns
ns
ns
ns
disable time
nOE to nAn
nOE to nBn
nOE to nAn
nOE to nBn
5.5
4.1
4.0
3.0
3.5
13.8
5.6
13.4
4.0
13.1
3.2
12.9
2.4
12.7
2.2
enable time
14.6
14.1
13.9
13.7
13.6
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
12 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation nAn to Bn
0.5
0.5
1.8
1.9
1.4
1.1
9.4
9.4
0.5
0.5
1.8
1.9
1.4
1.1
7.1
8.9
0.5
0.5
1.8
1.9
1.4
1.1
6.2
8.7
0.5
0.5
1.8
1.4
1.4
1.0
5.2
8.4
0.5
0.5
1.8
1.2
1.4
1.0
5.1 ns
8.2 ns
10.9 ns
9.1 ns
12.8 ns
7.7 ns
delay
nBn to nAn
disable time nOE to nAn
nOE to nBn
10.9
12.4
12.8
13.3
10.9
9.6
10.9
9.5
10.9
8.1
enable time nOE to nAn
nOE to nBn
12.8
10.0
12.8
8.9
12.8
7.9
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation nAn to Bn
delay
0.3
0.7
1.8
1.9
1.1
1.4
8.9
7.1
0.3
0.7
1.8
1.9
1.4
1.4
6.3
6.3
0.3
0.5
1.5
1.9
1.1
1.1
5.2
6.0
10.2
9.1
9.4
7.7
0.3
0.4
1.3
1.4
0.7
0.9
4.2
5.7
10.2
7.4
9.4
5.8
0.3
0.3
1.6
1.2
0.4
0.9
4.2 ns
5.6 ns
10.2 ns
7.6 ns
9.4 ns
5.6 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
10.2
11.3
9.4
10.2
10.3
9.4
enable time nOE to nAn
nOE to nBn
12.1
9.6
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation nAn to Bn
delay
0.1
0.6
1.8
1.7
1.0
1.2
8.7
6.2
0.1
0.6
1.6
1.7
1.0
1.2
6.0
5.3
8.6
9.9
7.2
9.2
0.1
0.5
1.8
1.6
1.0
1.0
4.9
4.9
8.6
8.7
7.2
7.4
0.1
0.3
1.3
1.2
0.6
0.8
3.9
4.6
8.6
6.9
7.2
5.3
0.3
0.3
1.6
1.0
0.4
0.8
3.9 ns
4.5 ns
8.6 ns
6.9 ns
7.2 ns
4.6 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
8.6
10.9
7.2
enable time nOE to nAn
nOE to nBn
11.7
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation nAn to Bn
delay
0.1
0.6
1.0
1.5
0.7
0.9
8.4
5.2
0.1
0.6
1.0
1.5
0.7
0.9
5.7
4.2
6.2
8.8
4.8
8.8
0.1
0.4
1.0
1.3
0.7
0.8
4.6
3.9
6.2
8.2
4.8
7.0
0.2
0.2
1.0
1.1
0.6
0.6
3.5
3.4
6.2
6.2
4.8
4.8
0.1
0.2
1.0
0.9
0.4
0.6
3.6 ns
3.3 ns
6.2 ns
5.2 ns
4.8 ns
4.0 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
6.2
10.4
4.8
enable time nOE to nAn
nOE to nBn
11.3
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation nAn to Bn
delay
0.1
0.6
0.7
1.4
0.6
0.8
8.2
5.1
0.1
0.6
0.7
1.4
0.6
0.8
5.6
4.2
5.6
9.3
3.8
8.7
0.1
0.4
0.7
1.2
0.6
0.6
4.5
3.4
5.6
8.1
3.8
6.8
0.1
0.2
0.7
1.0
0.6
0.5
3.3
3.0
5.6
6.4
3.8
4.7
0.1
0.1
0.7
0.8
0.4
0.5
2.9 ns
2.8 ns
5.6 ns
6.2 ns
3.8 ns
3.8 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
5.6
10.2
3.8
enable time nOE to nAn
nOE to nBn
11.3
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
13 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation nAn to Bn
0.5
0.5
1.8
1.9
1.4
1.1
10.4
10.4
12.0
13.7
14.1
14.7
0.5
0.5
1.8
1.9
1.4
1.1
7.9
9.8
0.5
0.5
1.8
1.9
1.4
1.1
6.9
9.6
0.5
0.5
1.8
1.4
1.4
1.0
5.8
9.3
0.5
0.5
1.8
1.2
1.4
1.0
5.7 ns
9.1 ns
12.0 ns
10.1 ns
14.1 ns
8.5 ns
delay
nBn to nAn
disable time nOE to nAn
nOE to nBn
12.0
10.6
14.1
11.0
12.0
10.5
14.1
9.8
12.0
9.0
enable time nOE to nAn
nOE to nBn
14.1
8.7
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation nAn to Bn
delay
0.3
0.7
1.8
1.9
1.1
1.4
9.8
7.9
0.3
0.7
1.8
1.9
1.4
1.4
7.0
7.0
0.3
0.5
1.5
1.9
1.1
1.1
5.8
6.6
0.3
0.4
1.3
1.4
0.7
0.9
4.7
6.3
0.3
0.3
1.6
1.2
0.4
0.9
4.7 ns
6.2 ns
11.3 ns
8.4 ns
10.4 ns
6.2 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
11.3
12.5
10.4
13.3
11.3
11.4
10.4
10.6
11.3
10.1
10.4
8.5
11.3
8.2
enable time nOE to nAn
nOE to nBn
10.4
6.4
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation nAn to Bn
delay
0.1
0.6
1.8
1.7
1.0
1.2
9.6
6.9
0.1
0.6
1.6
1.7
1.0
1.2
6.6
5.9
0.1
0.5
1.8
1.6
1.0
1.0
5.4
5.4
9.5
9.6
8.0
8.2
0.1
0.3
1.3
1.2
0.6
0.8
4.3
5.1
9.5
7.6
8.0
5.9
0.3
0.3
1.6
1.0
0.4
0.8
4.3 ns
5.0 ns
9.5 ns
7.6 ns
8.0 ns
5.1 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
9.5
9.5
12.0
8.0
10.9
8.0
enable time nOE to nAn
nOE to nBn
12.9
10.2
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation nAn to Bn
delay
0.1
0.6
1.0
1.5
0.7
0.9
9.3
5.8
0.1
0.6
1.0
1.5
0.7
0.9
6.3
4.7
6.9
10.4
5.3
9.7
0.1
0.4
1.0
1.3
0.7
0.8
5.1
4.3
6.9
9.1
5.3
7.7
0.2
0.2
1.0
1.1
0.6
0.6
4.0
3.9
6.9
6.9
5.3
5.3
0.1
0.2
1.0
0.9
0.4
0.6
4.0 ns
3.8 ns
6.9 ns
5.8 ns
5.3 ns
4.4 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
6.9
11.5
5.3
enable time nOE to nAn
nOE to nBn
12.4
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation nAn to Bn
delay
0.1
0.6
0.7
1.4
0.6
0.8
9.1
5.7
0.1
0.6
0.7
1.4
0.6
0.8
6.2
4.7
6.2
10.3
4.2
9.6
0.1
0.4
0.7
1.2
0.6
0.6
5.0
3.9
6.2
9.0
4.2
7.5
0.1
0.2
0.7
1.0
0.6
0.5
3.8
3.4
6.2
7.1
4.2
5.2
0.1
0.1
0.7
0.8
0.4
0.5
3.3 ns
3.3 ns
6.2 ns
6.9 ns
4.2 ns
4.2 ns
nBn to nAn
disable time nOE to nAn
nOE to nBn
6.2
11.3
4.2
enable time nOE to nAn
nOE to nBn
12.4
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
14 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
11. Waveforms
V
I
nAn, nBn input
GND
V
M
t
t
PLH
PHL
V
OH
nBn, nAn output
V
M
V
OL
001aak285
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. The data input (nAn, nBn) to output (nBn, nAn) propagation delay times
V
I
V
nOE input
M
GND
t
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aak286
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
Table 14. Measurement points
Supply voltage
VCC(A), VCC(B)
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input[1]
Output[2]
VM
VM
VX
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOL + 0.1 V
V
V
V
OH − 0.1 V
VOL + 0.15 V
VOL + 0.3 V
OH − 0.15 V
OH − 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
15 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 8. Load circuit for switching times
Table 15. Test data
Supply voltage
VCC(A), VCC(B)
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
VI[1]
Load
CL
VEXT
[3]
∆t/∆V[2]
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCCO
VCCI
VCCI
VCCI
≤ 1.0 ns/V
≤ 1.0 ns/V
≤ 1.0 ns/V
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
open
GND
2VCCO
open
GND
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt ≥ 1.0 V/ns
[3] VCCO is the supply voltage associated with the output port.
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
16 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
001aai476
001aai477
24
21
(1)
(2)
(3)
(4)
(5)
(6)
t
pd
(ns)
t
pd
(1)
(ns)
20
17
16
12
8
13
(2)
(3)
(4)
(5)
(6)
4
9
0
20
40
60
0
20
40
60
C
L
(pF)
C (pF)
L
a. Propagation delay (A to B); VCC(A) = 0.8 V
b. Propagation delay (A to B); VCC(B) = 0.8 V
(1) VCC(B) = 0.8 V.
(2) VCC(B) = 1.2 V.
(3) VCC(B) = 1.5 V.
(4) VCC(B) = 1.8 V.
(5) VCC(B) = 2.5 V.
(6) VCC(B) = 3.3 V.
(1) VCC(A) = 0.8 V.
(2) VCC(A) = 1.2 V.
(3) VCC(A) = 1.5 V.
(4) VCC(A) = 1.8 V.
(5) VCC(A) = 2.5 V.
(6) VCC(A) = 3.3 V.
Fig 9. Typical propagation delay versus load capacitance; Tamb = 25 °C
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
17 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
001aai478
(1)
001aai491
7
7
t
t
PHL
PLH
(ns)
(ns)
(1)
(2)
(3)
5
3
1
5
3
1
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (A to B);
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.2 V
VCC(A) = 1.2 V
001aai479
(1)
001aai480
7
5
3
1
7
t
t
PHL
(ns)
PLH
(ns)
(1)
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
c. LOW to HIGH propagation delay (A to B);
CC(A) = 1.5 V
d. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.5 V
V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 °C
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
18 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
001aai481
(1)
001aai482
7
7
t
t
PHL
PLH
(ns)
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (A to B);
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.8 V
VCC(A) = 1.8 V
001aai483
(1)
001aai486
7
5
3
1
7
t
t
PHL
(ns)
PLH
(ns)
(1)
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
c. LOW to HIGH propagation delay (A to B);
CC(A) = 2.5 V
d. HIGH to LOW propagation delay (A to B);
VCC(A) = 2.5 V
V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 °C
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
19 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
001aai485
(1)
001aai484
7
7
t
t
PHL
(ns)
PLH
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (A to B);
CC(A) = 3.3 V
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 3.3 V
V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 °C
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
20 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 13. Package outline SOT109-1 (SO16)
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
21 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 14. Package outline SOT403-1 (TSSOP16)
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
22 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 15. Package outline SOT763-1 (DHVQFN16)
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
23 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
14. Abbreviations
Table 16. Abbreviations
Acronym
CDM
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
CMOS
DUT
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
15. Revision history
Table 17. Revision history
Document ID
Release date
20090806
Data sheet status
Change notice
Supersedes
74AVCH4T245_1
Product data sheet
-
-
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
24 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AVCH4T245_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 6 August 2009
25 of 26
74AVCH4T245
NXP Semiconductors
4-bit dual supply translating transceiver; 3-state
18. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical propagation delay characteristics. . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 August 2009
Document identifier: 74AVCH4T245_1
相关型号：
74AVCH4T245PW,112
74AVCH4T245 - 4-bit dual supply translating transceiver with configurable voltage translation; 3-state TSSOP 16-Pin
NXP
74AVCH4T245PW,118
74AVCH4T245 - 4-bit dual supply translating transceiver with configurable voltage translation; 3-state TSSOP 16-Pin
NXP
74AVCH4T245PW-Q100
4-bit dual supply translating transceiver with configurable voltage translation 3-state
NEXPERIA
74AVCH4T245PWRE4
4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
TI
74AVCH4T245PWRG4
4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
TI
74AVCH4T245PWTE4
4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
TI
74AVCH4T245PWTG4
4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
TI
74AVCH4T245RGYRG4
4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
TI
74AVCH4T245RSVR-NT
4-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs
TI
74AVCH4T245RSVRG4
4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
TI
74AVCH8T245
8-bit dual supply translating transceiver with configurable voltage translation; 3-state
NXP
©2020 ICPDF网 联系我们和版权申明