74CBTLV3126BQ-Q100
更新时间：2024-10-29 14:20:17
品牌：NXP
描述：CBTLV/3B SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT762-1, QFN-14
概述
规格参数
数据手册74CBTLV3126BQ-Q100 概述
CBTLV/3B SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT762-1, QFN-14 总线驱动器/收发器
74CBTLV3126BQ-Q100 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Transferred |
| 零件包装代码： | QFN | 包装说明： | 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT762-1, QFN-14 |
| 针数： | 14 | Reach Compliance Code： | unknown |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.6 |
| 系列： | CBTLV/3B | JESD-30 代码： | R-PQCC-N14 |
| JESD-609代码： | e4 | 长度： | 3 mm |
| 逻辑集成电路类型： | BUS DRIVER | 湿度敏感等级： | 1 |
| 位数： | 1 | 功能数量： | 4 |
| 端口数量： | 2 | 端子数量： | 14 |
| 最高工作温度： | 125 °C | 最低工作温度： | -40 °C |
| 输出特性： | 3-STATE | 输出极性： | TRUE |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | HVQCCN |
| 封装形状： | RECTANGULAR | 封装形式： | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE |
| 峰值回流温度（摄氏度）： | 260 | 传播延迟（tpd）： | 0.31 ns |
| 筛选级别： | AEC-Q100 | 座面最大高度： | 1 mm |
| 最大供电电压 (Vsup)： | 3.6 V | 最小供电电压 (Vsup)： | 2.3 V |
| 标称供电电压 (Vsup)： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | AUTOMOTIVE |
| 端子面层： | NICKEL PALLADIUM GOLD | 端子形式： | NO LEAD |
| 端子节距： | 0.5 mm | 端子位置： | QUAD |
| 处于峰值回流温度下的最长时间： | 30 | 宽度： | 2.5 mm |
| Base Number Matches： | 1 |
74CBTLV3126BQ-Q100 数据手册
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PDF下载74CBTLV3126-Q100
4-bit bus switch
Rev. 1 — 3 April 2013
Product data sheet
1. General description
The 74CBTLV3126-Q100 provides a 4-bit high-speed bus switch with separate output
enable inputs (1OE to 4OE). The low on-state resistance of the switch allows connections
to be made with minimal propagation delay. The switch is disabled (high-impedance
OFF-state) when the output enable (nOE) input is LOW.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be
tied to the GND through a pull-down resistor. The current-sinking capability of the driver
determines the minimum value of the resistor.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Supply voltage range from 2.3 V to 3.6 V
Standard ’126’-type pinout
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
5 switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
IOFF circuitry provides partial Power-down mode operation
Multiple package options
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74CBTLV3126PW-Q100 40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14
leads; body width 4.4 mm
SOT402-1
74CBTLV3126BQ-Q100 40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1
very thin quad flat package; no leads; 14
terminals; body 2.5 3 0.85 mm
4. Functional diagram
1OE
1A
2OE
2A
1B
2B
3B
3OE
3A
4OE
4A
nA
nB
4B
nOE
001aaj023
001aal245
Fig 1. Logic symbol
Fig 2. Logic diagram (one switch)
74CBTLV3126_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
2 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
5. Pinning information
5.1 Pinning
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This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration SOT402-1 (TSSOP14)
Fig 4. Pin configuration SOT762-1 (DHVQFN14)
5.2 Pin description
Table 2.
Symbol
1OE to 4OE
1A to 4A,
1B to 4B
GND
Pin description
Pin
Description
1, 4, 10, 13
output enable input
A input/output
2, 5, 9, 12
3, 6, 8, 11
B output/input
7
ground (0 V)
VCC
14
-
positive supply voltage
not connected
n.c.
6. Functional description
Table 3.
Function table[1]
Output enable input OE
Function switch
OFF-state
L
H
ON-state
[1] H = HIGH voltage level; L = LOW voltage level.
74CBTLV3126_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
3 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
0.5
50
50
-
Max
+4.6
+4.6
VCC + 0.5
-
Unit
V
supply voltage
[1]
[2]
input voltage
control inputs
V
VSW
IIK
switch voltage
enable and disable mode
VI < 0.5 V
V
input clamping current
switch clamping current
switch current
mA
mA
mA
mA
mA
C
ISK
VI < 0.5 V
-
ISW
VSW = 0 V to VCC
128
+100
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
100
65
-
storage temperature
total power dissipation
+150
500
[3]
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage rating may be exceeded if the input clamping current ratings are observed.
[2] The switch voltage ratings may be exceeded if switch clamping current ratings are observed
[3] For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Max
3.6
Unit
supply voltage
input voltage
2.3
0
V
VI
control inputs
3.6
V
VSW
switch voltage
ambient temperature
enable and disable mode
0
VCC
+125
200
V
Tamb
40
0
C
ns/V
t/V
input transition rise and fall rate pin nOE; VCC = 2.3 V to 3.6 V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
1.7
2.0
-
Typ[1]
Max
-
Min
1.7
2.0
-
Max
-
VIH
VIL
HIGH-level
input voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
-
-
-
-
-
V
-
-
V
LOW-levelinput VCC = 2.3 V to 2.7 V
voltage
0.7
0.9
1.0
0.7
0.9
20
V
VCC = 3.0 V to 3.6 V
-
-
V
II
input leakage
current
pin nOE; VI = GND to VCC
VCC = 3.6 V
;
-
-
A
IS(OFF)
OFF-state
VCC = 3.6 V; see Figure 5
-
-
1
-
20
A
leakage current
74CBTLV3126_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
4 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
Table 6.
Static characteristics …continued
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
IS(ON)
IOFF
ICC
ON-state
leakage current
VCC = 3.6 V; see Figure 6
VI or VO = 0 V to 3.6 V;
-
-
1
-
20
A
A
A
power-off
leakage current VCC = 0 V
-
-
-
-
10
-
-
50
supply current VI = GND or VCC; IO = 0 A;
10
50
VSW = GND or VCC
VCC = 3.6 V
;
[2]
ICC
additional
supply current
pin nOE; VI = VCC 0.6 V;
SW = GND or VCC
VCC = 3.6 V
-
-
300
-
2000
A
V
;
CI
input
capacitance
pin nOE; VCC = 3.3 V;
VI = 0 V to 3.3 V
-
-
-
0.9
5.2
-
-
-
-
-
-
-
-
-
pF
pF
pF
CS(OFF) OFF-state
capacitance
VCC = 3.3 V; VI = 0 V to 3.3 V
CS(ON)
ON-state
VCC = 3.3 V; VI = 0 V to 3.3 V
14.3
capacitance
[1] All typical values are measured at Tamb = 25 C.
[2] One input at 3 V, other inputs at VCC or GND.
9.1 Test circuits
V
CC
V
CC
nOE
nB
nOE
nA
V
V
IH
IL
I
S
nA
nB
A
A
A
I
I
S
S
V
GND
V
V
GND
V
O
I
O
I
001aal249
001aal250
VI = VCC or GND and VO = GND or VCC
.
VI = VCC or GND and VO = open circuit.
Fig 5. Test circuit for measuring OFF-state leakage
current (one switch)
Fig 6. Test circuit for measuring ON-state leakage
current (one switch)
74CBTLV3126_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
5 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
9.2 ON resistance
Table 7.
Resistance RON
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
RON
ON resistance VCC = 2.3 V to 2.7 V;
see Figure 8 to Figure 10
ISW = 64 mA; VI = 0 V
ISW = 24 mA; VI = 0 V
ISW = 15 mA; VI = 1.7 V
-
-
-
4.2
4.2
8.4
8.0
8.0
-
-
-
15.0
15.0
60.0
40.0
VCC = 3.0 V to 3.6 V;
see Figure 11 to Figure 13
ISW = 64 mA; VI = 0 V
ISW = 24 mA; VI = 0 V
ISW = 15 mA; VI = 2.4 V
-
-
-
4.0
4.0
6.2
7.0
7.0
-
-
-
11.0
11.0
25.5
15.0
[1] Typical values are measured at Tamb = 25 C and nominal VCC
.
[2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
9.3 ON resistance test circuit and graphs
001aai109
11
R
ON
(Ω)
9
7
5
3
V
SW
V
V
CC
(1)
(2)
nOE
nA
V
IH
nB
(3)
(4)
V
GND
I
SW
I
0
0.5
1.0
1.5
2.0
2.5
V (V)
I
001aal251
RON = VSW / ISW
.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3)
Tamb = 25 C.
(4) Tamb = 40 C.
Fig 7. Test circuit for measuring ON resistance
(one switch)
Fig 8. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 15 mA
74CBTLV3126_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
6 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
001aai110
001aai111
11
11
R
ON
R
ON
(Ω)
(Ω)
9
7
5
3
9
7
5
3
(1)
(2)
(1)
(2)
(3)
(4)
(3)
(4)
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 9. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 24 mA
Fig 10. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 64 mA
001aai105
001aai106
8
8
R
ON
R
ON
(Ω)
(Ω)
6
4
2
6
4
2
(1)
(2)
(1)
(2)
(3)
(4)
(3)
(4)
0
1
2
3
4
0
1
2
3
4
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 11. ON resistance as a function of input voltage;
VCC = 3.3 V; ISW = 15 mA
Fig 12. ON resistance as a function of input voltage;
VCC = 3.3 V; ISW = 24 mA
74CBTLV3126_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
7 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
001aai107
7.5
R
ON
(Ω)
6.5
5.5
4.5
3.5
2.5
(1)
(2)
(3)
(4)
0
1
2
3
4
V (V)
I
(1)
(2)
T
amb = 125 C.
amb = 85 C.
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 13. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA
10. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 16
Symbol Parameter Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2][3]
tpd
ten
tdis
propagation delay nA to nB or nB to nA;
see Figure 14
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
-
-
-
-
0.13
0.20
-
-
0.20
0.31
ns
ns
[4]
enable time
disable time
nOE to nA or nB;
see Figure 15
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.0
1.0
2.5
2.2
4.5
4.2
1.0
1.0
6.0
6.0
ns
ns
[5]
nOE to nA or nB;
see Figure 15
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.0
1.0
2.6
3.4
4.7
4.8
1.0
1.0
6.5
6.5
ns
ns
[1] All typical values are measured at Tamb = 25 C and at nominal VCC
.
[2] The propagation delay is the calculated RC time constant of the on-state resistance of the switch and the load capacitance, when driven
by an ideal voltage source (zero output impedance).
[3] tpd is the same as tPLH and tPHL
[4] en is the same as tPZH and tPZL
.
t
.
[5] tdis is the same as tPHZ and tPLZ
.
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
8 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
11. Waveforms
V
I
V
V
M
input
0 V
M
t
t
PLH
PHL
V
OH
V
V
M
output
M
V
OL
001aai367
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 14. The data input (nA or nB) to output (nB or nA) propagation delays
Table 9.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VI
tr = tf
VX
VY
2.3 V to 2.7 V
3.0 V to 3.6 V
0.5VCC
0.5VCC
VCC
VCC
2.0 ns
2.0 ns
0.5VCC
0.5VCC
VOL + 0.15 V
VOL + 0.3 V
VOH 0.15 V
VOH 0.3 V
V
I
nOE input
output
V
M
GND
t
t
PZL
PLZ
V
CC
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
switch
enabled
switch
disabled
switch
enabled
001aal252
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. Enable and disable times
74CBTLV3126_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
9 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 16. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC
Load
CL
VEXT
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
2.3 V to 2.7 V
3.0 V to 3.6 V
30 pF
50 pF
500
500
open
GND
2VCC
74CBTLV3126_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
10 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
12. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 17. Package outline SOT402-1 (TSSOP14)
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
11 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 18. Package outline SOT762-1 (DHVQFN14)
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
12 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
13. Abbreviations
Table 11. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Military
HBM
MIL
MM
Machine Model
14. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74CBTLV3126_Q100 v.1 20130403
Product data sheet
-
-
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
13 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
14 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74CBTLV3126_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 3 April 2013
15 of 16
74CBTLV3126-Q100
NXP Semiconductors
4-bit bus switch
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
7
8
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
9
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 6
9.1
9.2
9.3
10
11
12
13
14
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 April 2013
Document identifier: 74CBTLV3126_Q100
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