74F114 [NXP]
Dual J-K negative edge-triggered flip-flop with common clock and reset; 双JK负边沿触发的触发器与普通时钟和复位
| 型号： | 74F114 |
| 厂家： | 
NXP |
| 描述： | Dual J-K negative edge-triggered flip-flop with common clock and reset |
| 文件： | 总6页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
with common clock and reset
74F114
DESCRIPTION
PIN CONFIGURATION
The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with
common clock and reset inputs, features individual J, K, Clock (CP),
Set (SD) and Reset (RD) inputs, true and complementary outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table regardless of the level at the other inputs.
RD
K0
1
2
3
4
5
14
V
CC
13 CP
12 K1
11 J1
J0
SD0
Q0
A High level on the clock (CP) input enables the J and K inputs and
data will be accepted. The logic levels and data will be accepted.
The logic levels at the J and K inputs may be allowed to change
while the CP is High and flip-flop will perform according to the
Function Table as long as minimum setup and hold times are
observed. Output changes are initiated by the High-to-Low transition
of the CP.
10 SD1
Q0
6
7
9
8
Q1
Q1
GND
SF00110
ORDERING INFORMATION
TYPICAL
COMMERCIAL RANGE
= 5V ±10%,
SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
V
CC
DESCRIPTION
PKG. DWG. #
T
amb
= 0°C to +70°C
74F114
100MHz
15mA
14-pin plastic DIP
14-pin plastic SO
N74F114N
SOT27-1
N74F114D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
J0, J1
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
20µA/0.6mA
J inputs
K inputs
1.0/1.0
1.0/1.0
1.0/5.0
1.0/10.0
1.0/8.0
50/33
K0, K1
20µA/0.6mA
SD0, SD1
RD
Set inputs (active Low)
Reset input (active Low)
Clock Pulse input (active falling edge)
Data outputs
20µA/3.0mA
20µA/6.0mA
CP
20µA/4.8mA
Q0, Q0; Q1, Q1
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
3
11
J1
2
12
1
R
13
C1
J0
K0
K1
13
4
CP
SD0
4
3
2
5
6
S
1K
1J
1
RD0
SD1
10
Q1 Q1
Q0 Q0
10
11
12
9
8
9
8
5
6
V
= Pin 14
CC
GND = Pin 7
SF00112
SF00111
1
1996 Mar 14
853–0340 16572
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
with common clock and reset
74F114
LOGIC DIAGRAM
Q
Q
SD
K
RD
J
TO OTHER
FLIP-FLOP
CP
SF00113
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD
L
RD
H
L
CP
X
X
X
↓
J
X
X
X
h
l
K
X
X
X
l
Q
Q
L
H
L
Asynchronous Set
Asynchronous Reset
Undetermined *
Toggle
H
L
H
H*
q
L
H*
q
H
H
H
H
H
H
H
H
↓
h
l
L
H
L
Load “0” (Reset)
Load “1” (Set)
↓
h
l
H
q
↓
l
q
Hold “no change”
H = High voltage level
h = High voltage level one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don’t care
↓ = High-to-Low clock transition
Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level
Set and Reset are independent of clock
Simultaneous Low on both SD and RD makes both Q and Q High.
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
40
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
2
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
with common clock and reset
74F114
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
5.0
SYMBOL
PARAMETER
UNIT
MIN
4.5
MAX
V
Supply voltage
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
20
T
amb
Operating free-air temperature range
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
V
2
MIN
2.5
TYP
MAX
V
V
V
V
V
V
V
= MIN, V = MAX ±10%V
CC
IL
CC
V
OH
High-level output voltage
= MIN, I = MAX
±5%V
2.7
3.4
IH
OH
CC
= MIN, V = MAX ±10%V
0.35
0.35
0.50
0.50
–1.2
100
20
CC
IL
CC
CC
V
V
Low-level output voltage
V
OL
= MIN, I = MAX
±5%V
IH
OL
Input clamp voltage
= MIN, I = I
IK
–0.73
V
IK
CC
CC
CC
I
I
Input current at maximum input voltage
High-level input current
Jn, Kn
= MAX, V = 7.0V
µA
I
I
I
= MAX, V = 2.7V
µA
IH
I
–0.6
–4.8
–3.0
–6.0
–150
21
mA
mA
mA
mA
mA
mA
CP
I
Low-level input current
SDn
V
CC
= MAX, V = 0.5V
IL
I
RD
3
I
I
Short-circuit output current
V
V
= MAX
= MAX
–60
OS
CC
4
Supply current (total)
15
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Measure I with the clock input grounded and all outputs open, with the Q and Q outputs High in turn.
CC
3
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
with common clock and reset
74F114
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
= +5.0V
= +25°C
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
amb
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
85
100
80
MHz
ns
MAX
t
t
Propagation delay
CP to Qn or Qn
2.0
2.0
5.0
5.5
6.5
7.5
2.0
2.0
7.5
8.5
PLH
PHL
t
t
Propagation delay
SDn, RD to Qn or Qn
2.0
2.0
4.5
4.5
6.5
6.5
2.0
2.0
7.5
7.5
PLH
PHL
Waveform 2,3
ns
AC SETUP REQUIREMENTS
LIMITS
V
= +5.0V
= +25°C
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
amb
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
S
Setup time, High or Low
Jn, Kn to CP
4.0
3.5
5.0
4.0
S
Waveform 1
Waveform 1
Waveform 1
Waveform 2,3
Waveform 2,3
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Jn, Kn to CP
0.0
0.0
0.0
0.0
h
t (L)
h
t (H)
CP Pulse width
High or Low
4.5
4.5
5.0
5.0
W
t (L)
W
SDn, RD Pulse width
Low
t (L)
W
4.5
4.5
5.0
5.0
Recovery time
SDn, RD to CP
t
REC
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
Kn
Jn
Jn, Kn
V
V
V
V
M
M
M
M
Jn
Kn
t (H)
t (H)
h
t (L)
s
t (L)
h
s
f
max
t
(L)
w
CP
Qn
V
V
M
V
M
M
t
(H)
w
t
PHL
t
PLH
V
V
M
M
M
t
t
PLH
PHL
V
M
V
Qn
SF00114
Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width
4
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
with common clock and reset
74F114
Jn, Kn
t
(L)
w
SDn
CP
V
V
M
M
t
REC
V
M
t
PLH
Qn
Qn
V
V
M
M
t
PHL
SF00115
Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock
Jn, Kn
t
(L)
w
RD
CP
V
V
M
M
t
REC
V
M
t
PHL
Qn
Qn
V
V
M
M
t
PLH
SF00116
Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock
5
1996 Mar 14
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
with common clock and reset
74F114
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
74F
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
6
1996 Mar 14
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