74F194 [NXP]
4-bit bidirectional universal shift register; 4位双向通用移位寄存器
| 型号： | 74F194 |
| 厂家： | 
NXP |
| 描述： | 4-bit bidirectional universal shift register |
| 文件： | 总10页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F194
4-bit bidirectional universal shift register
Product specification
IC15 Data Handbook
1989 Apr 04
Philips
Semiconductors
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
FEATURES
PIN CONFIGURATION
• Shift right and shift left capability
MR
1
2
3
4
5
16
V
CC
• Synchronous parallel and serial data transfer
• Easily expanded for both serial and parallel operation
• Asynchronous Master Reset
D
15 Q0
14 Q1
13 Q2
12 Q3
11 CP
10 S1
SR
D0
D1
D2
D3
• Hold (do nothing) mode
6
7
8
DESCRIPTION
D
SL
The functional characteristics of the 74F194 4-Bit Bidirectional Shift
Register are indicated in the Logic Diagram and Function Table. The
register is fully synchronous, with all operations taking place in less
than 9ns (typical) for 74F, making the device especially useful for
implementing very high speed CPUs, or for memory buffer registers.
GND
9
S0
SF00167
The 74F194 design has special logic features which increase the
range of application. The synchronous operation of the device is
determined by two Mode Select inputs, S0 and S1. As shown in the
Mode Select-Function Table, data can be entered and shifted from
left to right (shift right, Q0→Q1, etc.), or right to left (shift left,
Q3→Q2, etc.), or parallel data can be entered, loading all 4 bits of
the register simultaneously. When both S0 and S1 are Low, existing
data is retained in a hold (do nothing) mode. The first and last
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
74F194
150MHz
33mA
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%,
stages provide D-type Serial Data inputs (D , D ) to allow
SR
SL
V
amb
DESCRIPTION
PKG DWG #
CC
multistage shift right or shift left data transfers without interfering
with parallel load operation. Mode Select and data inputs on the
74F194 are edge-triggered, responding only to the Low-to-High
transition of the Clock (CP). Therefore, the only timing restriction is
that the Mode Select and selected data inputs must be stable one
setup time prior to the Low-to-High transition of the clock pulse.
Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data
T
= 0°C to +70°C
16-pin plastic DIP
16-pin plastic SO
N74F194N
SOT38-4
N74F194D
SOT109-1
(D , D ) can change when the clock is in either state, provided
SR
SL
only the recommended setup and hold times, with respect to the
clock rising edge, are observed. The four Parallel Data inputs
(D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs when
S0 and S1 are High is transferred to the Q0–Q3 outputs
respectively, following the next Low-to-High transition of the clock.
When Low, the asynchronous Master Reset (MR) overrides all other
input conditions and forces the Q outputs Low.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
Parallel data inputs
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
20µA/0.6mA
D0–D3
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
D
Serial data input (Shift Right)
Serial data input (Shift Left)
Mode Select inputs
20µA/0.6mA
SR
D
20µA/0.6mA
SL
S0, S1
CP
20µA/0.6mA
Clock Pulse input (active rising edge)
Asynchronous master Reset input (Active Low)
Data outputs
20µA/0.6mA
MR
20µA/0.6mA
Q0–Q3
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
2
April 4, 1989
853–0354 96224
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
LOGIC SYMBOL
IEC/IEEE SYMBOL
2
3
4
5
6
7
SRG8
1
9
R
0
0
3
M
10
11
D
D0
D1
D2
D3
D
SR
SL
1
C4
9
10
11
1
S0
S1
1 → /2 ←
CP
2
3
4
5
6
7
1, 4D
3, 4D
3, 4D
3, 4D
3, 4D
2, 4D
15
MR
Q2 Q3
13 12
14
13
Q0 Q1
12
V
= Pin 24
CC
15
14
GND = Pin 12
SF00168
SF00169
LOGIC DIAGRAM
10
S1
9
S0
12
13
14
15
7
S
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
D
SL
6
5
4
3
CP
R
D3
D2
D1
D0
R
R
R
R
D
D
D
D
S
CP
R
S
CP
R
S
CP
R
2
1
D
SR
MR
11
CP
V
= Pin 24
CC
GND = Pin 12
SF00170
3
April 4, 1989
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
FUNCTION TABLE
INPUTS
OUTPUTS
Q1 Q2
OPERATING MODES
CP
X
X
↑
MR
L
S1
X
l
S0
X
l
D
D
Dn
X
Q0
L
Q3
L
SR
SL
X
X
X
X
l
X
L
L
Reset (clear)
H
X
l
X
q0
q1
q1
L
q1
q2
q2
q0
q0
d1
q2
q3
q3
q1
q1
d2
q3
L
Hold (do nothing)
H
h
h
l
l
X
Shift left
↑
H
l
h
X
X
X
X
H
↑
H
h
h
h
X
q2
q2
d3
Shift right
↑
H
l
h
X
X
H
↑
H
h
dn
d0
Parallel load
H = High voltage level
h = High voltage level one setup time prior to Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
40
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
20
T
amb
Operating free-air temperature range
0
+70
4
April 4, 1989
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
DC ELECTRICAL CHARACTERISTICS
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
2
MIN
2.5
TYP
V
V
V
V
V
V
V
V
V
V
= MIN, V = MAX ±10%V
CC
IL
CC
3
V
OH
High-level output voltage
V
= MIN, I = MAX
±5%V
2.7
3.4
0.30
0.30
–0.73
IH
OH
CC
= MIN, V = MAX ±10%V
0.50
V
CC
IL
CC
CC
V
V
Low-level output voltage
OL
= MIN, I = MAX
±5%V
0.50
IH
OL
Input clamp voltage
= MIN, I = I
IK
–1.2
100
20
V
IK
CC
CC
CC
CC
CC
CC
I
I
I
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
µA
µA
mA
mA
mA
I
I
= MAX, V = 2.7V
IH
I
Low-level input current
= MAX, V = 0.5V
–0.6
–150
46
IL
I
4
Short-circuit output current
= MAX
= MAX
–60
OS
5
Supply current (total)
33
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Output High state will change to Low stat if an external voltage of less than 0.0V is applied.
4. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
5. With all outputs open, D inputs grounded and a 4.5V applied to S0, S1, MR and the serial inputs, I is tested with a momentary ground,
i
CC
then 4.5V applied to CP.
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
= +5.0V
= +25°C
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
amb
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
105
150
90
MHz
ns
MAX
t
t
Propagation delay
CP to Qn
3.5
3.5
5.2
5.5
7.0
7.0
3.5
3.5
8.0
8.0
PLH
PHL
Propagation delay
MR to Qn
t
Waveform 2
4.5
8.6
12.0
4.5
14.0
ns
PHL
AC SETUP REQUIREMENTS
LIMITS
V
= +5.0V
= +25°C
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
amb
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
S
Setup time, High or Low
4.0
4.0
4.0
4.0
S
Waveform 3
Waveform 3
Waveform 3
Waveform 3
ns
ns
ns
ns
Dn, D , D to CP
SL SR
t (H)
Hold time, High or Low
Dn, D , D to CP
0
0
1.0
1.0
h
t (L)
h
SL
SR
t (H)
Setup time, High or Low
Sn to CP
8.0
8.0
9.0
8.0
S
t (L)
S
t (H)
Hold time, High or Low
Sn to CP
0
0
0
0
h
t (L)
h
t (H)
CP Pulse width, High
MR Pulse width, Low
Recovery time, MR to CP
Waveform 1
Waveform 2
Waveform 2
5.0
5.0
7.0
5.5
5.0
8.0
ns
ns
ns
W
t (L)
W
t
REC
5
April 4, 1989
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
MR
CP
1/f
V
V
M
M
MAX
t
w
(L)
t
REC
CP
Qn
V
V
V
M
t
M
M
t
V
M
(H)
w
PLH
t
PHL
t
PHL
V
V
M
M
Qn
V
M
SF00171
SF00158
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery Time
Dn, D
,
SL
SR
V
V
V
V
D
M
M
M
M
S0, S1
t (H)
t
(H)
t (L)
t
(L)
s
h
s
h
CP
V
V
M
M
SF00172
Waveform 3. Setup and Hold Times
TIMING DIAGRAM
Typical Clear, Load, Shift-Right, Shift-Left and Inhibit Sequence
CP
S0
S1
MR
SERIAL
DATA
INPUTS
D
SR
D
SL
D0
D1
D2
D3
H
L
PARALLEL
DATA
INPUTS
H
L
Q0
Q1
Q2
Q3
OUTPUTS
CLEAR
SHIFT RIGHT
SHIFT LEFT
INHIBIT
CLEAR
LOAD
SF00173
6
April 4, 1989
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
74F
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
7
April 4, 1989
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
8
1989 Apr 04
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
9
1989 Apr 04
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74F194
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05095
Document order number:
Philips
Semiconductors
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