74F381 [NXP]
Arithmetic Logic Unit; 算术逻辑单元
| 型号： | 74F381 |
| 厂家： | 
NXP |
| 描述： | Arithmetic Logic Unit |
| 文件： | 总7页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
FEATURES
PIN CONFIGURATION
• Low-input loading minimizes drive requirements
1
2
3
4
5
20
19
18
17
16
A1
B1
A0
B0
S0
S1
S2
F0
F1
V
CC
• Performs six arithmetic and logic functions
A2
B2
A3
B3
Cn
P
• Selectable Low (clear) and High (preset) functions
• Carry Generate and Propagate outputs for use with Carry
look-ahead generator
6
7
8
9
15
14
13
12
11
DESCRIPTION
The 74F381 performs three arithmetic and three logic operations on
two 4-bit words, A and B. Three additional Select (S0–S2) input
codes force the Function outputs Low or High. Carry Propagate (P)
and Generate (G) ouputs are provided for use with the 74F182
Carry Look Ahead Generator for high-speed expansion to longer
word lengths. For ripple expansion, refer to the 74F382 ALU data
sheet.
G
F3
F2
GND 10
SF00921
Signals applied to the Select inputs (S0–S2) determine the mode of
operation, as indicated in the Function Select Table. An extensive
listing of input and output function levels is shown in the Function
Table. The circuit performs the arithmetic functions for either
active-HIgh or active-Low operands, with output levels in the same
convention. In the subtract operating modes, it is necessary to force
a Carry (High for active-HIgh operands, Low for active-Low
operands) into the Cn input of the least significant package. The
Carry Generate (G) and Carry Propagate (P) outputs supply input
signals to the 74F182 Carry look-ahead generator for expansion to
longer word length, as shown in Figure 1. Note that a 74F382 ALU is
used for the most significant package. Typical delays for Figure 1
are given in Table 1.
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT (TOTAL)
TYPE
74F381
6.5ns
59mA
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
DESCRIPTION
V
CC
amb
20-pin plastic DIP
20-pin plastic SO
N74F381N
N74F381D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
LOAD VALUE
74F (U.L.)
HIGH/LOW
PINS
DESCRIPTION
HIGH/LOW
20µA/2.4mA
20µA/2.4mA
20µA/0.6mA
20µA/2.4mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
A0 – A3
B0 – B3
S0 – S2
Cn
A operand inputs
A operand inputs
Function select inputs
Carry input
1.0/4.0
1.0/4.0
1.0/1.0
1.0/4.0
50/33
P
Carry Propagate ouptut (active-Low)
Carry Generate ouptut (active-Low)
Outputs
G
50/33
F0–F3
50/33
NOTE:
One (1.0) FAST unit load is defined as 20µA in the High state and 0.6mA in the Low state.
1
1989 Mar 01
853–0418 95907
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
LOGIC SYMBOL
IEC/IEEE SYMBOL
5
6
7
ALU
0
4
3
4
1
2
19 18 17 16
0
7
M
14
13
(1/2/3) CP
(1/2/3) CG
A0 B0 A1 B1 A2 B2 A3 B3
(1/2) Bl
3 Cl
15
15
5
Cn
G
P
13
14
S0
S1
S2
3
4
6
8
9
P
[1]
7
Q
F0 F1 F2 F3
1
P
[2]
[4]
2
Q
19
18
P
8
9
11 12
11
V
= Pin 20
CC
Q
GND = Pin 10
SF00922
17
16
P
12
[8]
Q
SF00923
2
1989 Mar 01
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
LOGIC DIAGRAM
15
Cn
3
A0
8
F0
4
B0
1
A1
9
F1
2
B1
19
A2
11
F2
18
B2
17
A3
12
F3
14
P
16
B3
13
G
5
S0
6
S1
7
S2
V
= Pin 20
CC
GND = Pin 10
SF00924
3
1989 Mar 01
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
FUNCTION TABLE
INPUTS
OUTPUTS
F2 F3
OPERATING
MODE
S0
L
S1
L
S2
L
Cn
X
L
An
X
L
Bn
X
L
F0
L
F1
L
G
L
P
L
L
H
H
L
L
H
H
L
Clear
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
H
H
L
H
L
L
L
L
H
L
H
L
H
L
H
L
H
L
B minus A
L
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
L
H
L
L
L
L
H
H
L
H
H
H
H
L
H
L
L
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
L
H
L
H
L
L
L
L
L
L
H
L
H
L
L
L
L
H
H
L
L
H
H
L
H
H
L
H
H
L
L
L
L
H
L
H
L
H
H
H
L
L
A minus B
L
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
L
L
L
H
L
L
L
H
H
L
H
L
H
L
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
L
L
L
H
L
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
L
L
H
H
L
L
L
L
H
L
L
A Plus B
L
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
L
L
H
L
H
H
L
H
H
L
H
H
L
H
H
L
A ę B
A + B
AB
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
L
H
H
H
L
L
L
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
H
L
Preset
H
H
H
H = High voltage level
L
X
=
=
Low voltage level
Don’t care
4
1989 Mar 01
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
FUNCTION SELECT TABLE
Table 1. 16-Bit Delay Tabulation
SELECT
TOWARD
OUTPUT
Cn+4, OVR
OPERATING
MODE
PATH SEGMENT
F
S0
L
S1
L
S2
L
Ai or Bi to P
Pi to Cn+i (74F182)
Cn to F
7.2ns
6.2ns
8.1ns
–
7.2ns
6.2ns
–
Clear
B minus A
A minus B
A Plus B
A ę B
H
L
L
L
H
H
L
L
Cn to Cn+4, OVR
Total Delay
8.0ns
21.4ns
H
L
L
21.5ns
H
H
H
H
H
L
L
A + B
H
H
AB
H
Preset
H = High voltage level
Low voltage level
L
=
APPLICATION
A0–A3
4
B0–B3
A4–A7
4
B4–B7
A8–A11 B8–B11
A12–A15
4
B12–B15
4
4
4
4
4
A
B
A
B
A
B
A
B
Cn+4
C
Cn
Cn
Cn
Cn
C
IN
OUT
74F381
74F381
74F381
Q
74F382
S
S
S
S
OVERFLOW
OVR
F
Q
P
F
Q
P
F
P
F
3
3
3
3
SELECT
3
F0–F3
Cn
F4–F7
F8–F11
F12–F15
G0 P0
Cn+x
G1 P1
Cn+y
G2 P2
Cn+z
74F182
SF00925
Figure 1. 16-bit Look-ahead Carry ALU Expansion
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +1
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in High output state
Current applied to output in Low output state
–0.5 to V
V
OUT
CC
40
mA
°C
°C
OUT
T
amb
Operating free-air temperature range
Storage temperature range
0 to +70
T
STG
–65 to +150
5
1989 Mar 01
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
5.0
SYMBOL
PARMETER
SYMBOL
UNIT
MAX
MIN
4.5
V
Supply voltage
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
20
T
amb
Operating free-air temperature range
0
70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
TEST
LIMITS
UNIT
SYMBOL
PARAMETER
1
2
CONDITIONS
MIN TYP
MAX
±10%V
±5%V
V
V
= MIN, V = MAX,
2.5
V
V
CC
CC
IL
V
OH
High-level output voltage
= MIN, I = MAX
2.7
3.4
CC
IH
OH
V
V
V
V
V
= MIN, V = MAX,
±10%V
0.30
0.30
0.50
0.50
V
V
CC
IL
CC
V
V
Low-level output voltage
OL
= MIN, I = MAX
±5%V
IH
OL
CC
Input clamp voltage
= MIN, I = I
IK
–0.73 –1.2
V
IK
CC
CC
CC
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
100
20
µA
µA
mA
mA
I
I
IH
= MAX, V = 2.7V
I
An, Bn, Cn
S0, S1, S2
–2.4
–0.6
I
IL
Low-level input current
V
CC
= MAX, V = 0.5V
I
3
Short-circuit output current
I
I
V
V
= MAX
= MAX
–60
–150
mA
mA
OS
CC
Supply current (total)
59
89
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
6
1989 Mar 01
Philips Semiconductors
Product specification
Arithmetic Logic Unit
74F381
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
T
amb
= +25°C
= 0°C to +70°C
amb
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
V
CC
= +5.0V ± 10%
UNIT
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Cn to Fn
2.5
2.5
6.0
4.5
11.0
6.5
2.5
2.5
12.5
7.5
PLH
PHL
Waveform 1
Waveform 1
Waveform 1
Waveform 1
Waveform 1
Waveform 1
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
Any An or Bn to any Fn
3.5
3.0
7.0
6.0
13.0
9.0
3.5
3.0
16.0
10.0
PLH
PHL
t
t
Propagation delay
Sn to Fn
5.0
4.0
9.0
7.5
20.0
10.5
5.0
4.0
21.5
11.5
PLH
PHL
t
t
Propagation delay
An to Bn to G
3.5
3.0
6.5
6.0
9.0
8.5
3.5
3.0
10.0
9.0
PLH
PHL
t
t
Propagation delay
An or Bn to P
3.0
3.5
5.5
6.0
8.0
8.5
3.0
3.5
9.0
9.0
PLH
PHL
t
t
Propagation delay
Sn to G or P
5.0
5.5
7.5
8.5
11.0
12.5
5.0
5.0
12.5
14.0
PLH
PHL
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
V
V
V
M
IN
M
t
t
PLH
PHL
V
V
V
M
OUT
M
SF00926
Waveform 1. Propagation Delay for Non-Inverting
or Inverting paths
TEST CIRCUIT AND WAVEFORM
t
AMP (V)
V
w
CC
90%
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
family
V
rep. rate
t
t
t
THL
amplitude
3.0V
M
w
TLH
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns 2.5ns
74F
1.5V
1MHz
500ns
SF00006
7
1989 Mar 01
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