74F50728 [NXP]
Synchronizing cascaded dual positive edge-triggered D-type flip-flop; 同步级联的双正边沿触发的D型触发器
| 型号： | 74F50728 |
| 厂家： | 
NXP |
| 描述： | Synchronizing cascaded dual positive edge-triggered D-type flip-flop |
| 文件： | 总12页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
Positive specification
IC15 Data Handbook
1990 Sep 14
Philips
Semiconductors
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output. Data entering the 74F50728 requires two
clock cycles to arrive at the outputs.
FEATURES
• Metastable immune characteristics
• Output skew less than 1.5ns
• See 74F5074 for synchronizing dual D-type flip-flop
The 74F50728 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
• See 74F50109 for synchronizing dual J–K positive edge-triggered
flip-flop
• See 74F50729 for synchronizing dual dual D-type flip-flop with
metastable state. Typical metastability parameters for the 74F50728
edge-triggered set and reset
6
are: τ 135ps and T
9.8 X 10 sec where τ represents a
0
• Industrial temperature range available (–40°C to +85°C)
function of the rate at which a latch in a metastable state resolves
that condition and T represents a function of the measurement of
o
the propensity of a latch to enter a metastable state.
DESCRIPTION
The 74F50728 is a cascaded dual positive edge–triggered D–type
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
TYPICAL SUPPLY
CURRENT (TOTAL)
TYPE
TYPICAL f
max
74F50728
145 MHz
23mA
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. They set and reset
both flip–flops of a cascaded pair simultaneously. Data must be
stable just one setup time prior to the low–to–high transition of the
clock for guaranteed propagation delays.
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%,
INDUSTRIAL RANGE
DESCRIPTION
PKG DWG #
V
V
CC
= 5V ±10%,
CC
T
amb
= 0°C to +70°C
T
amb
= –40°C to +85°C
I74F50728N
14–pin plastic DIP
14–pin plastic SO
N74F50728N
N74F50728D
SOT27-1
I74F50728D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
PINS
DESCRIPTION
D0, D1
CP0, CP1
Data inputs
1.0/0.417
1.0/1.0
1.0/1.0
1.0/1.0
50/33
20µA/250µA
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
Clock inputs (active rising edge)
Set inputs (active low)
Reset inputs (active low)
Data outputs
SD0, SD1
RD0, RD1
Q0, Q1, Q0, Q1
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2
September 14, 1990
853-1389 00421
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
PIN CONFIGURATION
LOGIC DIAGRAM
4, 10
SDn
V
1
2
3
4
5
14
13
CC
RD0
D0
2, 12
Dn
5, 9
D
Q
Q
D
Q
Qn
RD1
12 D1
6, 8
CP0
Q
CP
Q n
CP
11
10
9
CP1
SD1
Q1
SD0
Q0
3, 11
CPn
Q0
6
7
1, 13
RDn
8
GND
Q1
V
= Pin 14
cc
GND = Pin 7
SF00608
SF00605
NOTE: Data entering the flip–flop requires two clock cycles to
arrive at the output.
LOGIC SYMBOL
SYNCHRONIZING SOLUTIONS
2
12
Synchronizing incoming signals to a system clock has proven to be
costly, either in terms of time delays or hardware. The reason for this
is that in order to synchronize the signals a flip–flop must be used to
”capture” the incoming signal. While this is perhaps the only way to
synchronize a signal, to this point, there have been problems with
this method. Whenever the flop’s setup or hold times are violated
the flop can enter a metastable state causing the outputs in turn to
glitch, oscillate, enter an intermediate state or change state in some
abnormal fashion. Any of these conditions could be responsible for
causing a system crash. To minimize this risk, flip–flops are often
cascaded so that the input signal is captured on the first clock pulse
and released on the second clock pulse (see Fig.1). This gives the
first flop about one clock period minus the flop delay and minus the
second flop’s clock–to–Q setup time to resolve any metastable
condition. This method greatly reduces the probability of the outputs
of the synchronizing device displaying an abnormal state but the
trade-off is that one clock cycle is lost to synchronize the incoming
data and two separate flip–flops are required to produce the
cascaded flop circuit. In order to assist the designer of synchronizing
circuits Philips Semiconductors is offering the 74F50728.
D0 D1
3
4
CP0
SD0
RD0
1
11
CP1
10
13
SD1
RD1
Q0 Q0 Q1 Q1
5
6
9
8
V
= Pin 14
CC
GND = Pin 7
SF00606
IEC/IEEE SYMBOL
&
4
3
2
S
3
C1
D
Q
Q
D
Q
Q
Q OUTPUT
Q OUTPUT
DATA
1D
R
6
CLOCK
1
CP
CP
10
11
12
S
9
8
SF00609
C2
Figure 1.
2D
R
The 50728 consists of two pair of cascaded D–type flip–flops with
metastable immune features and is pin compatible with the 74F74.
Because the flops are cascaded on a single part the metastability
13
SF00607
3
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
characteristics are greatly improved over using two separate flops
that are cascaded. The pin compatibility with the 74F74 allows for
plug–in retrofitting of previously designed systems.
Suppose a designer wants to use the flop for synchronizing
asynchronous data that is arriving at 10MHz (as measured by a
frequency counter), and is using a clock frequency of 50MHz. He
simply plugs his number into the equation below:
Because the probability of failure of the 74F50728 is so remote, the
metastability characteristics of the part were empirically determined
based on the characteristics of its sister part, the 74F5074. The
table below shows the 74F5074 metastability characteristics.
(t’/t)
MTBF = e /T f f
o C I
In this formula, f is the frequency of the clock, f is the average
C
I
input event frequency, and t’ is the period of the clock input (20
Having determined the T and τ of the flop, calculating the mean
nanoseconds). In this situation the f will be twice the data
0
I
time between failures (MTBF) for the 74F50728 is simple. It is,
however, somewhat different than calculating MTBF for a typical part
because data requires two clock pulses to transit from the input to
the output. Also, in this case a failure is considered of the output
beyond the normal propagation delay.
frequency of 20 MHz because input events consist of both of low
and high data transitions. From Fig. 2 it is clear that the MTBF is
41
greater than 10 seconds. Using the above formula the actual
42
34
MTBF is 2.23 X 10 seconds or about 7 X 10 years.
TYPICAL VALUES FOR τ AND T AT VARIOUS V S AND TEMPERATURES
0
CC
T
amb
= 0°C
T
amb
= 25°C
T = 70°C
amb
τ
T
0
τ
T
0
τ
T
0
9
6
5
V
CC
V
CC
V
CC
= 5.5V
= 5.0V
= 4.5V
125ps
115ps
115ps
1.0 X 10 sec
138ps
135ps
132ps
5.4 X 10 sec
160ps
167ps
175ps
1.7 X 10 sec
10
6
4
1.3 X 10 sec
9.8 X 10 sec
3.9 X 10 sec
13
8
4
3.4 X 10 sec
5.1 X 10 sec
7.3 X 10 sec
MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY
70
10
Clock = 40MHz
60
10
50
10
Mean time
between failures
(seconds)
Clock = 50MHz
Clock = 650MHz
40
30
20
10
00
10
10
10
Clock = 70MHz
Clock = 80MHz
Clock = 100MHz
1 billion years
10
10
1K
100K
10M
Data frequency (Hz)
8
= 25°C, τ =135ps, To = 9.8 X 10 sec
NOTE: V = 5V, T
CC
amb
SF00610
Figure 2.
4
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
FUNCTION TABLE
INTERNAL
OUTPUTS
REGISTER
OPERATING MODE
INPUTS
RDn
SDn
L
CPn
X
Dn
X
X
X
h
Q
H
L
Qn
H
Qn
L
H
L
Asynchronous set
H
X
L
H
Asynchronous reset
Undetermined*
Load ”1”
L
L
X
X
H
H
H
H
H
H
↑
h
H
L
H
↑
l
l
L
H
Load ”0”
H
L
X
NC
NC
NC
Hold
NOTES:
NC= No change from the previous setup
H = High voltage level
X
*
=
=
Don’t care
h
=
High voltage level one setup time prior to low–to–high
clock transition
This setup is unstable and will change when either set of
reset return to the high–level
L
l
=
=
Low voltage level
Low voltage level one setup time prior to low–to–high
clock transition
↑
=
Low–to–high clock transition.
** = Data entering the flip–flop requires two clock cycles to
arrive at the output (see logic diagram)
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
–0.5 to V
V
OUT
CC
40
mA
°C
°C
°C
OUT
T
amb
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
T
stg
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
MIN
4.5
NOM
MAX
UNIT
V
V
Supply voltage
5.0
5.5
CC
IH
IL
V
V
High–level input voltage
Low–level input voltage
Input clamp current
2.4
V
0.8
–18
–3
V
I
I
I
mA
mA
mA
Ik
High–level output current
Low–level output current
OH
OL
20
T
amb
Operating free air temperature range
Commercial range
Industrial range
0
+70
°C
°C
–40
+85
5
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN TYP
MAX
V
High-level output voltage
V
V
V
= MIN, V = MIN
I
OH
= MAX
2.5
V
V
±10%V
±5%V
OH
CC
IH
CC
= MAX,
2.7
3.4
IL
CC
= MIN, V
=
IL
CC
V
OL
Low-level output voltage
I
OL
= MAX
0.30
0.30
0.50
0.50
V
V
±10%V
CC
MAX,
V
IH
= MIN
±5%V
CC
V
Input clamp voltage
V
V
= MIN, I = I
IK
-0.73 -1.2
100
V
IK
CC
I
I
I
I
Input current at maximum input voltage
= MAX, V = 7.0V
µA
I
CC
I
High–level input current
V
CC
V
CC
= MAX, V = 2.7V
20
µA
µA
IH
IL
I
Low–level input current
Dn
= MAX, V = 0.5V
-250
–20
-150
I
CPn, SDn, RDn
µA
3
I
I
Short–circuit output current
V
V
= MAX, V = 2.25V
-60
mA
OS
CC
O
4
Supply current (total)
= MAX
23
34
mA
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Measure I with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
CC
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= +25°C
T
= 0°C to
+70°C
= +5.0V ± 10%
T
amb
= –40°C to +85°C
V = +5.0V ± 10%
CC
amb
amb
V
SYMBOL
PARAMETER
TEST
V
= +5.0V
UNIT
CC
CC
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP MAX
MIN
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
100
145
85
70
ns
ns
max
t
t
Propagation delay
CPn to Qn or Qn
2.0
2.0
3.8
3.8
6.0
6.0
1.5
2.0
6.5
6.5
1.5
2.0
7.5
7.0
PLH
PHL
t
t
Propagation delay
SDn RDn to Qn or Qn
3.5
3.5
5.0
5.0
8.0
8.0
3.0
3.0
9.0
8.5
3.0
3.0
10.5
10.0
PLH
PHL
Waveform 2
Waveform 4
ns
ns
1, 2
t
Output skew
1.5
1.5
1.5
sk(o)
NOTES TO AC ELECTRICAL CHARACTERISTICS
1. | t actual –t actual | for any one output compare to any other output where N and M are either LH or HL.
PLH
PHL
2. Skew lines are valid only under same conditions (temperature, V , loading, etc.,).
CC
6
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to
T
amb
= –40°C to +85°C
+70°C
V
CC
= +5.0V ± 10%
V
CC
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP MAX
MIN
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
Dn to CPn
1.5
1.5
2.0
2.0
2.0
2.0
su
su
Waveform 1
Waveform 1
ns
ns
t (H)
Hold time, high or low
Dn to CPn
0.0
0.0
1.5
1.5
1.5
1.5
h
t (L)
h
t
t
(H)
(L)
CPn pulse width,
high or low
3.0
4.0
3.5
5.0
4.0
5.5
w
w
Waveform 2
Waveform 2
Waveform 3
ns
ns
ns
t
t
(L)
SDn, RDn pulse width, low
4.5
3.5
4.0
3.5
4.5
3.5
w
Recovery time
SDn, RDn to CPn
rec
AC WAVEFORMS
t
(L)
Jn, Kn
w
V
t
V
V
V
M
M
M
M
SDn
RDn
V
V
M
M
t
(H)
t
(H)
(L)
t (L)
h
su
h
su
1/f
M
max
t
(L)
w
V
V
M
M
CPn
Qn
V
V
M
V
M
t
(H)
w
t
t
PHL
PLH
t
(L)
t
PHL
w
t
PLH
Qn
Qn
V
V
V
M
M
M
V
V
M
M
M
t
t
PLH
PHL
t
t
PHL
PLH
V
M
V
M
V
Qn
SF00050
SF00139
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Waveform 1. Propagation delay for data to output, data setup
time and hold times, and clock width, and
maximum clock frequency
V
Qn, Qn
M
t
sk(o)
SDn or RDn
V
M
t
Qn, Qn
rec
V
M
V
CPn
M
SF00590
Waveform 4. Output skew
SF00603
Waveform 3. Recovery time for set or reset to output
NOTES:
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
7
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
74F50728
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
=
=
=
Load resistor;
L
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
family
74F
C
L
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
R
T
Termination resistance should be equal to Z
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
pulse generators.
SF00006
8
September 14, 1990
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered
D-type flip-flop
74F50728
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
9
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered
D-type flip-flop
74F50728
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
10
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered
D-type flip-flop
74F50728
NOTES
11
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered
D-type flip-flop
74F50728
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05215
Document order number:
Philips
Semiconductors
相关型号：
74F50729
Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
NXP
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