74F573 [NXP]
Octal transparent latch 3-State; 八路透明锁存器三态
| 型号： | 74F573 |
| 厂家： | 
NXP |
| 描述： | Octal transparent latch 3-State |
| 文件： | 总14页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F573
Octal transparent latch (3-State)
74F574
Octal transparent latch (3-State)
Product specification
IC15 Data Handbook
1989 Oct 16
Philips
Semiconductors
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
FEATURES
• 74F573 is broadside pinout version of 74F373
• 74F574 is broadside pinout version of 74F374
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
• Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
• Useful as an Input or Output port for Microprocessors
• 3-State Outputs for Bus interfacing
• Common Output Enable
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
• 74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
• 3-State Outputs glitch free during power-up and power-down
• These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTION
TYPICAL SUPPLY
TYPICAL
PROPAGATION DELAY
The 74F573 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
CURRENT
(TOTAL)
TYPE
74F573
5.0ns
35mA
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
TYPICAL SUPPLY
CURRENT
TYPE
TYPICAL f
MAX
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
(TOTAL)
74F574
180MHz
50mA
ORDERING INFORMATION
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
COMMERCIAL RANGE
= 5V ±10%,
V
DESCRIPTION
PKG DWG #
CC
T
amb
= 0°C to +70°C
20-Pin Plastic DIP
20-Pin Plastic SOL
20-Pin Plastic SSOP
N74F573N, N74F574N SOT146-1
N74F573D, N74F574D SOT163-1
N74F573DB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
D0 - D7
Data inputs
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
E (74F573)
OE
Latch Enable input (active falling edge)
Output Enable input (active Low)
Clock Pulse input (active rising edge)
3-State outputs
CP (74F574)
Q0 - Q7
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
2
1989 Oct 16
853-0083 97897
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
PIN CONFIGURATION – 74F573
PIN CONFIGURATION – 74F574
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20
19
V
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20
V
CC
CC
Q0
19 Q0
18 Q1
17 Q2
18 Q1
17
16
15
14
13
12
11
Q2
Q3
Q4
Q5
Q6
Q7
E
16
15
14
13
12
11
Q3
Q4
Q5
Q6
Q7
CP
GND 10
GND 10
SF01073
SF01074
LOGIC SYMBOL – 74F573
LOGIC SYMBOL – 74F574
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
2
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
11
1
E
11
1
CP
OE
OE
Q0
19
Q1
18
Q2
17
Q3
16
Q4
15
Q5
14
Q6
13
Q7
Q0
19
Q1
18
Q2
17
Q3
16
Q4
15
Q5
14
Q6
13
Q7
12
12
V
=Pin 20
V
=Pin 20
CC
CC
GND=Pin 10
GND=Pin 10
SF01075
SF01076
LOGIC SYMBOL (IEEE/IEC) – 74F573
LOGIC SYMBOL (IEEE/IEC) – 74F574
1
1
EN1
EN1
11
11
EN2
C2
2
19
18
17
16
2
19
18
17
16
2D
1
2D
1
3
3
4
5
4
5
15
14
6
7
15
14
6
7
13
12
8
9
13
12
8
9
SF01077
SF01078
3
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
LOGIC DIAGRAM – 74F573
D0
D1
D2
D3
D4
D5
D6
D7
9
2
3
4
5
6
7
8
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
Q
Q
Q
Q
Q
Q
Q
E
Q
11
1
E
OE
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
V
=Pin 20
CC
GND=Pin 10
SF01079
FUNCTION TABLE – 74F573
INPUTS
OUTPUTS
Q0 – Q7
INTERNAL
REGISTER
OPERATING MODES
OE
E
Dn
L
L
H
H
L
L
L
Load and read register
H
H
H
L
L
↓
↓
l
L
L
Latch and read register
Hold
h
H
H
L
L
X
NC
NC
H
H
L
X
NC
Dn
Z
Z
Disable outputs
H
Dn
H = High voltage level
h
L
l
= High voltage level one setup time prior to the High-to-Low E transition
= Low voltage level
= Low voltage level one setup time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓
= High-to-Low E transition
LOGIC DIAGRAM – 74F574
D0
D1
D2
D3
D4
6
D5
D6
8
D7
2
3
4
5
7
9
D
D
D
D
D
D
D
D
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
11
1
CP
OE
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
V
=Pin 20
CC
Q7
GND=Pin 10
SF01080
4
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
FUNCTION TABLE – 74F574
INPUTS
OUTPUTS
Q0 – Q7
INTERNAL
REGISTER
OPERATING MODES
OE
CP
Dn
L
L
l
L
L
↑
↑
Load and read register
h
H
H
L
↑
↑
X
NC
Dn
NC
Z
Hold
H
Dn
Disable outputs
H = High voltage level
h
L
l
= High voltage level one setup time prior to the Low-to-High clock transition
= Low voltage level
= Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑
= Low-to-High clock transition
↑
= Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–0.5 to +7.0
–30 to +5.0
V
V
CC
IN
I
IN
mA
V
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
–0.5 to +V
48
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
SYMBOL
PARAMETER
UNIT
MIN
4.5
MAX
V
CC
V
IH
V
IL
Supply voltage
5.0
5.5
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–3
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature range
OH
OL
24
T
amb
0
70
5
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
UNIT
NO TAG
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
NO TAG
±10%V
2.4
2.7
V
V
V
V
V
CC
V
V
= MIN, V = MAX,
IL
CC
V
High-level output voltage
OH
V
IH
= MIN, I = MAX
OH
±5%V
3.4
0.35
0.35
–0.73
CC
±10%V
0.50
0.50
–1.2
CC
CC
= MIN, V = MAX,
CC
IH
IL
V
V
Low-level output voltage
Input clamp voltage
OL
V
= MIN, I = MAX
OL
±5%V
V
CC
= MIN, I = I
I IK
IK
Input current at
maximum input voltage
I
I
V
CC
= MAX, V = 7.0V
100
µA
I
I
I
High-level input current
Low-level input current
V
V
= MAX, V = 2.7V
20
µA
IH
CC
I
= MAX, V = 0.5V
–0.6
mA
IL
CC
I
Off-state output current,
High-level voltage applied
I
V
= MAX, V = 2.7V
50
µA
µA
OZH
CC
CC
O
Off-state output current,
Low-level voltage applied
I
I
V
= MAX, V = 0.5V
–50
OZL
O
NO TAG
Short-circuit output current
V
= MAX
= MAX
–60
–150
40
mA
mA
mA
mA
mA
mA
mA
OS
CC
I
I
I
I
I
I
30
35
40
45
50
55
CCH
CCL
CCZ
CCH
CCL
CCZ
74F573
V
CC
50
Supply
current
(total)
60
I
CC
65
74F574
V
CC
= MAX
70
85
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
6
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
AC ELECTRICAL CHARACTERISTICS
LIMITS
TEST
CONDITIONS
T
V
= +25°C
T
= 0°C to +70°C
amb
amb
V
SYMBOL
PARAMETER
= +5V
= +5V ± 10%
UNIT
CC
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dn to Qn
Waveform
NO TAG
3.0
1.0
5.5
3.5
8.0
6.0
2.5
1.0
9.0
7.0
PLH
PHL
ns
ns
t
t
Propagation delay
E to Qn
Waveform
NO TAG
4.5
3.0
8.5
5.0
11.5
7.0
4.0
2.5
12.5
8.0
PLH
PHL
Waveform
NO TAG
Waveform
NO TAG
t
t
Output Enable time
to High or Low level
2.5
2.5
5.5
5.5
9.5
8.0
2.0
2.0
10.5
8.5
PZH
PZL
74F573
ns
ns
Waveform
NO TAG
Waveform
NO TAG
t
t
Output Disable time
from High or Low level
1.0
1.0
3.0
2.5
6.0
5.5
1.0
1.0
6.5
5.5
PHZ
PLZ
Waveform
NO TAG
f
Maximum Clock frequency
160
180
150
MHz
ns
MAX
t
t
Propagation delay
CP to Qn
Waveform
NO TAG
3.5
3.5
5.0
5.0
7.5
7.5
3.0
3.0
8.0
8.0
PLH
PHL
Waveform
NO TAG
Waveform
NO TAG
t
t
Output Enable time
to High or Low level
2.5
3.0
4.5
5.0
7.5
8.0
2.0
3.0
7.5
8.5
PZH
PZL
74F574
ns
ns
Waveform
NO TAG
Waveform
NO TAG
t
t
Output Disable time
from High or Low level
1.0
1.0
3.0
2.5
5.5
5.5
1.0
1.0
6.0
6.0
PHZ
PLZ
AC SETUP REQUIREMENTS
LIMITS
T
V
= +25°C
T
V
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
amb
TEST
CONDITIONS
SYMBOL
PARAMETER
= +5V
UNIT
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Setup time,
Dn to E
0.0
1.5
0.0
2.0
s
Waveform 4
Waveform 4
ns
ns
ns
ns
ns
ns
t (H)
Hold time,
Dn to E
2.5
4.0
2.5
4.0
h
74F573
74F574
t (L)
h
E pulse width,
High
t (H)
w
Waveform NO TAG
Waveform NO TAG
Waveform NO TAG
Waveform NO TAG
3.0
3.5
t (H)
Setup time,
Dn to CP
2.5
2.5
3.0
3.0
s
t (L)
s
t (H)
Hold time,
Dn to CP
0
0
0
0
h
t (L)
h
t (H)
CP Pulse width,
High or Low
3.0
3.5
3.0
4.0
w
t (L)
w
7
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
AC WAVEFORMS
For all waveforms, V = 1.5V
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
Dn
Qn
V
V
M
M
E, CP
V
V
V
M
M
M
t
t
(H)
(L)
W
W
t
t
PHL
PLH
t
t
PLH
PHL
V
V
M
M
V
V
M
Qn
M
SF01081
SF01082
Waveform 1. Propagation Delay, Clock and Enable Inputs
to Output, Enable, Clock Pulse Widths,
Waveform 2. Propagation Delay for Data to Outputs
and Maximum Clock Frequency
Dn
Dn
CP
V
V
V
V
M
V
V
t
V
V
M
M
M
M
M
M
M
t (H)
(H)
t (L)
t
(L)
t (H)
t (L)
s
s
h
s
h
t
(H)
t (L)
h
s
h
E
V
V
V
V
M
M
M
M
SF00992
SF00191
Waveform 4. Data Setup and Hold Times
Waveform 3. Data Setup and Hold Times
V
t
V
M
M
OE
Qn
V
V
M
M
OE
Qn
t
V
-0.3V
PZL
PLZ
OH
t
t
PHZ
PZH
V
M
V
M
0V
V
+0.3V
OL
SF00343
SF00344
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
8
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
TEST CIRCUIT AND WAVEFORM
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
R
M
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00777
9
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
10
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
11
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
12
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
NOTES
13
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
Production
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05141
Document order number:
Philips
Semiconductors
相关型号：
74F573DCQR
Bus Driver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, CDIP20, CERAMIC, DIP-20
FAIRCHILD
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