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74F674 [NXP]

16-bit serial/parallel-in, serial-out shift register 3-State; 16位串行/并行于，串行输出移位寄存器三态
74F674
型号： 74F674
厂家： NXP    NXP
描述：

16-bit serial/parallel-in, serial-out shift register 3-State
16位串行/并行于，串行输出移位寄存器三态

移位寄存器
文件： 总5页 (文件大小：51K)
中文：  中文翻译
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Philips Semiconductors  
Product specification  
16-bit serial/parallel-in, serial-out shift register (3-State)  
74F674  
FEATURES  
PIN CONFIGURATION  
• 16-bit serial I/O shift register  
• 16-bit parallel-in/serial-out converter  
• Recirculating serial shifting  
CS  
CP  
V
1
2
3
4
5
24  
CC  
23 D15  
22  
R/W  
NC  
D14  
• Common serial data I/O pin (3-State)  
21 D13  
DESCRIPTION  
M
20  
D12  
The 74F674 is a 16-bit shift register with serial and parallel load  
capability and serial output. A single pin serves alternately as an  
input for serial entry or as a 3-State serial output. In the serial out  
mode the data recirculates in the register. Chip Select, Read/Write  
and Mode inputs provide control flexibility. The 74F674 operates in  
one of four modes, as indicated in the Function table.  
SI/O  
6
7
8
9
19 D11  
18  
17  
16  
15  
14  
13  
D0  
D1  
D10  
D9  
D8  
D7  
D6  
D5  
D2  
D3 10  
D4  
Hold: A High signal on the Chip Select (CS) input prevents clocking  
and forces the Serial Input/Output (SI/O) 3-State buffer into the high  
impedance state.  
11  
GND 12  
Serial load: Data present on the SI/O pin shifts into the register on  
the falling edge of CP. Data enters the Q0 position and shifts toward  
Q15 on successive clocks.  
SF01188  
Serial output: The SI/O 3-State buffer is active and the register  
contents are shifted out from Q15 and simultaneously shifted back  
into Q0.  
TYPICAL SUPPLY  
CURRENT  
TYPE  
TYPICAL f  
MAX  
(TOTAL)  
Parallel load: Data present on D0–D15 is entered into the register  
on the falling edge of CP. The SI/O 3-State buffer is active and  
represents the Q15 output. To prevent false clocking, CP must be  
Low during a Low-to-High transition of CS.  
74F674  
95MHz  
55mA  
ORDERING INFORMATION  
DESCRIPTION  
COMMERCIAL RANGE  
= 5V ±10%, T = 0°C to +70°C  
V
CC  
amb  
24-Pin Plastic Slim DIP  
(300mil)  
N74F674N  
24-Pin Plastic SOL  
N74F674D  
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE  
74F(U.L.)  
HIGH/LOW  
LOAD VALUE  
PINS  
D0–D15  
DESCRIPTION  
HIGH/LOW  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
70mA/0.6mA  
3.0mA/24mA  
Parallel data inputs  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
3.5/1.0  
150/40  
CS  
CP  
M
Chip Select input (active Low)  
Clock Pulse input (active falling edge)  
Mode select input  
R/W  
Read/Write input  
Serial data input or  
SI/O  
Serial 3-state output  
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.  
1
1989 Feb 05  
853–1248 92263  
Philips Semiconductors  
Product specification  
16-bit serial/parallel-in, serial-out shift register (3-State)  
74F674  
LOGIC SYMBOL  
LOGIC SYMBOL (IEEE/IEC)  
7
8
9
10 11 13 14 15 16 17 18  
19 20 21 22 23  
SRG16  
5
0
1
0
3
M
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15  
CS  
3
&
&
EN  
1
2
3
1
2
CP  
C4(0/1/2)  
R/W  
5
M
SO  
7
8
3, 4D  
3, 4D  
3, 4D  
V
= Pin 24  
9
CC  
6
GND = Pin 12  
SF01189  
10  
11  
13  
14  
15  
16  
17  
18  
FUNCTION TABLE  
CONTROL INPUTS  
SI/O  
STATUS  
OPERATING  
MODE  
CS  
H
R/W  
X
M
X
X
CP  
X
High Z  
Data in  
Hold  
L
L
↓
Serial load  
19  
20  
21  
22  
Serial output with  
recirculation  
L
L
H
H
L
↓
↓
Data out  
Active  
Parallel load;  
no shifting  
H
6
23  
3, 4D  
H = High voltage level  
= Low voltage level  
X = Don’t care  
= High-to-Low transition of designed input  
L
SF01190  
↓
LOGIC DIAGRAM  
D0–D15 (7–11, 13–23)  
5
1
M
D0–D15  
PE  
CS  
Q0  
CP  
6
Q15  
SI/O  
2
3
CP  
R/W  
V
=
=
Pin 24  
Pin 12  
CC  
GND  
SF01191  
2
1989 Feb 05  
Philips Semiconductors  
Product specification  
16-bit serial/parallel-in, serial-out shift register (3-State)  
74F674  
ABSOLUTE MAXIMUM RATINGS  
(Operation beyond the limits set forth in this table may impair the useful life of the device.  
Unless otherwise noted these limits are over the operating free-air temperature range.)  
SYMBOL  
PARAMETER  
RATING  
UNIT  
V
V
V
Supply voltage  
Input voltage  
Input current  
–0.5 to +7.0  
–0.5 to +7.0  
–30 to +5.0  
CC  
V
IN  
I
IN  
mA  
V
Voltage applied to output in High output state  
Current applied to output in Low output state  
Operating free-air temperature range  
Storage temperature  
–0.5 to +V  
48  
V
OUT  
OUT  
CC  
I
mA  
°C  
°C  
T
amb  
0 to +70  
T
stg  
–65 to +150  
RECOMMENDED OPERATING CONDITIONS  
LIMITS  
SYMBOL  
PARAMETER  
UNIT  
MIN  
4.5  
NOM  
MAX  
V
CC  
V
IH  
V
IL  
Supply voltage  
5.0  
5.5  
V
V
High-level input voltage  
Low-level input voltage  
Input clamp current  
2.0  
0.8  
–18  
–3  
V
I
I
I
mA  
mA  
mA  
°C  
IK  
High-level output current  
Low-level output current  
Operating free-air temperature range  
OH  
OL  
24  
T
amb  
0
70  
DC ELECTRICAL CHARACTERISTICS  
(Over recommended operating free-air temperature range unless otherwise noted.)  
LIMITS  
1
SYMBOL  
PARAMETER  
TEST CONDITIONS  
UNIT  
2
MIN  
TYP  
MAX  
±10%V  
2.4  
2.7  
V
V
CC  
V
V
= MIN, V = MAX,  
IL  
CC  
IH  
V
High-level output voltage  
OH  
= MIN, I = MAX  
OH  
±5%V  
3.3  
0.35  
0.35  
–0.73  
CC  
±10%V  
0.50  
0.50  
–1.2  
100  
100  
20  
V
CC  
CC  
V
CC  
= MIN, V = MAX,  
IL  
V
V
Low-level output voltage  
Input clamp voltage  
OL  
V
= MIN, I = MAX  
IH  
OL  
±5%V  
V
V
CC  
= MIN, I = I  
IK  
V
IK  
I
SI/O only  
others  
V
CC  
V
CC  
V
CC  
V
CC  
= MAX, V = 5.5V  
µA  
µA  
µA  
mA  
I
Input current at  
maximum input voltage  
I
I
= MAX, V = 7.0V  
I
I
I
High-level input current  
Low-level input current  
= MAX, V = 2.7V  
I
IH  
= MAX, V = 0.5V  
–0.6  
IL  
I
Off-state output current  
High-level voltage applied  
I
I
+I  
V
= MAX, V = 2.7V  
70  
µA  
µA  
OZH IH  
CC  
CC  
O
SI/O  
only  
Off-state output current  
Low-level voltage applied  
+I  
OZL IL  
V
= MAX, V = 0.5V  
–600  
O
3
I
I
Short-circuit output current  
Supply current (total)  
V
V
= MAX  
= MAX  
–60  
–150  
80  
mA  
mA  
OS  
CC  
55  
CC  
CC  
NOTES:  
1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type.  
2. All typical values are at V = 5V, T = 25°C.  
CC  
amb  
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold  
OS  
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting  
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any  
sequence of parameter tests, I should be performed last.  
OS  
3
1989 Feb 05  
Philips Semiconductors  
Product specification  
16-bit serial/parallel-in, serial-out shift register (3-State)  
74F674  
AC ELECTRICAL CHARACTERISTICS  
LIMITS  
T
V
= +25°C  
= +5.0V  
T
V
= 0°C to +70°C  
= +5.0V ± 10%  
amb  
amb  
TEST  
CONDITIONS  
SYMBOL  
PARAMETER  
UNIT  
CC  
CC  
C = 50pF, R = 500Ω  
C = 50pF, R = 500Ω  
L L  
L
L
MIN  
TYP  
MAX  
MIN  
MAX  
f
Maximum clock frequency  
Waveform 1  
Waveform 1  
80  
95  
70  
MHz  
MAX  
t
t
Propagation delay  
CP to SI/O  
7.0  
6.0  
9.5  
8.5  
12.5  
11.5  
6.5  
5.5  
14.0  
12.5  
ns  
ns  
PLH  
PHL  
t
t
Output Enable time  
CS to SI/O  
Waveform 3  
Waveform 4  
5.5  
7.0  
8.5  
9.5  
11.0  
12.5  
5.0  
6.5  
12.5  
14.0  
ns  
ns  
PZH  
PZL  
t
t
Output Disable time  
CS to SI/O  
Waveform 3  
Waveform 4  
3.0  
4.5  
6.0  
7.5  
8.5  
10.0  
3.0  
4.5  
10.0  
11.5  
ns  
ns  
PHZ  
PLZ  
t
t
Output Enable time  
R/W to SI/O  
Waveform 3  
Waveform 4  
6.0  
7.5  
8.5  
10.0  
11.5  
13.0  
5.5  
7.0  
13.0  
14.0  
ns  
ns  
PZH  
PZL  
t
t
Output Disable time  
R/W to SI/O  
Waveform 3  
Waveform 4  
5.0  
5.5  
7.5  
8.0  
10.5  
11.0  
4.5  
5.0  
12.0  
13.5  
ns  
ns  
PHZ  
PLZ  
AC SETUP REQUIREMENTS  
LIMITS  
T
V
= +25°C  
= +5.0V  
T
V
CC  
= 0°C to +70°C  
= +5.0V ± 10%  
amb  
amb  
SYMBOL  
PARAMETER  
TEST CONDITION  
UNIT  
CC  
C = 50pF, R = 500Ω  
C = 50pF, R = 500Ω  
L L  
L
L
MIN  
TYP  
MAX  
MIN  
MAX  
t (H)  
t (L)  
s
Setup time, High or Low  
SI/O to CP  
2.0  
2.0  
2.5  
2.5  
ns  
ns  
s
Waveform 2  
Waveform 2  
Waveform 2  
Waveform 2  
Waveform 2  
Waveform 2  
Waveform 2  
Waveform 2  
Waveform 1  
t (H)  
Hold time, High or Low  
SI/O to CP  
1.5  
1.5  
2.0  
2.0  
ns  
ns  
h
t (L)  
h
t (H)  
Setup time, High or Low  
Dn to CP  
1.5  
1.0  
2.0  
1.0  
ns  
ns  
s
t (L)  
s
t (H)  
Hold time, High or Low  
Dn to CP  
3.0  
4.0  
3.0  
4.0  
ns  
ns  
h
t (L)  
h
t (H)  
Setup time, High or Low  
M to CP  
2.0  
5.5  
2.5  
6.0  
ns  
ns  
s
t (L)  
s
t (H)  
Hold time, High or Low  
M to CP  
0.0  
0.0  
1.0  
1.0  
ns  
ns  
h
t (L)  
h
Setup time, Low  
CS to CP  
t (L)  
s
8.0  
0.0  
9.0  
0.0  
ns  
ns  
Hold time, High  
CS to CP  
t (H)  
h
t (H)  
CP Pulse width,  
High or Low  
3.5  
4.5  
4.0  
5.0  
ns  
ns  
w
t (L)  
w
4
1989 Feb 05  
Philips Semiconductors  
Product specification  
16-bit serial/parallel-in, serial-out shift register (3-State)  
74F674  
AC WAVEFORMS  
For all waveforms, V = 1.5V.  
M
The shaded areas indicate when the input is permitted to change for predictable output performance.  
1/f  
MAX  
Dn, CS,  
M, R/W,  
SI/O  
V
V
V
V
t
M
M
M
M
CP  
V
t
V
V
t
M
t
M
t
M
t (H)  
t
(H)  
t (L)  
(L)  
s
h
s
h
(L)  
(H)  
W
W
PLH  
PHL  
V
V
M
CP  
M
SI/O  
V
V
M
M
SF01192  
SF01193  
Waveform 1. Propagation Delay, Clock Input to Output,  
Clock Pulse Width, and Maximum Clock Frequency  
Waveform 2. Setup and Hold Times  
CS, R/W  
SI/O  
V
V
CS, R/W  
SI/O  
V
V
M
M
t
M
t
M
t
V
-0.3V  
0V  
OH  
t
PZL  
PLZ  
PZH  
PHZ  
V
V
M
M
V
+0.3V  
OL  
SF01195  
SF01194  
Waveform 3. 3-State Output Enable Time to High Level  
and Output Disable Time from High Level  
Waveform 4. 3-State Output Enable Time to Low Level  
and Output Disable Time from Low Level  
TEST CIRCUIT AND WAVEFORM  
V
CC  
t
w
AMP (V)  
0V  
7.0V  
90%  
90%  
NEGATIVE  
PULSE  
V
V
M
R
L
M
V
V
OUT  
IN  
10%  
10%  
PULSE  
GENERATOR  
D.U.T.  
t
t )  
t
t )  
THL ( f  
TLH ( r  
R
C
R
L
T
L
t
t )  
t
t )  
TLH ( r  
THL ( f  
AMP (V)  
0V  
90%  
M
90%  
POSITIVE  
PULSE  
V
V
M
Test Circuit for 3-State Outputs  
10%  
10%  
t
w
SWITCH POSITION  
TEST  
SWITCH  
closed  
closed  
open  
Input Pulse Definition  
t
t
PLZ  
PZL  
All other  
DEFINITIONS:  
R
L
C
L
R
T
=
=
=
Load resistor;  
INPUT PULSE REQUIREMENTS  
see AC electrical characteristics for value.  
Load capacitance includes jig and probe capacitance;  
see AC electrical characteristics for value.  
Termination resistance should be equal to Z  
pulse generators.  
family  
V
M
rep. rate  
t
t
t
THL  
amplitude  
w
TLH  
of  
OUT  
2.5ns  
2.5ns  
74F  
3.0V  
1.5V  
1MHz  
500ns  
SF00777  
5
1989 Feb 05  

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