74F824 [NXP]
Bus interface registers; 总线接口寄存器
| 型号： | 74F824 |
| 厂家： | 
NXP |
| 描述： | Bus interface registers |
| 文件： | 总18页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F821/822/823/824/825/826
Bus interface registers
Product specification
IC15 Data Handbook
1996 Jan 05
Philips
Semiconductors
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
74F821 10-bit bus interface register, non-inverting (3-State)
74F822 10-bit bus interface register, inverting (3-State)
74F823 9-bit bus interface register, non-inverting (3-State)
74F824 9-bit bus interface register, inverting (3-State)
74F825 8-bit bus interface register, non-inverting (3-State)
74F826 8-bit bus interface register, inverting (3-State)
FEATURES
DESCRIPTION
The 74F821 series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of busses
carrying parity.
• High speed parallel registers with positive edge-triggered D-type
flip-flops
• High performance bus interface buffering for wide data/address
paths or busses carrying parity
The 74F821/74F822 are buffered 10-bit wide versions of the popular
74F374/74F534 functions.
• High impedance PNP base inputs for reduced loading (20µA in
high and low states)
The 74F822 is the inverted output version of 74F821.
• I is 20µA vs 1000µA for AM29821 series
IL
The 74F823 and 74F824 are 9-bit wide buffered registers with clock
enable (CE) and master reset (MR) which are ideal for parity bus
interfacing in high microprogrammed systems.
• Buffered control inputs to reduce AC effects
• Ideal where high speed, light loading, or increased fan-in as
The 74F824 is the inverted version of 74F823.
required with MOS microprocessor
The 74F825 and 74F826 are 8-bit buffered registers with all the
74F823/74F824 controls plus output enable (OE0, OE1, OE2) to
allow multiuser control of the interface, e.g., CS, DMA, and RD/WR.
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• Slim Dip 300 mil package
They are ideal for uses as an output port requiring high I /I
.
OL OH
The 74F826 is the inverted version of 74F825.
• Broadside pinout compatible with AMD AM 29821-29826 series
• Outputs sink 64mA and source 24mA
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPICAL
TYPE
f
max
• Industrial temperature range available (–40°C to +85°C) for
74F823
74F821, 74F822
74F823, 74F824
74F825, 74F826
180MHz
180MHz
180MHz
75mA
70mA
65mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%,
INDUSTRIAL RANGE
DESCRIPTION
PKG. DWG. #
V
V
CC
= 5V ±10%,
= –40°C to +85°C
CC
T
amb
= 0°C to +70°C
T
amb
N74F821N, N74F822N, N74F823N,
N74F824N, N74F825N, N74F826N
24-pin plastic slim DIP (300mil)
24-pin plastic SOL
I74F823N
SOT222-1
SOT137-1
N74F821D, N74F822D, N74F823D,
N74F824D, N74F825D, N74F826D
I74F823D
2
1996 Jan 05
853-1304 16195
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
Dn
CP
Data inputs
Clock input
1.0/1.0
1.0/1.0
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
24mA/64mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
20µA/1.8mA
24mA/64mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
20µA/1.8mA
24mA/64mA
74F821
74F822
OE
Output enable input (active low)
Data outputs
1.0/3.0
Qn, Qn
Dn
1200/106.7
1.0/1.0
Data inputs
CP
Clock input
1.0/1.0
74F823
74F824
CE
Clock enable input (active low)
Master reset input (active low)
Output enable input (active low)
Data outputs
1.0/3.0
MR
1.0/3.0
OE
1.0/3.0
Qn, Qn
Dn
1200/106.7
1.0/1.0
Data inputs
CP
Clock input
1.0/1.0
74F825
74F826
CE
Clock enable input (active low)
Master reset input (active low)
Output enable input (active low)
Data outputs
1.0/3.0
MR
1.0/3.0
OE
1.0/3.0
Qn, Qn
1200/106.7
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION – 74F821
LOGIC SYMBOL – 74F821
2
3
4
5
6
7
8
9
10 11
OE
D0
D1
D2
1
2
3
4
5
24
23
22
21
20
V
CC
Q0
Q1
Q2
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
CP
OE
13
1
D3
D4
D5
Q3
Q4
6
7
19
18 Q5
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
8
17
16
15
D6
D7
D8
Q6
Q7
Q8
9
10
V
= Pin 24
CC
GND = Pin 12
SF00483
D9 11
14 Q9
13
GND 12
CP
SF00482
3
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
IEC/IEEE SYMBOL – 74F821
IEC/IEEE SYMBOL – 74F822
1
1
EN1
G2
EN1
13
13
G2
2
23
22
21
20
19
18
17
16
15
14
2D
1
2
23
22
21
20
19
18
17
16
15
14
2D
1
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
10
11
SF00484
SF00487
PIN CONFIGURATION – 74F823
PIN CONFIGURATION – 74F822
OE
D0
D1
D2
1
2
3
4
5
24
23
22
OE
D0
D1
D2
1
2
3
4
5
24
23
22
V
V
CC
CC
Q0
Q1
Q0
Q1
21 Q2
21 Q2
20
19
20
19
D3
D4
D5
Q3
Q4
D3
D4
D5
Q3
Q4
6
7
6
7
18 Q5
18 Q5
8
17
16
15
8
17
16
15
D6
D7
D8
Q6
Q7
Q8
D6
D7
D8
Q6
Q7
Q8
9
9
10
10
D9 11
14 Q9
13
MR 11
14 CE
13
GND 12
GND 12
CP
SF00485
CP
SF00488
LOGIC SYMBOL – 74F823
LOGIC SYMBOL – 74F822
2
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
CP
CE
MR
OE
13
14
11
1
CP
OE
13
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15
SF00489
23 22 21 20 19 18 17 16 15 14
SF00486
V
= Pin 24
CC
V
= Pin 24
CC
GND = Pin 12
GND = Pin 12
4
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
IEC/IEEE SYMBOL – 74F823
IEC/IEEE SYMBOL – 74F824
1
1
EN1
R
EN1
11
14
13
11
R
14
G1
G1
13
1G2
1G2
2
23
22
21
20
19
18
17
16
15
2
23
22
21
20
19
18
17
16
15
2D
1
2D
1
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
SF00490
SF00493
PIN CONFIGURATION – 74F824
PIN CONFIGURATION – 74F825
1
2
3
4
5
24
V
OE0
OEI
DO
D1
OE
D0
D1
D2
1
2
3
4
5
24
23
22
CC
V
CC
Q0
23
22
21
20
OE2
QO
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CE
CP
Q1
21 Q2
D2
20
19
D3
D4
D5
Q3
Q4
D3
6
7
19
18
17
16
15
14
13
6
7
D4
18 Q5
D5
8
8
17
16
15
D6
D7
D8
Q6
Q7
Q8
D6
9
9
10
11
D7
10
MR
MR 11
14 CE
13
GND 12
GND 12
CP
SF00491
SF00494
LOGIC SYMBOL – 74F824
LOGIC SYMBOL – 74F825
2
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9 10
D0 D1 D2 D3 D4 D5 D6 D7 D8
D0 D1 D2 D3 D4 D5 D6 D7
13
14
11
1
CP
CP
CE
MR
OE
13
14
11
1
CE
MR
OE0
OE1
OE2
2
23
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
23 22 21 20 19 18 17 16 15
22 21 20 19 18 17 16 15
SF00495
V
= Pin 24
V
= Pin 24
CC
CC
GND = Pin 12
GND = Pin 12
SF00492
5
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
IEC/IEEE SYMBOL – 74F825
LOGIC SYMBOL – 74F826
&
1
3
4
5
6
7
8
9 10
2
EN
23
11
14
13
D0 D1 D2 D3 D4 D5 D6 D7
13
14
11
1
CP
R
CE
G1
1G2
MR
OE0
OE1
OE2
2
3
22
21
20
19
18
17
16
15
23
2D
1
4
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
5
6
22 21 20 19 18 17 16 15
SF00498
V
= Pin 24
GND = Pin 12
7
CC
8
9
IEC/IEEE SYMBOL – 74F826
10
&
1
SF00496
2
EN
23
11
14
13
PIN CONFIGURATION – 74F826
R
G1
1
24
23
22
21
20
V
OE0
CC
1G2
2
OE2
QO
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CE
CP
OEI
3
DO
3
22
21
20
19
18
17
16
15
2D
1
4
4
D1
5
5
D2
6
D3
D4
D5
D6
D7
MR
6
7
19
18
17
16
15
14
13
7
8
8
9
9
10
10
11
SF00499
GND 12
SF00497
LOGIC DIAGRAM FOR 74F821
D8
10
D9
11
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
13
1
CP
OE
15
Q8
14
Q9
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
V
= Pin 24
CC
GND = Pin 12
SF00500
6
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
LOGIC DIAGRAM FOR 74F822
D8
10
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D9
11
D
CP
D
Q
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
Q
Q
Q
Q
Q
Q
Q
Q
Q
13
1
CP
OE
15
Q8
14
Q9
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
V
= Pin 24
CC
GND = Pin 12
SF00501
FUNCTION TABLE FOR 74F821 AND 74F822
OUTPUTS
INPUTS
OPERATING MODE
74F821
74F822
OE
L
CP
↑
Dn
l
Q
L
Q
H
Load and read data
L
↑
h
H
L
L
↑
X
X
NC
Z
NC
Z
Hold
H
X
High impedance
H = High-voltage level
h
L
l
=
=
=
High state must be present one setup time before the low-to-high clock transition
Low-voltage level
Low state must be present one setup time before the low-to-high clock transition
NC= No change
X
Z
↑
=
=
=
=
Don’t care
High impedance “off” state
Low-to-high clock transition
Not low-to-high clock transition
↑
LOGIC DIAGRAM FOR 74F823
14
CE
D8
10
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
13
CP
CP
Q
CP
D
Q
R
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
11
MR
1
OE
15
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
Q8
V
= Pin 24
CC
GND = Pin 12
SF00502A
7
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
LOGIC DIAGRAM FOR 74F824
D8
10
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
14
13
CE
CP
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
11
1
MR
OE
15
Q8
SF00503A
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
V
= Pin 24
CC
GND = Pin 12
FUNCTION TABLE for 74F823 and 74F824
OUTPUTS
INPUTS
OPERATING MODE
74F823
74F824
OE
L
MR
L
CE*
X
CP
X
↑
Dn
X
h
Q
L
Q
L
Clear
L
H
L
H
L
Load and read data
L
H
L
↑
l
L
H
L
H
H
X
X
X
X
NC
Z
NC
Z
Hold
H
X
X
High impedance
H = High-voltage level
h
L
l
=
=
=
High state must be present one setup time before the low-to-high clock transition
Low-voltage level
Low state must be present one setup time before the low-to-high clock transition
NC= No change
X
Z
*
=
=
=
Don’t care
High impedance “off” state
Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders
or other potentially glitch prone device on the CE input.
↑
=
Low-to-high clock transition
LOGIC DIAGRAM FOR 74F825
14
CE
D0
D1
D2
D3
D4
D5
D6
D7
10
3
4
5
6
7
8
9
13
CP
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
11
MR
1
OE0
2
OE1
23
22
Q0
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
SF00504A
OE2
V
= Pin 24
CC
GND = Pin 12
8
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
LOGIC DIAGRAM FOR 74F826
D0
D1
4
D2
5
D3
6
D4
7
D5
D6
D7
10
3
8
9
14
13
CE
CP
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
11
MR
1
OE0
OE1
2
23
15
Q7
22
21
20
19
18
Q4
17
Q5
16
Q6
OE2
Q0
Q1
Q2
Q3
V
= Pin 24
CC
GND = Pin 12
SF00505A
FUNCTION TABLE FOR 74F825 AND 74F826
OUTPUTS
INPUTS
OPERATING MODE
74F825
74F826
OEn
MR
L
CE*
X
CP
X
↑
Dn
X
h
Q
L
Q
L
L
L
L
L
H
Clear
H
L
H
L
Load and read data
H
L
↑
l
L
H
H
H
X
X
X
X
NC
Z
NC
Z
Hold
X
X
High impedance
H = High-voltage level
h
L
l
=
=
=
High state must be present one setup time before the low-to-high clock transition
Low-voltage level
Low state must be present one setup time before the low-to-high clock transition
NC= No change
X
Z
*
=
=
=
Don’t care
High impedance “off” state
Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders
or other potentially glitch prone device on the CE input.
↑
=
Low-to-high clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
V
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
128
OUT
OUT
CC
I
mA
°C
°C
°C
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
T
amb
Operating free-air temperature range
Storage temperature range
T
stg
9
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
RECOMMENDED OPERATING CONDITIONS
LIMITS
UNIT
PARAMETER
SYMBOL
MIN
4.5
NOM
MAX
V
V
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–24
64
V
I
I
I
mA
mA
mA
°C
°C
Ik
High–level output current
Low–level output current
OH
OL
Commercial range
Industrial range
0
+70
+85
T
amb
Operating free-air temperature range
–40
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
2.4
2.4
2.0
2.0
TYP
MAX
±10%V
V
V
V
V
V
CC
I
= –15mA
= –24mA
OH
OH
I
V
V
V
= MIN,
= MAX,
= MIN
CC
±5%V
CC
V
OH
High-level output voltage
IL
IH
±10%V
CC
CC
I
±5%V
V
V
V
= MIN,
= MAX,
= MIN
±10%V
0.55
CC
IL
IH
CC
V
OL
Low-level output voltage
= MAX
OL
±5%V
0.42
0.55
–1.2
100
20
V
CC
V
IK
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73
V
I
I
I
I
I
I
I
Input current at maximum input voltage
High–level input current
= 0.0V, V = 7.0V
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
I
= MAX, V = 2.7V
IH
I
Low–level input current
= MAX, V = 0.5V
–20
50
IL
I
Off–state output current, high–level voltage applied
Off–state output current, low–level voltage applied
= MAX, V = 2.7V
O
OZH
OZL
OS
= MAX, V = 0.5V
–50
-225
105
105
115
100
105
110
85
O
3
Short–circuit output current
= MAX
-100
I
75
75
75
65
70
75
60
60
65
CCH
74F821,
74F822
V
CC
V
CC
V
CC
= MAX
I
CCL
CCZ
CCH
I
I
74F823,
74F824
I
Supply current (total)
= MAX
= MAX
I
CC
CCL
CCZ
CCH
I
I
74F825,
74F826
I
90
CCL
I
95
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
10
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
AC ELECTRICAL CHARACTERISTICS FOR 74F821/74F822/74F824/74F825/74F826
LIMITS
T
V
= +25°C
= +5.0V
T
V
L
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
amb
CC
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω C = 50pF, R = 500Ω
L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
150
180
140
ns
ns
max
t
t
Propagation delay
CP to Qn or Qn
74F821,
74F825, 74F826
4.0
4.0
6.5
6.0
8.5
8.5
4.0
3.5
9.5
9.0
PLH
PHL
t
t
Propagation delay
CP to Qn
4.5
4.5
6.5
6.5
9.0
9.0
4.5
4.5
10.0
9.0
PLH
PHL
74F822, 74F824
Waveform 1
Waveform 2
ns
ns
ns
ns
Propagation delay
MR to Qn or Qn
74F824
74F825, 74F826
t
3.0
5.0
8.0
3.0
8.0
PHL
t
t
Output enable time
OEn to Qn or Qn
Waveform 4
Waveform 5
2.0
3.0
4.5
5.0
8.0
8.0
2.0
2.5
9.0
9.0
PZH
PZL
t
t
Output disable time
OEn to Qn or Qn
Waveform 4
Waveform 5
1.5
1.5
3.5
3.5
6.5
6.5
1.5
1.5
7.5
7.5
PHZ
PLZ
AC SETUP REQUIREMENTS FOR 74F821/74F822/74F824/74F825/74F826
LIMITS
T
V
= +25°C
= +5.0V
T
V
L
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
amb
CC
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω C = 50pF, R = 500Ω
L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
Dn to CP
1.0
1.0
1.0
1.0
su
su
Waveform 3
Waveform 3
Waveform 1
Waveform 3
Waveform 3
ns
ns
ns
ns
ns
t (H)
Hold time, high or low
Dn to CP
2.0
2.0
2.0
2.0
h
t
h
(L)
t
w
t
w
(H)
(L)
CP Pulse width,
high or low
3.5
3.5
4.0
4.0
t
su
t
su
(H)
(L)
Setup time, high or low,
CE to CP
0.0
2.0
0.0
2.0
t (H)
Hold time, high or low
CE to CP
0.0
3.0
0.0
3.5
h
74F824, 74F825,
74F826
t
t
t
(L)
h
(L)
MR Pulse width, low
Waveform 2
Waveform 2
4.5
2.5
4.5
2.5
ns
ns
w
Recovery time, MR to CP
rec
11
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
AC ELECTRICAL CHARACTERISTICS FOR 74F823
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
T
= –40°C to +85°C
V = +5.0V ± 10%
CC
amb
CC
amb
CC
amb
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF
R = 500Ω
L
C = 50pF
R = 500Ω
L
C = 50pF
R = 500Ω
L
L
L
L
MIN TYP MAX
MIN
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
150
180
140
130
ns
ns
max
t
t
Propagation delay
CP to Qn or Qn
4.0
4.0
6.5
6.0
8.5
8.5
4.0
3.5
9.5
9.0
4.0
3.5
10.0
9.0
PLH
PHL
Propagation delay
MR to Qn or Qn
t
Waveform 2
3.0
5.0
8.0
3.0
8.0
3.0
8.5
ns
ns
ns
PHL
t
t
Output enable time
OEn to Qn or Qn
Waveform 4
Waveform 5
2.0
3.0
4.5
5.0
8.0
8.0
2.0
2.5
9.0
9.0
2.0
2.5
11.0
9.0
PZH
PZL
t
t
Output disable time
OEn to Qn or Qn
Waveform 4
Waveform 5
1.5
1.5
3.5
3.5
6.5
6.5
1.5
1.5
7.5
7.5
1.5
1.5
8.5
8.5
PHZ
PLZ
AC SETUP REQUIREMENTS FOR 74F823
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
T
= –40°C to +85°C
V = +5.0V ± 10%
CC
amb
CC
amb
CC
amb
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF
R = 500Ω
L
C = 50pF
R = 500Ω
L
C = 50pF
R = 500Ω
L
L
L
L
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
Dn to CP
1.0
1.0
1.0
1.0
2.0
1.5
su
su
Waveform 3
Waveform 3
Waveform 1
Waveform 3
Waveform 3
Waveform 2
Waveform 2
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time, high or low
Dn to CP
2.0
2.0
2.0
2.0
2.5
2.0
h
t
h
(L)
t
w
t
w
(H)
(L)
CP Pulse width,
high or low
3.5
3.5
4.0
4.0
4.0
4.0
t
su
t
su
(H)
(L)
Setup time, high or low,
CE to CP
0.0
2.0
0.0
2.0
0.0
2.0
t (H)
Hold time, high or low
CE to CP
0.0
3.0
0.0
3.5
1.5
4.0
h
t
h
(L)
MR Pulse width,
low
t
w
(L)
4.5
2.5
4.5
2.5
4.5
2.5
Recovery time,
MR to CP
t
rec
12
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
MR
V
V
M
M
CP
V
V
M
V
M
M
t
(H)
t
(L)
t
w
w
rec
t
t
(L)
t
PHL
w
PLH
V
CP
M
V
V
Qn
Qn
t
PHL
M
M
t
V
PHL
t
M
Qn, Qn
PLH
V
V
M
M
SF00507
Waveform 2. Master reset pulse width, master reset to output
delay and master reset to clock recovery time
SF00506
Waveform 1. Propagation delay for clock input to output,
clock pulse width, and maximum clock frequency
OEn
V
V
M
Dn, CE
M
V
V
V
V
M
M
M
M
V
-0.3V
0V
OH
t
(L)
t (L)
h
t
t
PHZ
t
(H)
t (H)
h
su
PZH
su
Qn, Qn
V
V
CP
M
M
V
M
SF00508
SF00509
Waveform 3. Data setup time and hold times
Waveform 4. 3-State output enable time to high level and
output disable time from high level
OEn
V
t
V
M
M
t
PZL
PLZ
3.5V
V
M
Qn, Qn
V
+0.3V
OL
SF00510
Waveform 5. 3-State output enable time to low level and
output disable time from low level
13
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
TEST CIRCUIT AND WAVEFORMS
V
CC
t
w
AMP (V)
0V
7.0V
90%
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
10%
10%
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00128
14
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
15
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
16
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
NOTES
17
1996 Jan 05
Philips Semiconductors
Product specification
Bus interface registers
74F821/822/823/824/825/826
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
(print code)
Date of release: July 1994
9397-750-05185
Document order number:
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