74F835 [NXP]
8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out; 8位的移位寄存器2： 1复用器式，锁存的“B”输入端，而串行输出
| 型号： | 74F835 |
| 厂家： | 
NXP |
| 描述： | 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out |
| 文件： | 总6页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
8-bit shift register with 2:1 mux-in,
latched “B” inputs, and serial out
74F835
FEATURES
PIN CONFIGURATION
• Specifically designed for Video applications
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
PE
CP
• Combines the 74F373, two 74F157s, and the 74F166 functions in
D3B
D3A
D2B
D2A
D1B
D1A
D0B
one package
3
D4A
D4B
D5A
D5B
D6A
D6B
D7A
D7B
Q7
• Interleaved loading with 2:1 mux
• Dual 8-bit parallel inputs
• Transparent latch on all “B” inputs
• Guaranteed serial shift frequency to 100MHz
• Expandable to 16-bits or more with serial input
4
5
6
7
8
9
D0A
DS
DESCRIPTION
10
11
The 74F835 is a high speed 8-bit parallel/serial-in, serial-out shift
register whose parallel inputs have been connected to an internal
octal two-to-one multiplexer with all the “B” inputs connected to an
octal latch.
SA/B
LE
GND 12
SF01355
This 24-pin part is specifically designed for video bit shifting, where
interleaved loading is desired and parts count is critical. It is useful in
any design where a 2:1 mux input with a transparent latch is
needed.
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%,
PACKAGE
DRAWING
NUMBER
V
DESCRIPTION
CC
T
amb
= 0°C to +70°C
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
24-pin plastic
Slim DIP (300 mil)
N74F835N
SOT222-1
SOT137-1
24-pin plastic SOL
N74F835D
74F835
150MHz
45mA
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0A – D7A
D0B – D7B
DS
DESCRIPTION
Parallel data inputs
74F (U.L.) HIGH/LOW
1.0/1.0
LOAD VALUE HIGH/LOW
20µA/0.6mA
Latched Parallel data inputs
Serial data input
1.0/1.0
20µA/0.6mA
1.0/1.0
20µA/0.6mA
CP
Shift Register Clock input (active rising edge)
Mux Select
1.0/1.0
20µA/0.6mA
SA/B
1.0/1.0
20µA/0.6mA
LE
Latch Enable input (for B inputs)
Parallel Enable input
1.0/1.0
20µA/0.6mA
PE
1.0/1.0
20µA/0.6mA
Q7
Output
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1
1990 Jan 08
853–0615 99490
Philips Semiconductors
Product specification
8-bit shift register with 2:1 mux-in,
latched “B” inputs, and serial out
74F835
LOGIC SYMBOL
IEC/IEEE SYMBOL
SRG 8
2
C1
15 16 17 18 19 20 21 22 23
3
4
5
6
7
8
9
10
MUX
1
M4
13
14
EN3
G2
DS
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D0A D1A
D2A
D3A
D4A
D5A
D6A
D7A
2
1
CP
PE
LE
15
16
17
18
19
20
21
22
23
3
1,4
13
14
1, 2, 3, 4
1, 2, 3, 4
SA/B
Q7
11
V
= PIN 24
CC
GND = PIN 12
SF01356
4
5
6
7
8
9
11
10
SF01357
TYPICAL TIMING DIAGRAM
UNLOAD
B LATCH
LOAD A
PE
SHIFT A
SHIFT B
CP
LOAD B LATCH
LE
SA/B
D0A
SET B
D7A
D0B
D7B
q7A
Q7
q6A
q1A q0A
q7B
q6B
q5B
q0B
SF01359
2
1990 Jan 08
Philips Semiconductors
Product specification
8-bit shift register with 2:1 mux-in,
latched “B” inputs, and serial out
74F835
LOGIC DIAGRAM
D0B
17
D1B
19
D2B
21
D3B
23
D4B
4
D5B
6
D6B
8
D7B
10
D7A
9
D0A
16
D1A
18
D2A
20
D3A
22
D4A
3
D5A
5
D6A
7
13
LE
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
D
Q
E
14
SA/B
1
PE
DS
15
11
Q7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
2
CP
V
= PIN 24
CC
GND = PIN 12
SF01358
FUNCTION TABLE
INTERNAL
SERIAL REGISTER
INPUTS
OUTPUT
Q7
OPERATING
MODE
B
LATCH
PE
CP
LE
SA/B
DnA
DnB
DS
Q0
Q1–6
h
l
X
X
X
X
X
X
H
L
H
L
H
L
Parallel load
A data
L
↑
X
↑
↑
↑
X
L
X
X
h
l
X
X
H
L
X
X
X
X
X
X
Latch B data
X
L
L
L
X
H
H
X
X
X
X
X
X
X
h
l
H
L
H
L
H
L
Parallel load B data
(from Latch)
X
X
h
l
X
X
h
l
H
L
H
L
H
L
Parallel load B data
(Transparent Mode)
L
H
X
X
X
X
X
h
l
X
X
H
L
qn–1
qn–1
q6
q6
Serial Shift
H
H
L
h
l
=
=
=
=
=
High voltage level
Low voltage level
High voltage level one setup time prior to the Low-to-High clock transition
Low voltage level one setup time prior to the Low-to-High clock transition
Don’t care
X
qn = Lower case letters indicate the state of the referenced flop cell one cycle prior to the Low-to-High clock transition
Low-to-High clock transition
↑
=
3
1990 Jan 08
Philips Semiconductors
Product specification
8-bit shift register with 2:1 mux-in,
latched “B” inputs, and serial out
74F835
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
OUT
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
40
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
20
T
amb
Operating free-air temperature range
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
±10% V
= MIN, V = MAX
IL
UNIT
2
MIN
2.5
TYP
MAX
V
V
CC
V
V
CC
IH
V
OH
= MIN, I = MAX
OH
±5% V
2.7
3.4
CC
±10% V
0.30
0.30
0.50
0.50
–1.2
100
20
V
CC
V
V
= MIN, V = MAX
IL
CC
IH
V
V
OL
= MIN, I L= MAX
OH
±5% V
V
CC
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73
V
IK
I
I
I
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
µA
µA
mA
mA
mA
I
I
= MAX, V = 2.7V
IH
I
Low-level input current
= MAX, V = 0.5V
–0.6
–150
65
IL
I
3
Short circuit output current
= MAX
= MAX
–60
OS
Supply current (total)
45
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V. T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other tests. In any sequence of
parameter tests, I tests should be performed last.
OS
4
1990 Jan 08
Philips Semiconductors
Product specification
8-bit shift register with 2:1 mux-in,
latched “B” inputs, and serial out
74F835
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
amb
CC
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
130
150
100
MHz
ns
MAX
t
t
Propagation delay
CP to Q7 (Load)
5.0
5.0
7.0
7.0
9.5
9.5
5.0
5.0
10.0
10.0
PLH
PHL
t
t
Propagation delay
CP to Q7 (Shift)
5.0
5.0
7.0
7.0
9.5
9.5
5.0
5.0
10.0
10.0
PLH
PHL
Waveform 1
ns
AC SETUP REQUIREMENTS
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
amb
CC
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Setup time
DnA or DnB to CP
3.5
3.5
3.5
3.5
s
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 2
Waveform 1
Waveform 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time
DnA or DnB to CP
1.0
1.0
1.5
1.5
h
t (L)
h
t (H)
Setup time
DS to CP
1.0
1.0
1.5
1.5
s
t (L)
s
t (H)
Hold time
DS to CP
2.0
2.0
2.5
2.5
h
t (L)
h
t (H)
Setup time
PE to CP
3.5
3.5
4.0
4.0
s
t (L)
s
t (H)
Hold time
PE to CP
0.0
0.0
0.0
0.0
h
t (L)
h
t (H)
Setup time
DnB to LE
0.0
0.0
0.0
0.0
s
t (L)
s
t (H)
Hold time
DnB to LE
3.0
3.0
4.0
4.0
h
t (L)
h
t (H)
Setup time
SA/B to CP
4.5
4.5
5.0
5.0
s
t (L)
s
t (H)
Hold time
SA/B to CP
0.0
0.0
0.0
0.0
h
t (L)
h
t (H)
clock pulse width,
High or Low
4.5
4.5
5.5
5.0
w
t (L)
w
Latch Enable pulse width,
High
t (H)
w
4.5
5.0
5
1990 Jan 08
Philips Semiconductors
Product specification
8-bit shift register with 2:1 mux-in,
latched “B” inputs, and serial out
74F835
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
DS, PE
V
V
V
V
M
M
M
M
CP
Q7
DnA, DnB
SA/B
V
t
V
V
t
M
t
M
t
M
t (H)
h
t (L)
h
t (H)
t (L)
s
(H)
(L)
s
W
W
PHL
PLH
CP, LE
V
V
M
M
V
V
M
M
SF00287
SF01360
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Data and Select Setup and Hold Times
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
0V
V
CC
90%
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
family
74F
V
rep. rate
t
t
t
THL
amplitude
M
w
TLH
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
6
1990 Jan 08
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