74F8963 [NXP]
9-Bit latched bidirectional Futurebus transceivers open-collector; 9位锁存双向FUTUREBUS收发器，集电极开路
| 型号： | 74F8963 |
| 厂家： | 
NXP |
| 描述： | 9-Bit latched bidirectional Futurebus transceivers open-collector |
| 文件： | 总10页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
power consumption and a series diode on
the drivers to reduce capacitive loading.
FEATURES
• Octal latched transceiver
• Multiple GND pins minimize ground bounce
• Glitch–free power up/power down
Incident wave switching to 9Ω is guaranteed.
The voltage swing is much less for BTL, so is
its receiver threshold region, therefore noise
margins are excellent.
operation
• Drives heavily loaded backplanes with
equivalent load impedances down to 10Ω
DESCRIPTION
• High drive (100mA) open collector drivers
The 74F8962 and 74F8963 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired-OR bus. The B port
inverting drivers are low-capacitance open
collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 150mV
threshold region.
on B port
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
• Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
The 74F8962 and 74F8963 A ports have TTL
3-state drivers and TTL receivers with a latch
function.
• Compatible with IEEE 896 futurebus
standards
The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
The 74F8963 is the non-inverting version of
74F8962.
• Built–in precision band–gap reference
provides accurate receiver thresholds and
improved noise immunity
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT( TOTAL)
74F8962
74F8963
6.5ns
5.5ns
90mA
90mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
V
CC
amb
1
44–pin Quad Flat Pack
N74F8962Y, N74F8963Y
N74F8962A, N74F8963A
44–pin Plastic Leaded Chip Carrier
Note to ordering information
1. Flatpack package is not available at this time.
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
AI0 – AI8
B0 – B8
PNP latched inputs
1.0/0.167
5.0/0.167
1.0/0.033
1.0/0.033
150/40
20µA/100µA
100µA/100µA
20µA/20µA
20µA/20µA
3mA/24mA
OC/100mA
Data inputs with threshold circuitry
Output enable inputs (active low)
Latch enable inputs (active low)
3–state outputs
OEAB, OEBA
LEAB, LEBA
AO0 – AO8
B0 – B8
Open collector outputs
OC/166.7
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
1
March 11, 1993
853–1425 09230
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
PIN CONFIGURATION FLATPACK AND PLCC
IEC/IEEE SYMBOL
74F8962
74F8962
24
25
43
44
V
EN1
EN2
EN3
EN4
GND AO1 AI1 AO0 AI0
OEBA LEBA BO GND B1
CC
44
40
6
5
4
3
2
1
43
42
41
AI2
AO2
A13
AO3
AI4
7
8
GND
B2
39
42
2
3
4
5
7
8
9
38
37
36
1
4
2
3D
9
10
11
GND
B3
40
38
36
34
32
30
35
34
33
GND
B4
GND 12
10
11
13
14
15
16
17
19
20
21
22
AO4
AI5
13
14
GND
B5
32
31
15
16
AO5
AI6
GND
B6
30
29
28
26
AO6
17
GND
18
19
20
21
22
23
24
25
26
27
28
B8
GND AI7 AO7 AI8 AO8
LEAB OEAB
GND B7
V
CC
PIN DESCRIPTION
SYMBOL
PINS
2, 4, 7, 9, 11, 14, 16, 19, 21
TYPE
NAME AND FUNCTION
AI0 – AI8
Input
I/O
PNP latched inputs.
B0 – B8
OEAB
42, 40, 38, 36, 34, 32, 30, 28, 26
Data input / open collector output, high current drives.
Output enable input. Enables the B outputs when low.
Output enable input. Enables the A outputs when high.
Latch enable input. Enables the AB latches low.
Latch enable input. Enables the BA latches low.
25
Input
Input
Input
Input
OEBA
44
LEAB
24
LEBA
43
AO0 – AO8
GND
3, 5, 8, 10, 13, 15, 17, 20, 22
Output TTL 3–state outputs.
6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41 Ground Grounds
1, 23 Power Positive supply voltages
V
CC
2
March 11, 1993
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
LOGIC SYMBOL FOR 74F8962
74F8962
2
3
4
5
7
8
9
10 11 13 14 15 16 17 19 20 21 22
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8
25
24
43
44
OEAB
LEAB
LEBA
OEBA
B0 B1 B2 B3 B4 B5 B6 B7 B8
V
= Pin 1, 23
CC
42 40 38 36 34 32 30 28 26
GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
LOGIC SYMBOL FOR 74F8963
74F8963
2
3
4
5
7
8
9
10 11 13 14 15 16 17 19 20 21 22
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8
25
24
43
44
OEAB
LEAB
LEBA
OEBA
B0 B1 B2 B3 B4 B5 B6 B7 B8
V
= Pin 1, 23
CC
42 40 38 36 34 32 30 28 26
GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
3
March 11, 1993
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
LOGIC DIAGRAM
74F8963
74F8962
25
43
24
44
25
43
24
44
OEAB
LEBA
LEAB
OEBA
OEAB
LEBA
LEAB
OEBA
2
2
Data
E
Q
AI0
42
40
38
36
34
32
30
28
26
Data
E
Q
AI0
42
B0
B1
B2
B3
B4
B5
B6
B7
B8
B0
3
3
Q
Data
E
Q
Data
E
AO0
AI1
AO0
AI1
4
4
Data
E
Q
Data
E
Q
40
B1
5
5
Q
Data
E
Q
Data
E
AO1
AI2
AO1
AI2
7
7
Data
E
Q
Data
E
Q
38
B2
8
8
Q
Data
E
AO2
AI3
Q
Data
E
AO2
AI3
9
9
Data
E
Q
Data
E
Q
36
B3
10
11
13
14
15
16
17
19
20
21
22
10
11
13
14
15
16
17
19
20
21
22
Q
Data
E
AO3
AI4
Q
Data
E
AO3
AI4
Data
E
Q
Data
E
Q
34
B4
Q
Data
E
AO4
AI5
Q
Data
E
AO4
AI5
Data
E
Q
Data
E
Q
32
B5
Q
Data
E
AO5
AI6
Q
Data
E
AO5
AI6
Data
E
Q
Data
E
Q
30
B6
Q
Data
E
AO6
AI7
Q
Data
E
AO6
AI7
Data
E
Q
Data
E
Q
28
B7
Q
Data
E
AO7
AI8
Q
Data
E
AO7
AI8
Data
E
Q
Data
E
Q
26
B8
AO8
Q
Data
E
AO8
Q
Data
E
V
= Pin 1, 23
CC
GND = Pin 6, 12, 18, 27, 29, 31, 33, 37, 39, 41
4
March 11, 1993
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
FUNCTION TABLE FOR 74F8962
INPUTS
LATCH STATES
OUTPUTS
OPERATING MODE
AIn Bn*
LEAB
LEBA
OEAB
OEBA
AB
H
BA
H
AOn
Z
Bn
X
H
L
H
L
L
L
L
L
H
H
H
L
H
H
H
H
H
L
L
L
Z
X
B and AO disabled
X
H
L
X
–
H
L
H
X
X
L
Qn
H
Qn
Qn
Qn
H
Z
X
Z
L
AO 3–state, transparent data from AI to B
B disabled, transparent data from B to AO
–
L
L
L
Z
H**
X
X
X
X
X
X
H
L
H
L
X
X
H
X
H
L
H
H
L
Qn
Qn
Qn
Qn
Qn
H
L
L
L
L
H
X
X
X
X
–
X
H
H
L
H
L
Qn
Qn
Qn
L
Z
Qn AO 3–state, latched data to B
B disabled, latched to AO
Qn Latched state to AO and B
Read back from AI to B to AO
H** (both latches transparent)
H
L
Qn
Qn
H
X
L
L
L
L
–
L
L
L
L
L
H
L
Notes to function table for 74F8962
1. H = High voltage level
2. L
3. X
4. –
5. Z
=
=
=
=
Low voltage level
Don’t care
Input not externally driven
High impedance ”off’ state
6. Q = High or low voltage level one setup time prior to the low–to–high LEXX transition.
n
7. H**= Goes to level of pullup voltage.
8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8963
INPUTS
LATCH STATES
OUTPUTS
OPERATING MODE
AIn Bn*
LEAB
LEBA
OEAB
OEBA
AB
L
BA
L
AOn
Z
Bn
X
H
L
H
L
L
L
L
L
H
H
H
L
H
H
H
H
H
L
H
H
Z
X
B and AO disabled
X
H
L
X
–
H
L
H
X
X
L
Qn
L
Qn
Qn
Qn
L
Z
X
Z
H
L
AO 3–state, transparent data from AI to B
B disabled, transparent data from B to AO
–
L
L
H
Z
X
X
X
X
X
H
L
H
L
X
X
H
X
H
L
H
H
L
Qn
Qn
Qn
Qn
Qn
L
H
X
L
L
H
L
X
X
X
X
–
X
H
H
L
H
L
Qn
Qn
Qn
L
Z
Qn AO 3–state, latched data to B
B disabled, latched to AO
H
L
Qn
Qn
H
X
L
Qn Latched state to AO and B
L
L
H** Read back from AI to B to AO
–
L
L
L
L
H
L
L
L
(both latches transparent)
Notes to function table for 74F8963
1. H = High voltage level
2. L
3. X
4. –
5. Z
=
=
=
=
Low voltage level
Don’t care
Input not externally driven
High impedance ”off” state
6. Q = High or low voltage level one setup time prior to the low–to–high LEXX transition.
n
7. H**= Goes to level of pullup voltage.
8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
5
March 11, 1993
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
Supply voltage
Input voltage
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +5.5
–40 to +5
V
V
CC
OEBA, OEAB, LEBA, LEAB
AI0 – AI8, B0 – B8
IN
V
I
IN
Input current
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
V
OUT
CC
AO0 – AO8
B0 – B8
48
mA
mA
°C
°C
OUT
200
T
amb
Operating free air temperature range
Storage temperature range
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
V
Supply voltage
4.5
5.0
5.5
CC
IH
V
High–level input voltage
Except B0 – B8
2.0
V
B0 – B8
Except B0 – B8
B0 – B8
1.62
V
V
Low–level input voltage
0.8
1.47
–18
–3
V
IL
V
I
I
I
Input clamp current
mA
mA
mA
mA
Ik
High–level output current
Low–level output current
AO0 – AO8
AO0 – AO8
B0 – B8
OH
OL
24
100
+70
T
amb
Operating free air temperature
0
°C
6
March 11, 1993
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN TYP
MAX
100
I
I
High-level output current
B0 – B8
B0 – B8
V
V
V
V
V
V
V
= MAX, V = MAX, V = MIN, V = 2.1V
µA
µA
V
OH
CC
CC
CC
CC
IL
IH
OH
Power-off output current
High-level output voltage
= 0.0V, V = MAX, V = MIN, V = 2.1V
100
OFF
IL
IH
OH
4
4
V
V
V
AO0 – AO8
AO0 – AO8
B0 – B8
= MAX, V = MAX, V = MIN, I = –3mA
2.5
V
CC
OH
OL
IK
IL
IH
OH
= MIN,
I
OL
= 24mA
0.50
1.10
V
Low-level output voltage
Input clamp voltage
= MAX
= MIN
I
OL
= 100mA
0.75
0.40
1.0
V
IL
I
OL
= 4mA
V
IH
CC
= MIN, I = I
-1.2
100
1
V
I
IK
OEAB, OEBA,
LEAB, LEBA,
AI0 – AI8
I
I
V
CC
V
CC
V
CC
= MAX, V = 7.0V
µA
mA
µA
Input current at
maximum input voltage
I
B0 – B8
= MAX, V = 5.5V
I
OEAB, OEBA,
LEAB, LEBA,
AI0 – AI8
= MAX, V = 2.7V
20
I
I
I
High-level input current
Low-level input current
IH
B0 – B8
V
CC
V
CC
= MAX, V = 2.1V
100
µA
µA
I
OEAB, OEBA,
LEAB, LEBA,
AI0 – AI8
= MAX, V = 0.5V
–100
I
IL
B0 – B8
V
V
= MAX, V = 0.3V
–100
50
µA
µA
CC
I
Off state output current,
high-level voltage applied
I
I
I
AO0 – AO8
= MAX, V = 2.7V
O
OZH
OZL
OS
CC
Off state output current,
low-level voltage applied
µA
V
V
= MAX, V = 0.5V
–50
CC
I
AO0 –
74F8962
AO8
= MAX, Bn = 1.3V, OEBA = 0.8V,
CC
OEAB = 2.7V
V = MAX, Bn = 1.8V, OEBA = 0.8V,
CC
Short circuit output
-60
-150
mA
3
current
only 74F8963
OEAB = 2.7V
I
I
V
V
= MAX
80
105
80
110
145
110
mA
mA
mA
CCH
CC
I
Supply current (total)
I
= MAX, V = 0.5V
IL
CC
CCL
CCZ
CC
NOTES TO DC ELECTRICAL CHARACTERISTICS
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Due to test equipment limitations, actual test conditions are for V = 1.8V and V = 1.3V.
IH
IL
7
March 11, 1993
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
AC ELECTRICAL CHARACTERISTICS FOR 74F8962
A PORT LIMITS
T
amb
= +25°C
T
amb
= 0°C to
T
amb
= 0°C to
+70°C
+70°C
V
CC
= +5.0V ± 10%
V
CC
= +5.0V ± 5%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
Propagation delay
Bn to AOn
5.0
3.5
7.0
5.5
10.0
8.5
4.5
3.5
11.0
8.5
4.5
3.5
10.5
8.5
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 5, 6
Waveform 5, 6
Waveform 4
ns
ns
ns
ns
ns
t
t
Propagation delay
LEBA to AOn
5.5
4.5
7.0
6.5
10.0
9.5
5.0
4.5
10.0
9.5
5.0
4.5
10.0
9.5
PLH
PHL
t
t
Output enable time to high or
low, OEBA to AOn
7.5
8.5
9.5
10.5 13.0
12.5
6.5
7.5
13.5
14.5
6.5
7.5
13.0
13.5
PZH
PZL
t
t
Output disable from high or low,
OEBA to AOn
3.5
4.5
5.5
6.5
8.5
9.5
2.5
4.0
10.0
10.0
2.5
4.0
9.0
9.5
PHZ
PLZ
Skew between receivers in
same package
t
1.5
2.0
4.0
4.0
sk(o)
B PORT LIMITS
T
amb
= +25°C
T
amb
= 0°C to
T
amb
= 0°C to
+70°C
+70°C
V
CC
= +5.0V ± 10%
V
CC
= +5.0V ± 5%
SYMBOL
PARAMETER
TEST
CONDITION
V
C
= +5.0V
= 30pF,
= 9Ω
UNIT
CC
C
= 30pF,
C = 30pF,
D
D
D
R
R
= 9Ω
R = 9Ω
U
U
U
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
Propagation delay
AIn to Bn
3.5
4.0
5.5
6.0
8.5
9.5
3.0
3.5
9.0
10.5
3.0
3.5
9.0
10.0
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 1
ns
ns
ns
ns
ns
t
t
Propagation delay
LEAB to Bn
4.0
5.0
6.0
7.0
8.5
10.5
3.5
5.0
9.5
10.5
3.5
5.0
9.5
10.5
PLH
PHL
t
t
Output enable/disable time
OEBA to Bn
3.5
3.0
5.0
4.0
8.0
8.0
3.0
2.5
8.5
8.5
3.0
2.5
8.0
8.5
PLH
PHL
t
t
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and 1.0
1.2
2.0
1.6
2.5
1.0
1.0
2.5
3.5
1.0
1.0
2.5
3.5
TLH
THL
waveforms
1.0
Skew between drivers in same
package
t
Waveform 4
0.5
2.5
3.0
3.0
sk(o)
AC SETUP REQUIREMENTS FOR 74F8962
LIMITS
= 0°C to
+70°C
T
amb
= +25°C
T
amb
T
amb
= 0°C to
+70°C
V
CC
= +5.0V ± 10%
V
CC
= +5.0V ± 5%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
AIn to LEAB
3.0
1.0
3.5
2.0
3.0
1.5
su
su
Waveform 3
Waveform 3
Waveform 3
ns
ns
ns
th(H)
th(L)
Hold time, high or low
AIn to LEAB
3.0
0.0
3.5
0.0
3.0
0.0
t
su
t
su
(H)
(L)
Setup time, high or low
Bn to LEBA
2.0
1.0
2.5
1.0
2.0
1.0
t (H)
th(L)
Hold time, high or low
Bn to LEBA
3.0
1.5
3.5
2.0
3.0
2.0
h
Waveform 3
Waveform 3
ns
ns
t (L)
w
LEAB or LEBA pulse width, low
4.5
4.5
4.5
8
March 11, 1993
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
AC ELECTRICAL CHARACTERISTICS FOR 74F8963
A PORT LIMITS
T
amb
= +25°C
T
amb
= 0°C to
T
amb
= 0°C to
+70°C
+70°C
V
CC
= +5.0V ± 10%
V
CC
= +5.0V ± 5%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
Propagation delay
Bn to AOn
3.5
2.5
5.5
4.0
8.0
7.0
3.0
2.0
9.0
7.5
3.0
2.0
8.0
7.5
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 5, 6
Waveform 5, 6
Waveform 4
ns
ns
ns
ns
ns
t
t
Propagation delay
LEBA to AOn
6.0
4.0
7.5
5.5
10.0
8.5
5.0
3.5
11.5
9.0
5.0
3.5
10.0
8.5
PLH
PHL
t
t
Output enable time to high or
low, OEBA to AOn
9.0
11.0 15.0
8.5
9.0
16.5
18.0
8.5
9.0
15.5
16.5
PZH
PZL
10.0 12.0 16.0
t
t
Output disable time from high or
low, OEBA to AOn
4.0
5.5
6.0
7.0
9.0
11.0
3.0
5.0
10.5
12.0
3.0
5.0
9.5
11.0
PHZ
PLZ
Skew between receivers in
same package
t
1.5
2.0
4.0
4.0
sk(o)
B PORT LIMITS
T
amb
= +25°C
T
amb
= 0°C to
T
amb
= 0°C to
+70°C
+70°C
V
CC
= +5.0V ± 10%
V
CC
= +5.0V ± 5%
SYMBOL
PARAMETER
TEST
CONDITION
V
C
= +5.0V
= 30pF,
= 9Ω
UNIT
CC
C
= 30pF,
C = 30pF,
D
D
D
R
R
= 9Ω
R = 9Ω
U
U
U
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
Propagation delay
AIn to Bn
2.0
2.0
4.0
3.5
6.5
6.5
1.5
1.5
7.0
6.5
2.0
2.0
7.0
6.5
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 1
ns
ns
ns
ns
ns
t
t
Propagation delay
LEAB to Bn
3.5
2.5
5.0
4.0
8.0
7.0
3.0
2.0
8.5
8.0
3.5
2.5
8.5
8.0
PLH
PHL
t
t
Output enable/disable time
OEBA to Bn
3.5
3.0
5.5
5.0
9.0
7.5
2.5
2.5
9.5
8.5
2.5
2.5
9.0
8.0
PLH
PHL
t
t
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and 1.0
1.2
2.0
1.6
2.5
1.0
1.0
2.5
3.5
1.0
1.0
2.5
3.5
TLH
THL
waveforms
1.0
Skew between drivers in same
package
t
Waveform 4
0.5
2.0
3.0
3.0
sk(o)
AC SETUP REQUIREMENTS FOR 74F8963
LIMITS
= 0°C to
+70°C
T
amb
= +25°C
T
amb
T
amb
= 0°C to
+70°C
V
CC
= +5.0V ± 10%
V
CC
= +5.0V ± 5%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN TYP MAX
MIN
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
AIn to LEAB
4.0
1.0
4.5
1.5
4.0
1.0
su
su
Waveform 3
Waveform 3
Waveform 3
ns
ns
ns
th(H)
th(L)
Hold time, high or low
AIn to LEAB
2.5
0.0
3.0
0.0
2.5
0.0
t
su
t
su
(H)
(L)
Setup time, high or low
Bn to LEBA
2.0
1.0
2.5
1.0
2.0
1.0
t (H)
th(L)
Hold time, high or low
Bn to LEBA
2.5
1.0
3.0
1.5
3.0
1.0
h
Waveform 3
Waveform 3
ns
ns
t (L)
w
LEAB or LEBA pulse width, low
4.5
5.5
5.5
9
March 11, 1993
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
AC WAVEFORMS
AIn, Bn,
LEAB, LEBA
OEAB
AIn, Bn,
LEAB, LEBA
V
V
V
M
M
t
V
M
M
t
t
t
PHL
PLH
PLH
PHL
AOn, Bn
V
V
V
V
M
M
M
M
An, Bn
Waveform 2. Propagation delay for data or latch enable to
output
Waveform 1. Propagation delay for data or output enable or
latch enable to output
AOn, Bn
V
M
AIn, Bn
V
V
V
t
V
M
M
M
M
t
sk(o)
t
(L)
t (H)
h
(H)
h
su
t
(L)
t (L)
su
w
V
AOn, Bn
V
V
V
M
M
M
M
LEAB, LEBA
Waveform 4. Output skew
Waveform 3. Data setup and hold times and LEAB/LEBA pulse widths
OEAB
An
V
V
V
V
M
OEAB
An
M
M
M
V
-0.3V
0V
OH
t
t
t
t
PLZ
PZH
PHZ
PZL
V
V
M
M
V
+0.3V
OL
Waveform 5. 3–state output enable time to high level
and output disable time from high level
Waveform 6. 3-state output enable time to low level
and output disable time from low level
NOTES TO AC WAVEFORMS
1. For all waveforms, V = 1.5V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
t
AMP (V)
w
90%
90%
TEST
SWITCH
closed
open
NEGATIVE
PULSE
V
CC
V
V
M
M
t
, t
PLZ PZL
10%
10%
7.0V
All other
Low V
R
t
t
)
)
t
t )
L
THL ( f
TLH ( r
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
t
t )
TLH ( r
THL ( f
AMP (V)
Low V
R
C
R
L
90%
M
90%
T
L
POSITIVE
PULSE
V
V
M
10%
10%
Test circuit for 3–state outputs on A port
t
w
V
7.0V
CC
Input pulse definition
INPUT PULSE REQUIREMENTS
R
U
V
V
OUT
IN
family
PULSE
GENERATOR
D.U.T.
V
Low V
74F amplitude
rep. rate
1MHz
t
t
t
M
w
TLH
THL
A port
B port
3.0V
3.0V
0.0V 1.5V
1.0V 1.5V
500ns 2.5ns 2.5ns
500ns 4.0ns 4.0ns
R
C
D
T
1MHz
Test circuit for outputs on B port
DEFINITIONS:
R
C
R
C
R
=
=
=
=
=
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Pull up resistor; see AC electrical characteristics for value.
L
L
U
D
T
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Termination resistance should be equal to Z
of pulse generators.
OUT
10
March 11, 1993
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