74HC05PW,118 [NXP]
74HC05 - Hex inverter with open-drain outputs TSSOP 14-Pin;
| 型号： | 74HC05PW,118 |
| 厂家： | 
NXP |
| 描述： | 74HC05 - Hex inverter with open-drain outputs TSSOP 14-Pin 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC05
Hex inverter with open-drain outputs
Rev. 02 — 18 June 2009
Product data sheet
1. General description
The 74HC05 is a high-speed Si-gate CMOS device that complies with JEDEC standard
no. 7A.
The 74HC05 contains six inverters.The outputs of the 74HC05 are open-drain and can be
connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH
wired-AND functions. The open-drain outputs require pull-up resistors to perform correctly.
2. Features
I Wide operating voltage 2.0 V to 6.0 V
I Input levels:
N For 74HC05: CMOS level
I Latch-up performance exceeds 100 mA per JESD 78 Class II level A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC05D
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HC05PW
74HC05BQ
TSSOP14
DHVQFN14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
4. Functional diagram
1
3
5
9
1A
2A
3A
4A
1Y
2Y
3Y
4Y
2
4
6
8
V
CC
11 5A
13 6A
5Y 10
6Y 12
Y
A
GND
mna525
001aaj979
Fig 1. Logic symbol
Fig 2. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
74HC05
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1Y
V
CC
6A
6Y
5A
5Y
4A
4Y
2A
2Y
3A
3Y
8
GND
001aaj980
Fig 3. Pin configuration SOT108-1 (SO14)
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
2 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
74HC05
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1Y
6A
6Y
5A
5Y
4A
74HC05
2A
2Y
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1Y
V
CC
6A
6Y
5A
5Y
4A
4Y
(1)
2A
GND
2Y
3A
3Y
001aak277
GND
8
Transparent top view
001aak276
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4. Pin configuration SOT402-1 (TSSOP14)
Fig 5. Pin configuration SOT762-1 (DHVQFN14)
5.2 Pin description
Table 2.
Symbol
1A to 6A
1Y to 6Y
GND
Pin description
Pin
Description
data input
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
data output
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nY
Z
H
L
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
-
Max
+7
Unit
V
supply voltage
[1]
[1]
[1]
input clamping current
output clamping current
output voltage
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
20
mA
mA
IOK
-
20
VO
−0.5
VCC + 0.5 V V
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
3 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
IO
Parameter
Conditions
Min
Max
25
Unit
mA
mA
mA
°C
output current
VO < VCC + 0.5 V
-
ICC
supply current
-
50
IGND
Tstg
ground current
storage temperature
total power dissipation
−50
−65
-
-
+150
500
[2]
Ptot
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
Parameter
Conditions
Min
Typ
Max
6.0
Unit
supply voltage
2.0
5.0
V
VI
input voltage
0
-
VCC
VCC
+125
625
139
83
V
VO
output voltage
0
-
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
-
°C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ
1.5 1.2
3.15 2.4
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Max Min Max
1.5 1.5
Max
VIH
HIGH-level
VCC = 2.0 V
-
-
-
-
-
-
-
V
V
V
V
V
V
input voltage
VCC = 4.5 V
-
3.15
3.15
VCC = 6.0 V
4.2
3.2
0.8
2.1
2.8
-
4.2
4.2
VIL
LOW-level
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
-
-
-
0.5
-
-
-
0.5
input voltage
VCC = 4.5 V
1.35
1.8
1.35
1.8
VCC = 6.0 V
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0.1
0.1
0.15 0.26
0.16 0.26
0.33
0.33
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
4 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
Min Typ
−40 °C to +85 °C −40 °C to +125 °C Unit
Max
Min
Max
Min
Max
II
input leakage
current
VI = VCC or GND;
-
-
0.1
-
1
-
1
µA
µA
V
CC = 6.0 V
IOZ
OFF-state
per input pin; VI = VIL;
-
-
0.5
-
5.0
-
10
output current VO = VCC or GND;
other inputs at VCC or GND;
CC = 6.0 V; IO = 0 A
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
-
2.0
-
-
-
20
-
-
-
40
-
µA
V
input
3.5
pF
capacitance
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter Conditions
25 °C
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Min
Typ
Max
tPLZ
tPZL
tTHL
CPD
LOW to OFF-state nA to nY; see Figure 6
propagation delay
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
20
11
10
90
18
15
115
23
135
27
ns
ns
ns
20
23
OFF-state to LOW nA to nY; see Figure 6
propagation delay
VCC = 2.0 V
-
-
-
22
9
90
18
15
115
23
135
27
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
8
20
23
HIGH to LOW
output transition
time
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
18
6
75
15
13
-
95
19
16
-
110
22
19
-
ns
ns
ns
pF
5
[1]
power dissipation per inverter; VI = GND to VCC
capacitance CC = 5.0 V
;
4
V
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(0.5 × CL × VO2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
VO = output voltage in V (output HIGH);
VCC = supply voltage in V;
N = number of inputs switching;
RL = load resistance in MΩ;
CL = load capacitance in pF;
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
5 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
11. Waveforms
V
I
nA input
GND
V
M
t
t
PZL
PLZ
V
CC
90 %
nY output
V
M
10 %
V
X
V
OL
t
THL
001aaj981
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. The input nA to output nY propagation delays and output transition times
Table 8.
Input
VM
Measurement points
Output
VM
VX
0.5VCC
0.5VCC
0.1VCC
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
6 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 7. Test circuit for measuring switching times
Table 9.
Input
VI
Test data
Load
CL
S1 position
tPZL, tPLZ
VCC
tr, tf
RL
VCC
6 ns
50 pF
1 kΩ
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
7 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 8. Package outline SOT108-1 (SO14)
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
8 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 9. Package outline SOT402-1 (TSSOP14)
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
9 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 10. Package outline SOT762-1 (DHVQFN14)
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
10 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
14. Revision history
Table 11. Revision history
Document ID
74HC05_2
Release date
20090618
Data sheet status
Change notice
Supersedes
Product data sheet
-
74HC05_1
Modifications:
• Added type numbers 74HC05PW (TSSOP14 package) and 74HC05BQ (DHVQFN14
package)
74HC05_1
20090427
Product data sheet
-
-
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
11 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC05_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 18 June 2009
12 of 13
74HC05
NXP Semiconductors
Hex inverter with open-drain outputs
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 June 2009
Document identifier: 74HC05_2
相关型号：
74HC05PW-Q100
HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14
NXP
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