74HC132DB,112 [NXP]
74HC(T)132 - Quad 2-input NAND Schmitt trigger SSOP1 14-Pin;
| 型号： | 74HC132DB,112 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)132 - Quad 2-input NAND Schmitt trigger SSOP1 14-Pin PC 光电二极管 逻辑集成电路 |
| 文件： | 总20页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
Rev. 3 — 30 August 2012
Product data sheet
1. General description
The 74HC132; 74HCT132 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A
The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt trigger inputs. This
device features reduced input threshold levels to allow interfacing to TTL logic levels.
Inputs also include clamp diodes that enable the use of current limiting resistors to
interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly
changing input signals into sharply defined jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
2. Features and benefits
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
4. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC132N
40 C to +125 C
40 C to +125 C
40 C to +125 C
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HCT132N
74HC132D
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT132D
74HC132DB
74HCT132DB
SSOP14
TSSOP14
plastic shrink small outline package; 14 leads; body SOT337-1
width 5.3 mm
74HC132PW 40 C to +125 C
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT132PW
5. Functional diagram
1A
1
1Y
3
1B
2
2A
4
1
2
2Y
6
&
&
&
&
3
6
2B
5
4
5
3A
9
3Y
8
3B
10
9
8
10
4A
12
A
B
12
13
4Y
11
11
Y
4B
13
mna407
mna408
mna409
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one
Schmitt trigger)
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
2 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
1A
1B
1
2
3
4
5
6
7
14 V
CC
13 4B
12 4A
11 4Y
10 3B
1Y
2A
132
2B
2Y
9
8
3A
3Y
GND
mna406
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
6.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
Pin description
Pin
Description
data input
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
data input
data output
ground (0 V)
supply voltage
VCC
14
7. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nB
L
nY
H
L
H
L
H
H
H
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
3 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
50
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
storage temperature
total power dissipation
DIP14 package
+150
[2]
-
-
750
500
mW
mW
SO14, and (T)SSOP14
packages
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC132
74HCT132
Unit
Min
2.0
0
Typ
Max
6.0
Min
4.5
0
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
5.0
5.0
V
-
VCC
VCC
+125
-
VCC
VCC
+125
V
VO
output voltage
ambient temperature
0
-
0
-
V
Tamb
40
+25
40
+25
C
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
4 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
74HC132
VOH
HIGH-level
VI = VT+ or VT
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VT+ or VT
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1.0
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
2.0
-
20
-
40
A
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT132
VOH HIGH-level
VI = VT+ or VT; VCC = 4.5 V
IO = 20 A
output voltage
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VT+ or VT; VCC = 4.5 V
IO = 20 A;
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 4.0 mA;
0.15 0.26
0.33
1.0
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
1.0
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
2.0
-
-
20
-
-
40
A
A
V
additional
per input pin;
30
108
135
147
supply current VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
V
CC = 4.5 V to 5.5 V
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
5 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 6.
Symbol Parameter
Conditions
25 C
40 C to +125 C Unit
Max Max
(85 C) (125 C)
Min
Typ
Max
74HC132
[1]
tpd
propagation delay nA, nB to nY; see Figure 5
VCC = 2.0 V
-
-
-
-
36
13
11
10
125
25
-
155
31
-
190
38
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
21
26
32
[2]
tt
transition time
see Figure 5
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
19
7
75
15
13
-
95
19
16
-
110
22
19
-
ns
ns
ns
pF
6
[3]
[1]
CPD
power dissipation per package; VI = GND to VCC
capacitance
24
74HCT132
tpd
propagation delay nA, nB to nY; see Figure 5
VCC = 4.5 V
-
-
-
-
20
17
7
33
-
41
-
50
-
ns
ns
ns
pF
VCC = 5.0 V; CL = 15 pF
VCC = 4.5 V; see Figure 5
[2]
[3]
tt
transition time
15
-
19
-
22
-
CPD
power dissipation per package;
capacitance VI = GND to VCC 1.5 V
20
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
6 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
12. Waveforms
V
I
nA, nB input
GND
V
M
t
t
PLH
PHL
V
OH
V
Y
V
nY output
M
V
X
V
OL
t
t
TLH
THL
001aai814
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Input to output propagation delays
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC132
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HCT132
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 6. Load circuitry for measuring switching times
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
7 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74HC132
VCC
3.0 V
6.0 ns
6.0 ns
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74HCT132
13. Transfer characteristics
Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 7 and Figure 8.
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C
to +85 C
Tamb = 40 C
to +125 C
Unit
Min Typ Max
Min
Max
Min
Max
74HC132
VT+
VT
VH
positive-going VCC = 2.0 V
0.7 1.18 1.5
1.7 2.38 3.15
2.1 3.14 4.2
0.3 0.63 1.0
0.9 1.67 2.2
1.2 2.26 3.0
0.2 0.55 1.0
0.4 0.71 1.4
0.6 0.88 1.6
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
1.5
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
1.5
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
V
V
V
V
V
V
V
V
V
threshold
voltage
VCC = 4.5 V
VCC = 6.0 V
negative-going VCC = 2.0 V
threshold
voltage
VCC = 4.5 V
VCC = 6.0 V
hysteresis
voltage
VCC = 2.0 V
CC = 4.5 V
VCC = 6.0 V
V
74HCT132
VT+
VT
VH
positive-going VCC = 4.5 V
1.2 1.41 1.9
1.4 1.59 2.1
1.2
1.4
1.9
2.1
1.2
1.4
1.9
2.1
V
V
threshold
voltage
VCC = 5.5 V
negative-going VCC = 4.5 V
0.5 0.85 1.2
0.6 0.99 1.4
0.5
0.6
1.2
1.4
0.5
0.6
1.2
1.4
V
V
threshold
voltage
VCC = 5.5 V
hysteresis
voltage
VCC = 4.5 V
VCC = 5.5 V
0.4 0.56
0.4 0.60
-
-
0.4
0.4
-
-
0.4
0.4
-
-
V
V
14. Transfer characteristics waveforms
V
O
V
T+
V
I
V
H
V
T−
V
I
V
V
O
H
V
V
T+
T−
mna207
mna208
Fig 7. Transfer characteristics
Fig 8. Transfer characteristics definitions
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
8 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
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a. VCC = 2.0 V
b. VCC = 4.5 V
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c. VCC = 6.0 V
Fig 9. Typical 74HC132 transfer characteristics
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
9 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
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a. VCC = 4.5 V
b. VCC = 5.5 V
Fig 10. Typical 74HCT132 transfer characteristics
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd = fi (tr ICC(AV) + tf ICC(AV)) VCC where:
Padd = additional power dissipation (W);
fi = input frequency (MHz);
tr = rise time (ns); 10 % to 90 %;
tf = fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (A).
Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 11
and Figure 12.
An example of a relaxation circuit using the 74HC132; 74HCT132 is shown in Figure 13.
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
10 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
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(1) Positive-going edge.
(2) Negative-going edge.
Fig 11. Average additional supply current as a function of VCC for 74HC132; linear change of VI between 0.1VCC
to 0.9VCC
.
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(1) Positive-going edge.
(2) Negative-going edge.
Fig 12. Average additional supply current as a function of VCC for 74HCT132; linear change of VI between 0.1VCC
to 0.9VCC
.
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
11 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
V
V
CC
CC
R
A
Y
B
C
001aac440
1
T
1
-- -----------------
For 74HC132 and 74HCT132: f =
K RC
For K-factor, see Figure 14
Fig 13. Relaxation oscillator
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ꢆꢎꢇ
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ꢈꢎꢋ
ꢈꢎꢆ
ꢆꢎꢋ
ꢆ
ꢆ
ꢇ
ꢉ
ꢊ
ꢋ
ꢏ
ꢊꢎꢋ
ꢋꢎꢆ
ꢋꢎꢋ
ꢀ
ꢃꢄꢀꢅ
ꢌꢌ
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ꢃꢄꢀꢅ
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K-factor for 74HC132
K-factor for 74HCT132
Fig 14. Typical K-factor for relaxation oscillator
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
12 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
16. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 15. Package outline SOT27-1 (DIP14)
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
13 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 16. Package outline SOT108-1 (SO14)
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
14 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
Fig 17. Package outline SOT337-1 (SSOP14)
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
15 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 18. Package outline SOT402-1 (TSSOP14)
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
16 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
17. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
TTL
Transistor-Transistor Logic
18. Revision history
Table 12. Revision history
Document ID
Release date
20120830
Data sheet status
Change notice
Supersedes
74HC_HCT132 v.3
Modifications:
Product data sheet
-
74HC_HCT132_CNV v.2
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Figure 14 added (typical K-factor for relaxation oscillator).
74HC_HCT132_CNV v.2 19970826
Product specification
-
-
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
17 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
19.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
18 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
19 of 20
74HC132; 74HCT132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
21. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Transfer characteristics . . . . . . . . . . . . . . . . . . 8
Transfer characteristics waveforms. . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
8
9
10
11
12
13
14
15
16
17
18
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
19.1
19.2
19.3
19.4
20
21
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 August 2012
Document identifier: 74HC_HCT132
相关型号：
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Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS
ONSEMI
74HC132DTR2G
Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS
ONSEMI
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