74HC165PW,118 [NXP]
74HC(T)165 - 8-bit parallel-in/serial-out shift register TSSOP 16-Pin;
| 型号： | 74HC165PW,118 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)165 - 8-bit parallel-in/serial-out shift register TSSOP 16-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总22页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 03 — 14 March 2008
Product data sheet
1. General description
The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with
complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
2. Features
I Asynchronous 8-bit parallel load
I Synchronous serial input
I Complies with JEDEC standard no. 7A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Applications
I Parallel-to-serial data conversion
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
4. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
plastic dual in-line package; 16 leads (300 mil)
Version
74HC165N
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
DIP16
SOT38-4
74HCT165N
74HC165D
SO16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT165D
74HC165DB
74HCT165DB
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads; body width SOT338-1
5.3 mm
74HC165PW −40 °C to +125 °C
74HCT165PW
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT403-1
74HC165BQ −40 °C to +125 °C
74HCT165BQ
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals; body
2.5 × 3.5 × 0.85 mm
5. Functional diagram
SRG8
1
C2[LOAD]
G1[SHIFT]
15
≥ 1
10
C3/
1
2
DS
11
D0
10
11
12
13
14
3
3D
2D
2D
12
D1
13
D2
14
D3
3
D4
4
D5
5
9
7
D6
D7
PL
Q7
Q7
4
6
1
5
9
7
CP CE
15
6
2
mna985
mna986
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
2 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
11 12 13 14 3
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1
PL
10 DS
Q7
Q7
9
7
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
2
CP
15 CE
mna992
Fig 3. Functional diagram
6. Pinning information
6.1 Pinning
74HC165
74HCT165
74HC165
74HCT165
terminal 1
index area
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PL
CP
V
CC
CE
D3
D2
D1
D0
DS
Q7
2
3
4
5
6
7
15
14
13
12
11
10
CP
CE
D3
D2
D1
D0
DS
D4
D4
D5
D6
D7
Q7
D5
D6
(1)
GND
D7
Q7
001aah565
GND
Transparent top view
001aah564
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 4. Pin configuration (DIP16, SO16
and (T)SSOP16)
Fig 5. Pin configuration (DHVQFN16)
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
3 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
6.2 Pin description
Table 2.
Symbol
PL
Pin description
Pin
Description
1
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
CP
2
Q7
7
GND
Q7
8
9
serial output from the last stage
serial data input
DS
10
D0 to D7
CE
11, 12, 13, 14, 3, 4, 5, 6
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
15
16
VCC
7. Functional description
Table 3.
Function table[1]
Operating modes Inputs
PL
Qn registers
Outputs
CE
X
X
L
CP
X
X
↑
DS
X
X
l
D0 to D7 Q0
Q1 to Q6 Q7
Q7
H
parallel load
L
L
L
L to L
L
L
H
X
X
X
X
X
X
H
L
H to H
H
L
serial shift
H
H
H
H
H
H
q0 to q5 q6
q0 to q5 q6
q0 to q5 q6
q0 to q5 q6
q1 to q6 q7
q1 to q6 q7
q6
q6
q6
q6
q7
q7
L
↑
h
H
L
↑
L
l
↑
L
h
H
q0
q0
hold “do nothing”
H
X
X
H
X
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
4 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
serial shift
mna993
load
Fig 6. Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
-
±20
±20
±25
50
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
ground current
−50
−65
-
storage temperature
+150
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
5 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
Conditions
Min
Max
Unit
Ptot
total power dissipation
Tamb = −40 °C to +125 °C
DIP16 package
[2]
[3]
[4]
[5]
-
-
-
-
750
500
500
500
mW
mW
mW
mW
SO16 package
(T)SSOP16 package
DHVQFN16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70 °C.
[3] Ptot derates linearly with 8 mW/K above 70 °C.
[4] Ptot derates linearly with 5.5 mW/K above 60 °C.
[5] Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC165
74HCT165
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
VCC
VCC
VO
output voltage
0
-
0
-
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
−40
-
−40
-
+125 °C
-
-
-
-
1.67
-
-
-
-
-
1.67
-
-
ns/V
139 ns/V
VCC = 6.0 V
-
ns/V
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC165
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
3.15 2.4
3.15
3.15
4.2
3.2
0.8
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
2.1 1.35
2.8 1.8
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
6 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = −4.0 mA; VCC = 4.5 V 3.98 4.32
IO = −5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND;
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1
V
V
II
input leakage
current
-
±0.1
8.0
-
µA
V
CC = 6.0 V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
-
-
-
80
-
-
-
160
-
µA
V
input
3.5
pF
capacitance
74HCT165
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = −4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND;
-
-
-
0
0.1
-
-
-
0.1
0.33
±1
-
-
-
0.1
0.4
±1
V
0.16 0.26
V
II
input leakage
current
-
±0.1
µA
V
CC = 6.0 V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
8.0
-
80
-
160
µA
V
additional
per input pin;
supply current VI = VCC − 2.1 V;
other inputs at VCC or GND;
CC = 4.5 V to 5.5 V
V
Dn and DS inputs
-
-
-
35
65
126
234
-
-
-
-
157.5
292.5
-
-
-
-
171.5 µA
318.5 µA
CP CE, and PL inputs
CI
input
3.5
-
pF
capacitance
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
7 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC165
[1]
tpd
propagation
delay
CP or CE to Q7, Q7;
see Figure 7
VCC = 2.0 V
-
-
-
-
52 165
-
-
-
-
205
41
35
-
-
-
-
-
250
50
43
-
ns
ns
ns
ns
VCC = 4.5 V
19
15
16
33
28
-
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
PL to Q7, Q7; see Figure 8
VCC = 2.0 V
-
-
-
-
50 165
-
-
-
-
205
41
35
-
-
-
-
-
250
50
43
-
ns
ns
ns
ns
VCC = 4.5 V
18
14
15
33
28
-
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
D7 to Q7, Q7; see Figure 9
VCC = 2.0 V
-
-
-
-
36 120
-
-
-
-
150
30
26
-
-
-
-
-
180
36
31
-
ns
ns
ns
ns
VCC = 4.5 V
13
10
11
24
20
-
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
Q7, Q7 output; see Figure 7
VCC = 2.0 V
[2]
tt
transition
time
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width
CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
PL input LOW; see Figure 8
VCC = 2.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
17
20
trec
recovery time PL to CP, CE; see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100 22
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
20
17
8
6
21
26
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
8 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
tsu
set-up time
DS to CP, CE; see Figure 10
VCC = 2.0 V
80
16
14
11
4
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
17
20
CE to CP and CP to CE;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
5
17
20
Dn to PL; see Figure 11
VCC = 2.0 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
th
hold time
DS to CP, CE and Dn to PL;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
5
5
5
6
2
2
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
CE to CP and CP to CE;
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
5
5
5
−17
−6
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 6.0 V
−5
fmax
maximum
frequency
CP input; see Figure 7
VCC = 2.0 V
6
30
35
-
17
51
61
56
35
-
-
-
-
-
5
24
28
-
-
-
-
-
-
4
20
24
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
[3]
CPD
power
per package;
-
-
-
dissipation
capacitance
VI = GND to VCC
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
9 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HCT165
[1]
tpd
propagation
delay
CE, CP to Q7, Q7;
see Figure 7
VCC = 4.5 V
-
-
17
14
34
-
-
-
43
-
-
-
51
-
ns
ns
VCC = 5.0 V; CL = 15 pF
PL to Q7, Q7; see Figure 8
VCC = 4.5 V
-
-
20
17
40
-
-
-
50
-
-
-
60
-
ns
ns
VCC = 5.0 V; CL = 15 pF
D7 to Q7, Q7; see Figure 9
VCC = 4.5 V
-
-
14
11
28
-
-
-
35
-
-
-
42
-
ns
ns
VCC = 5.0 V; CL = 15 pF
Q7, Q7 output; see Figure 7
VCC = 4.5 V
[2]
tt
transition
time
-
7
6
9
8
2
15
-
-
19
-
-
22
-
ns
ns
ns
ns
ns
tW
pulse width
CP input; see Figure 7
VCC = 4.5 V
16
20
20
20
20
25
25
25
24
30
30
30
PL input; see Figure 8
VCC = 4.5 V
-
-
-
trec
recovery time PL to CP, CE; see Figure 8
VCC = 4.5 V
-
-
-
tsu
set-up time
DS to CP, CE; see Figure 10
VCC = 4.5 V
-
-
-
CE to CP and CP to CE;
see Figure 10
VCC = 4.5 V
20
20
7
-
-
25
25
-
-
30
30
-
-
ns
ns
Dn to PL; see Figure 11
VCC = 4.5 V
10
th
hold time
DS to CP, CE and Dn to PL;
see Figure 10
VCC = 4.5 V
7
0
−1
−7
-
-
9
0
-
-
11
0
-
-
ns
ns
CE to CP and CP to CE;
see Figure 10
VCC = 4.5 V
fmax
maximum
frequency
CP input; see Figure 7
VCC = 4.5 V
26
-
44
48
-
-
21
-
-
-
17
-
-
-
MHz
MHz
VCC = 5.0 V; CL = 15 pF
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
10 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
[3]
CPD
power
per package;
-
35
-
-
-
-
-
pF
dissipation
capacitance
VI = GND to VCC − 1.5 V
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
1/f
max
V
I
CP or CE input
V
M
t
GND
t
W
t
PHL
PLH
V
OH
V
Q7 or Q7 output
M
V
OL
t
t
TLH
THL
mna987
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
11 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
V
I
V
PL input
M
GND
t
t
rec
W
V
I
CE, CP input
V
M
GND
t
PHL
V
OH
V
Q7 or Q7 output
M
V
OL
mna988
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel
load to clock (CP) and clock enable (CE) recovery time
V
I
V
D7 input
M
GND
t
t
t
t
PLH
PHL
PHL
PLH
V
OH
V
V
Q7 output
Q7 output
M
M
V
OL
V
OH
V
OL
mna989
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
12 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
(1)
V
V
I
CP, CE input
M
GND
t
t
h
h
t
t
su
su
V
I
V
DS input
M
GND
t
su
t
V
I
W
V
CP, CE input
M
GND
mna990
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
(1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1.
Fig 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs,
from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the
clock enable input (CE)
V
I
V
V
M
Dn input
GND
M
t
t
t
t
h
su
h
su
V
I
PL input
GND
V
V
M
M
mna991
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
Table 8.
Type
Measurement points
Input
Output
VM
VI
VM
74HC165
VCC
3 V
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT165
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
13 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC165
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT165
open
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
14 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 13. Package outline SOT38-4 (DIP16)
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
15 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 14. Package outline SOT109-1 (SO16)
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
16 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 15. Package outline SOT338-1 (SSOP16)
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
17 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 16. Package outline SOT403-1 (TSSOP16)
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
18 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 17. Package outline SOT763-1 (DHVQFN16)
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
19 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
74HC_HCT165_3
Modifications:
Release date
20080314
Data sheet status
Change notice
Supersedes
Product data sheet
-
74HC_HCT165_CNV_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Package SOT763-1 (DHVQFN16) added to Section 4 “Ordering information” and Section
13 “Package outline”.
• Family data added, see Section 10 “Static characteristics”
74HC_HCT165_CNV_2
December 1990 Product specification
-
-
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
20 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT165_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 14 March 2008
21 of 22
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 March 2008
Document identifier: 74HC_HCT165_3
相关型号：
74HC165PW-Q100
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
NXP
74HC165PW-T
IC HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16, Shift Register
NXP
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