74HC21D,653 [NXP]
74HC21 - Dual 4-input AND gate SOIC 14-Pin;
| 型号： | 74HC21D,653 |
| 厂家： | 
NXP |
| 描述： | 74HC21 - Dual 4-input AND gate SOIC 14-Pin |
| 文件： | 总14页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC21
Dual 4-input AND gate
Rev. 04 — 7 April 2009
Product data sheet
1. General description
The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL).
The 74HC21 provide the 4-input AND function.
2. Features
I Low-power dissipation
I Complies with JEDEC standard no. 7A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Multiple package options
I Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC21N
74HC21D
−40 °C to +125 °C
−40 °C to +125 °C
DIP14
SO14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
SOT108-1
plastic small outline package; 14 leads;
body width 3.9 mm
74HC21DB
−40 °C to +125 °C
−40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
SOT402-1
74HCT21PW
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74HC21
NXP Semiconductors
Dual 4-input AND gate
4. Functional diagram
1A
1
1A
1B
1C
1D
2A
2B
2C
2D
1
2
1B
2
4
1Y
6
8
1C
1D
2A
2B
2C
2D
1Y
6
4
5
5
9
9
10
12
13
2Y
10
12
13
2Y
8
001aab975
001aab973
Fig 1. Functional diagram
Fig 2. Logic symbol
&
1
2
4
5
6
8
A
B
C
&
9
Y
10
12
13
D
001aab974
001aab976
Fig 3. IEC Logic symbol
Fig 4. Logic diagram
5. Pinning information
5.1 Pinning
74HC21
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
74HC21
2D
2C
n.c.
2B
2A
2Y
1
2
3
4
5
6
7
14
V
1A
1B
CC
n.c.
1C
13
12
11
10
9
2D
2C
n.c.
2B
2A
2Y
n.c.
1C
1D
1D
1Y
1Y
8
GND
GND
8
001aab972
001aai659
Fig 5. Pin configuration SOT27-1 and SOT108-1
Fig 6. Pin configuration SOT337-1 and SOT402-1
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
2 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
5.2 Pin description
Table 2.
Symbol
1A, 1B, 1C, 1D
n.c.
Pin description
Pin
Description
data input
1, 2, 4, 5
3, 11
not connected
data output
ground (0 V)
data output
data input
1Y
6
GND
7
2Y
8
2A, 2B, 2C, 2D
VCC
9, 10, 12, 13
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nB
X
nC
X
nD
X
nY
L
X
L
X
X
L
X
X
L
X
L
X
X
X
L
L
H
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
-
±20
±20
±25
50
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−50
−65
-
storage temperature
total power dissipation
DIP14 package
+150
[2]
-
-
750
500
mW
mW
SO14 and (T)SSOP14
packages
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
3 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
Parameter
Conditions
Min
Typ
Max
6.0
Unit
V
supply voltage
input voltage
output voltage
2.0
5.0
VI
0
-
VCC
VCC
625
139
83
V
VO
0
-
V
∆t/∆V
input transition rise and fall VCC = 2.0 V
rate
-
-
ns/V
ns/V
ns/V
°C
VCC = 4.5 V
-
1.67
VCC = 6.0 V
-
-
-
Tamb
ambient temperature
−40
+125
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
1.5
3.15
4.2
-
Max
-
Min
1.5
3.15
4.2
-
Max
-
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15 2.4
-
-
VCC = 6.0 V
4.2
3.2
0.8
-
-
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.5
1.35
1.8
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
-
-
VCC = 6.0 V
2.8
1.8
-
-
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = −4.0 mA; VCC = 4.5 V 3.98 4.32
IO = −5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND;
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1
V
V
II
input leakage
current
-
±0.1
2.0
-
µA
V
CC = 6.0 V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
-
-
-
20
-
-
-
40
-
µA
V
input
3.5
pF
capacitance
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
4 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; test circuit see Figure 8.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
[1]
tpd
propagation
delay
nA, nB, nC or nD to nY;
see Figure 7
VCC = 2.0 V
-
-
-
-
33
12
10
10
110
22
19
-
-
-
-
-
140
28
24
-
-
-
-
-
165
33
28
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
[2]
[3]
tt
transition time nY output; see Figure 7
VCC = 2.0 V
-
-
-
-
19
7
75
15
13
-
-
-
-
-
95
19
16
-
-
-
-
-
110
22
19
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
6
CPD
power
VI = GND to VCC
15
dissipation
capacitance
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑ (CL × VCC2 × fo) = sum of outputs.
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
5 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
11. Waveforms
V
I
nA, nB, nC,
nD input
V
M
GND
t
t
PLH
PHL
V
V
OH
V
Y
nY output
M
V
X
V
OL
t
t
THL
TLH
001aab977
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output
transition times
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC21
0.5VCC
0.5VCC
0.1VCC
0.9VCC
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
6 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 8. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74HC21
VCC
6.0 ns
15 pF, 50 pF
tPLH, tPHL
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
7 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
12. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 9. Package outline SOT27-1 (DIP14)
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
8 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 10. Package outline SOT108-1 (SO14)
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
9 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
Fig 11. Package outline SOT337-1 (SSOP14)
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
10 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 12. Package outline SOT402-1 (TSSOP14)
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
11 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74HC21_4
Release date Data sheet status
20090407 Product data sheet
Change notice
Supersedes
74HC21_3
-
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74HC21PW (TSSOP14 package).
74HC21_3
20041112
19970828
19901201
Product data sheet
Product specification
Product specification
-
-
-
74HC_HCT21_CNV_2
74HC_HCT21_CNV_2
74HC_HCT21_1
74HC_HCT21_1
-
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
12 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC21_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 7 April 2009
13 of 14
74HC21
NXP Semiconductors
Dual 4-input AND gate
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 April 2009
Document identifier: 74HC21_4
相关型号：
74HC21D-T
IC HC/UH SERIES, DUAL 4-INPUT AND GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14, Gate
NXP
74HC21DB-T
IC HC/UH SERIES, DUAL 4-INPUT AND GATE, PDSO14, 5.30 MM, PLASTIC, MO-150, SOT337-1, SSOP-14, Gate
NXP
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