74HC237DB,118 [NXP]
74HC237 - 3-to-8 line decoder, demultiplexer with address latches SSOP1 16-Pin;型号: | 74HC237DB,118 |
厂家: | NXP |
描述: | 74HC237 - 3-to-8 line decoder, demultiplexer with address latches SSOP1 16-Pin |
文件: | 总17页 (文件大小:223K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC237
3-to-8 line decoder, demultiplexer with address latches
Rev. 6 — 23 August 2012
Product data sheet
1. General description
The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC
standard no. 7A.
The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address
inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit
storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present
at the inputs before this transition, is stored in the latches. Further address changes are
ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the
state of the outputs independent of the address inputs or latch operation. All outputs are
HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobed (stored address) applications in
bus-oriented systems.
2. Features and benefits
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active HIGH mutually exclusive outputs
Low-power dissipation
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC237N
74HC237D
40 C to +125 C
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
SOT109-1
40 C to +125 C
plastic small outline package; 16 leads; body width
3.9 mm
74HC237DB
40 C to +125 C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
4. Functional diagram
4
LE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
15
14
13
12
11
10
9
A0
A1
1
2
INPUT
LATCHES
3 TO 8
DECODER
3 A2
Y7 7
5 E1
6 E2
001aab871
Fig 1. Functional diagram
DX
4
1
2
3
15
14
13
12
11
10
9
C8
0
0
1
2
3
4
5
6
7
0
7
8D,G
4
2
LE
15
14
13
12
11
10
9
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
5
6
&
7
1
A0
2
3
INPUT
LATCHES
3 TO 8
DECODER
A1
A2
X/Y
4
1
2
3
15
14
13
12
11
10
9
C8
0
1
2
3
4
5
6
7
7
8D,1
8D,2
8D,4
E1
E2
5
6
001aab869
5
6
&
7
EN
001aab870
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC237
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
2 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
A1
A2
LE
LATCH
LATCH
LATCH
A0
LE
LE
LE
LE
A1
A1
LE
A2
A2
LE
E1
E2
001aab872
Fig 4. Logic diagram
5. Pinning information
5.1 Pinning
74HC237
1
2
3
4
5
6
7
8
16
V
A0
A1
CC
74HC237
15
14
13
12
11
10
9
Y0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A2
Y1
Y2
Y3
Y4
Y5
Y6
A0
A1
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
LE
A2
E1
LE
E1
E2
E2
Y7
Y7
GND
GND
001aab868
001aan382
Fig 5. Pin configuration DIP16 and SO16
Fig 6. Pin configuration SSOP16
74HC237
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
3 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
5.2 Pin description
Table 2.
Symbol
A0 to A2
LE
Pin description
Pin
Description
1, 2, 3
data input
4
5
6
latch enable input (active LOW)
data enable input 1 (active LOW)
data enable input 2 (active HIGH)
E1
E2
Y0 to Y7
GND
15, 14, 13, 12, 11, 10, 9, 7 output
8
ground (0 V)
VCC
16
supply voltage
6. Functional description
Table 3:
Function table
Input
Enable
Output
LE
H
X
E1
L
E2
H
X
A0
X
X
X
L
A1
X
X
X
L
A2
X
X
X
L
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
stable
H
X
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
X
L
L
L
H
H
L
L
L
H
H
L
L
H
L
L
H
H
H
H
H
L
L
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
25
+50
50
+150
750
500
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
65
[1]
[2]
DIP16 package
-
-
mW
mW
SO16 and SSOP16 packages
74HC237
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
4 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
VCC
Parameter
Conditions
Min
Typ
Max
6.0
Unit
V
supply voltage
2.0
5.0
VI
input voltage
0
-
VCC
VCC
+125
625
139
83
V
VO
output voltage
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
40
+25
C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
Min Typ Max
Tamb = 40 C to Tamb = 40 C to Unit
+85 C +125 C
Min
Max
-
Min
Max
-
VIH
HIGH-level
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
1.5
V
V
V
V
V
V
input voltage
VCC = 4.5 V
3.15
3.15
-
3.15
-
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
input voltage
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0.1
0.15 0.26
0.16 0.26
0.33
0.33
74HC237
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
5 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
Min Typ Max
Tamb = 40 C to Tamb = 40 C to Unit
+85 C +125 C
Min
Max
Min
Max
II
input leakage
current
VI = VCC or GND;
-
-
-
-
0.1
8.0
-
-
-
-
1.0
-
-
-
1.0
A
A
pF
VCC = 6.0 V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
80
-
160
-
input
3.5
capacitance
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions
Tamb = 25 C
Min Typ Max
Tamb = 40 C
to +85 C
Tamb = 40 C
to +125 C
Unit
Min
Max
Min
Max
[1]
tpd
propagation An to Yn; see Figure 7
delay
VCC = 2.0 V
-
-
-
-
52
19
16
15
160
32
-
-
-
-
-
200
40
-
-
-
-
-
240
48
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
27
34
41
[1]
LE to Yn; see Figure 7
VCC = 2.0 V
-
-
-
-
61
22
19
18
190
38
-
-
-
-
-
240
48
-
-
-
-
-
285
57
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
32
41
48
[1]
E1to Yn; see Figure 8
VCC = 2.0 V
-
-
-
-
47
17
14
14
145
29
-
-
-
-
-
180
36
-
-
-
-
-
220
44
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
25
31
38
[1]
E2 to Yn; see Figure 7
VCC = 2.0 V
-
-
-
-
47
17
14
14
145
29
-
-
-
-
-
180
36
-
-
-
-
-
220
44
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
25
31
38
[2]
tt
transition
time
Yn; see Figure 7 and
Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
6
19
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
6 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions
Tamb = 25 C
Min Typ Max
Tamb = 40 C
to +85 C
Tamb = 40 C
to +125 C
Unit
Min
Max
Min
Max
tW
pulse width LE HIGH; see Figure 9
VCC = 2.0 V
VCC = 4.5 V
50
10
9
11
4
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
VCC = 6.0 V
3
tsu
set-up time An to LE; see Figure 9
VCC = 2.0 V
50
10
9
6
2
2
-
-
-
65
13
11
-
-
-
-
-
-
-
-
75
15
13
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
th
hold time
An to LE; see Figure 9
VCC = 2.0 V
30
6
3
1
-
-
-
-
40
8
45
9
-
-
-
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
5
1
7
8
[3]
CPD
power
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
-
60
-
-
dissipation
capacitance
[1] tpd is the same as tPLH and tPHL
[2] tt is the same as tTHL and tTLH
[3] PD is used to determine the dynamic power dissipation (PD in W).
.
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
An, E2, LE
input
V
M
t
t
PLH
PHL
90 %
90 %
Yn output
V
M
10 %
10 %
t
t
THL
TLH
001aab873
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (An) and enable inputs (E2, LE) to output (Yn) and output transition time
74HC237
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
7 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
E1 input
V
M
t
t
PLH
PHL
90 %
90 %
Yn output
V
M
10 %
10 %
t
t
THL
TLH
001aab874
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Propagation enable inputs (E1) to output (Yn) and output transition time
An input
LE input
V
M
t
t
h
h
t
t
su
su
V
M
transparant
latched
transparant
latched
t
W
001aab875
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. The data input (An) to latch enable input (LE) set-up times, latch enable input (LE) to data input (An) hold
times and latch enable input (LE) pulse width
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC237
0.5VCC
0.5VCC
74HC237
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
8 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 10. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74HC237
VCC
6.0 ns
15 pF, 50 pF
tPLH, tPHL
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
9 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
12. Application information
strobe
decoder enable
X0
X1
X2
LE
A2 A1 A0
237
E2 E1
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
input
address
0
1
2
3
4
5
6
7
to five
other
decoders
X3
X4
X5
LE
A2 A1 A0
237
E2 E1
LE
A2 A1 A0
237
E2 E1
LE
A2 A1 A0
237
E2 E1
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
16 17 18 19 20 21 22 23
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
outputs
outputs
outputs
001aab876
Fig 11. 6-to-64 line decoder with input address storage
74HC237
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
10 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 12. Package outline SOT38-4 (DIP16)
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
11 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 13. Package outline SOT109-1 (SO16)
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
12 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 14. Package outline SOT338-1 (SSOP16)
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
13 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 11. Revision history
Document ID
74HC237 v.6
Release date Data sheet status
20120823 Product data sheet
Change notice
Supersedes
-
74HC237 v.5
Modifications:
• Measurement points added to Figure 7 and Figure 8 (errata).
74HC237 v.5
20111209
Product data sheet
-
74HC237 v.4
Modifications:
• Legal pages updated.
74HC237 v.4
20110110
20041112
19970828
19901201
Product data sheet
-
-
-
-
74HC237 v.3
74HC237 v.3
Product data sheet
Product specification
Product specification
74HC_HCT237_CNV v.2
74HC_HCT237 v.1
-
74HC_HCT237_CNV v.2
74HC_HCT237 v.1
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
14 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
15 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
16 of 17
74HC237
NXP Semiconductors
3-to-8 line decoder, demultiplexer with address latches
18. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application information. . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 August 2012
Document identifier: 74HC237
相关型号:
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