74HC240N [NXP]
Octal buffer/line driver; 3-state; inverting; 八路缓冲器/线路驱动器;三态;反相
| 型号： | 74HC240N |
| 厂家： | 
NXP |
| 描述： | Octal buffer/line driver; 3-state; inverting |
| 文件： | 总7页 (文件大小：48K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT240
Octal buffer/line driver; 3-state;
inverting
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state;
inverting
74HC/HCT240
FEATURES
GENERAL DESCRIPTION
• Output capability: bus driver
• ICC category: MSI
The 74HC/HCT240 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT240 are octal inverting buffer/line drivers
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high impedance
OFF-state. The “240” is identical to the “244” but has
inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
1An to 1Yn;
CL = 15 pF; VCC = 5 V
9
9
ns
2An to 2Yn
CI
input capacitance
3.5
30
3.5
30
pF
pF
CPD
power dissipation capacitance per buffer
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state; inverting
74HC/HCT240
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
1OE
output enable input (active LOW)
data inputs
2, 4, 6, 8
3, 5, 7, 9
10
1A0 to 1A3
2Y0 to 2Y3
GND
bus outputs
ground (0 V)
17, 15, 13, 11
18, 16, 14, 12
19
2A0 to 2A3
1Y0 to 1Y3
2OE
data inputs
bus outputs
output enable input (active LOW)
positive supply voltage
20
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state; inverting
74HC/HCT240
FUNCTION TABLE
INPUTS
OUTPUT
nYn
nOE
nAn
L
L
H
L
H
X
H
L
Z
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
Fig.4 Functional diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state; inverting
74HC/HCT240
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
1An to 1Yn;
30
11
9
100
20
17
125
25
21
150 ns
30
26
2.0 Fig.5
4.5
6.0
2An to 2Yn
t
t
t
PZH/ tPZL 3-state output enable time
1OE to 1Yn;
39
14
11
150
30
26
190
38
33
225 ns
45
38
2.0 Fig.6
4.5
6.0
2OE to 2Yn
PHZ/ tPLZ 3-state output disable time
1OE to 1Yn;
41
15
12
150
30
26
190
38
33
225 ns
45
38
2.0 Fig.6
4.5
6.0
2OE to 2Yn
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0 Fig.5
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state; inverting
74HC/HCT240
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
IICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
1An
UNIT LOAD COEFFICIENT
1.50
2An
1OE
2OE
1.50
0.70
0.70
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
1An to 1Yn;
11 20
13 30
13 25
25
38
31
15
30
45
38
18
ns
ns
ns
ns
4.5 Fig.5
2An to 2Yn
t
t
t
PZH/ tPZL 3-state output enable time
1OE to 1Yn;
4.5 Fig.6
4.5 Fig.6
4.5 Fig.5
2OE to 2Yn
PHZ/ tPLZ 3-state output disable time
1OE to 1Yn;
2OE to 2Yn
THL/ tTLH output transition time
5
12
December 1990
6
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state; inverting
74HC/HCT240
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.5 Waveforms showing the input (1An, 2An) to output (1Yn, 2Yn) propagation delays and the output transition
times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the 3-state enable and disable times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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