74HC273DB-T [NXP]
IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 5.30 MM, PLASTIC, MO-150, SOT-339-1, SSOP-20, FF/Latch;
| 型号： | 74HC273DB-T |
| 厂家： | 
NXP |
| 描述： | IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 5.30 MM, PLASTIC, MO-150, SOT-339-1, SSOP-20, FF/Latch 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总26页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 03 — 24 January 2006
Product data sheet
1. General description
The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC273; 74HCT273 has eight edge-triggered, D-type flip-flops with individual
D inputs and Q outputs. The common clock (pin CP) and master reset (pin MR) inputs
load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up
time before the LOW-to-HIGH clock transition, is transferred to the corresponding output
(Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or data inputs by a LOW voltage
level on the MR input.
The device is useful for applications where the true output only is required and the clock
and master reset are common to all storage elements.
2. Features
■ Ideal buffer for MOS microprocessor or memory
■ Common clock and master reset
■ Eight positive edge-triggered D-type flip-flops
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM EIA/JESD22-A114-C exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
74HC273
Conditions
Min
Typ
Max
Unit
tPHL
tPLH
,
propagation delay CP to Qn VCC = 5 V; CL = 15 pF
-
-
-
15
15
66
-
-
-
ns
tPHL
HIGH-to-LOW propagation
delay MR to Qn
VCC = 5 V; CL = 15 pF
VCC = 5 V; CL = 15 pF
ns
fmax
maximum input clock
frequency
MHz
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 1:
Quick reference data …continued
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
Conditions
Min
Typ
3.5
20
Max
Unit
pF
Ci
input capacitance
-
-
-
-
[1]
CPD
power dissipation
capacitance
per flip-flop; VI = GND
to VCC
pF
74HCT273
tPHL propagation delay CP to Qn VCC = 5 V; CL = 15 pF
tPLH
,
-
-
-
15
20
36
-
-
-
ns
tPHL
fmax
Ci
HIGH-to-LOW propagation
delay MR to Qn
VCC = 5 V; CL = 15 pF
ns
maximum input clock
frequency
VCC = 5 V; CL = 15 pF
MHz
input capacitance
-
-
3.5
23
-
-
pF
pF
[1]
CPD
power dissipation
capacitance
per flip-flop; VI = GND
to (VCC − 1.5 V)
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Type number Package
Temperature range Name
Description
Version
74HC273
74HC273N
74HC273D
74HC273DB
−40 °C to +125 °C
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
−40 °C to +125 °C
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
SSOP20
plastic shrink small outline package; 20 leads; body width SOT339-1
5.3 mm
74HC273PW −40 °C to +125 °C
TSSOP20
plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
SOT360-1
74HC273BQ
−40 °C to +125 °C
DHVQFN20 plastic dual in-line compatible thermal enhanced very thin SOT764-1
quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
74HCT273
74HCT273N
74HCT273D
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
2 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 2:
Ordering information …continued
Type number Package
Temperature range Name
Description
Version
74HCT273DB −40 °C to +125 °C
74HCT273PW −40 °C to +125 °C
74HCT273BQ −40 °C to +125 °C
SSOP20
plastic shrink small outline package; 20 leads; body width SOT339-1
5.3 mm
TSSOP20
plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
SOT360-1
DHVQFN20 plastic dual in-line compatible thermal enhanced very thin SOT764-1
quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
5. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
2
5
7
6
FF1
TO
FF8
8
9
13
14
17
18
12
15
16
19
MR
CP
1
11
001aae055
Fig 1. Functional diagram
11
1
CP
C1
R
MR
11
CP
3
2
1D
D0
Q0
3
4
2
5
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
D1
D2
D3
D4
D5
D6
D7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
7
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
MR
1
mna764
mna763
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
3 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
D0
D1
D2
D3
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
FF1
FF2
FF3
FF4
R
R
R
R
D
D
D
D
CP
MR
Q0
Q1
Q2
Q3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
CP
FF5
CP
FF6
CP
FF7
CP
FF8
R
R
R
R
D
D
D
D
Q4
Q5
Q6
Q7
001aae056
Fig 4. Logic diagram
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
4 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
6. Pinning information
6.1 Pinning
74HC273
74HCT273
terminal 1
index area
74HC273
74HCT273
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
1
20
19
18
17
16
15
14
13
12
11
MR
Q0
V
CC
2
3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
D0
4
D1
5
Q1
(1)
6
GND
Q2
7
D2
8
D3
9
Q3
001aae054
10
GND
001aae053
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or output.
Fig 5. Pin configuration DIP20, SO20,
SSOP20 and TSSOP20
Fig 6. Pin configuration DHVQFN20
6.2 Pin description
Table 3:
Pin description
Symbol
MR
Q0
Pin
1
Description
master reset input (active LOW)
flip-flop output 0
data input 0
2
D0
3
D1
4
data input 1
Q1
5
flip-flop output 1
flip-flop output 2
data input 2
Q2
6
D2
7
D3
8
data input 3
Q3
9
flip-flop output 3
ground (0 V)
GND
CP
10
11
12
13
14
clock input (LOW-to-HIGH, edge-triggered)
flip-flop output 4
data input 4
Q4
D4
D5
data input 5
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
5 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 3:
Symbol
Q5
Pin description …continued
Pin
15
16
17
18
19
20
Description
flip-flop output 5
flip-flop output 6
data input 6
Q6
D6
D7
data input 7
Q7
flip-flop output 7
supply voltage
VCC
7. Functional description
7.1 Function table
Table 4:
Function table[1]
Operating
modes
Control
Input
Output
MR
L
CP
X
Dn
X
h
Qn
L
Reset (clear)
Load 1
H
↑
H
Load 0
H
↑
I
L
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑ = LOW-to-HIGH transition;
X = don’t care.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7
Unit
V
VCC
IIK
supply voltage
−0.5
input clamping current VI < −0.5 V or VI > VCC + 0.5 V
-
-
±20
±20
mA
mA
IOK
output clamping current VO < −0.5 V or VO >
VCC + 0.5 V
IO
output current
VO = −0.5 V to (VCC + 0.5 V)
-
-
±25
mA
mA
ICC
quiescent supply
current
50
IGND
Tstg
ground current
-
−50
mA
storage temperature
−65
+150 °C
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
6 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 5:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Ptot total power dissipation
Conditions
Min
Max
Unit
[1]
[2]
[3]
[3]
[4]
DIP20 package
-
-
-
-
-
750
500
500
500
500
mW
mW
mW
mW
mW
SO20 package
SSOP20 package
TSSOP20 package
DHVQFN20 package
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO20 package: Ptot derates linearly with 8 mW/K above 70 °C.
[3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] For DHVQFN20 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol Parameter
74HC273
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.0
5.0
6.0
V
input voltage
0
-
VCC
VCC
+125
1000
500
400
V
VO
output voltage
0
-
V
Tamb
tr, tf
ambient temperature
input rise and fall time
−40
+25
°C
ns
ns
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
6.0
-
74HCT273
VCC
supply voltage
4.5
0
5.0
-
5.5
V
VI
input voltage
VCC
VCC
+125
500
V
VO
output voltage
0
-
V
Tamb
tr, tf
ambient temperature
input rise and fall time
−40
-
+25
6.0
°C
ns
VCC = 4.5 V
10. Static characteristics
Table 7:
Static characteristics 74HC273
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-state input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
2.4
3.2
-
-
-
V
V
V
3.15
4.2
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
7 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 7:
Static characteristics 74HC273 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
0.8
2.1
2.8
Max
0.5
Unit
V
VIL
LOW-state input voltage
VCC = 2.0 V
-
-
-
VCC = 4.5 V
1.35
1.8
V
VCC = 6.0 V
V
VOH
HIGH-state output voltage
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4.0 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
2.0
-
-
-
-
-
V
V
V
V
V
4.4
4.5
5.9
6.0
3.98
5.48
4.32
5.81
VOL
LOW-state output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VIH or VIL; VO = VCC or GND;
-
-
-
-
-
-
-
0
0.1
V
0
0.1
V
0
0.1
V
0.15
0.26
0.26
±0.1
±0.5
V
0.16
V
ILI
input leakage current
-
-
µA
µA
IOZ
OFF-state output current
V
CC = 6.0 V
VI = VCC or GND; IO = 0 A;
CC = 6.0 V
ICC
Ci
quiescent supply current
input capacitance
-
-
-
8.0
-
µA
V
3.5
pF
Tamb = −40 °C to +85 °C
VIH HIGH-state input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4.0 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
4.4
5.9
3.84
5.34
VOL
LOW-state output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.1
V
0.1
V
0.33
0.33
±1.0
V
V
ILI
input leakage current
µA
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
8 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 7:
Static characteristics 74HC273 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND;
-
-
±5.0
µA
V
CC = 6.0 V
VI = VCC or GND; IO = 0 A;
CC = 6.0 V
ICC
quiescent supply current
-
-
80
µA
V
Tamb = −40 °C to +125 °C
VIH HIGH-state input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4.0 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
VOL
LOW-state output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VIH or VIL; VO = VCC or GND;
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
V
V
V
V
V
ILI
input leakage current
µA
IOZ
OFF-state output current
±10.0 µA
V
CC = 6.0 V
VI = VCC or GND; IO = 0 A;
CC = 6.0 V
ICC
quiescent supply current
-
-
160
µA
V
Table 8:
Static characteristics 74HCT273
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
VIL
HIGH-state input voltage
LOW-state input voltage
HIGH-state output voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
2.0
-
1.6
1.2
-
V
V
0.8
VOH
4.4
4.5
-
-
V
V
IO = −4.0 mA
3.98
4.32
VOL
LOW-state output voltage
input leakage current
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
0
0.1
V
IO = 4.0 mA
0.15
-
0.26
±0.1
V
ILI
VI = VCC or GND; VCC = 5.5 V
µA
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
9 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 8:
Static characteristics 74HCT273 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
-
-
±0.5
µA
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
8.0
µA
V
CC = 5.5 V
VI = VCC − 2.1 V; other inputs at
CC or GND; VCC = 4.5 V to 5.5 V;
∆ICC
additional quiescent supply
current
V
IO = 0 A
pin MR
pin CP
-
-
-
-
100
175
15
360
630
54
-
µA
µA
µA
pF
pin Dn
Ci
input capacitance
3.5
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH-state input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
2.0
-
-
-
-
V
V
LOW-state input voltage
HIGH-state output voltage
0.8
VOH
4.4
-
-
-
-
V
V
IO = −4.0 mA
3.84
VOL
LOW-state output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
-
-
-
-
-
0.1
V
IO = 4.0 mA
0.33
±1.0
±5.0
V
ILI
input leakage current
VI = VCC or GND; VCC = 5.5 V
µA
µA
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
80
µA
V
CC = 5.5 V
VI = VCC − 2.1 V; other inputs at
CC or GND; VCC = 4.5 V to 5.5 V;
∆ICC
additional quiescent supply
current
V
IO = 0 A
pin MR
pin CP
pin Dn
-
-
-
-
-
-
450
µA
787.5 µA
67.5
µA
Tamb = −40 °C to +125 °C
VIH
VIL
HIGH-state input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
2.0
-
-
-
-
V
V
LOW-state input voltage
HIGH-state output voltage
0.8
VOH
4.4
3.7
-
-
-
-
V
V
IO = −4.0 mA
VOL
LOW-state output voltage
input leakage current
VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
-
-
-
-
-
-
0.1
V
IO = 4.0 mA
0.4
V
ILI
VI = VCC or GND; VCC = 5.5 V
±1.0
µA
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
10 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 8:
Static characteristics 74HCT273 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
-
-
±10
µA
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
160
µA
V
CC = 5.5 V
VI = VCC − 2.1 V; other inputs at
CC or GND; VCC = 4.5 V to 5.5 V;
IO = 0 A
∆ICC
additional quiescent supply
current
V
pin MR
pin CP
pin Dn
-
-
-
-
-
-
490
µA
857.5 µA
73.5 µA
11. Dynamic characteristics
Table 9:
Dynamic characteristics 74HC273
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL
tPLH
,
propagation delay CP to Qn
see Figure 7
VCC = 2.0 V
-
-
-
-
41
15
15
13
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
tPHL
HIGH-to-LOW propagation delay see Figure 8
MR to Qn
VCC = 2.0 V
-
-
-
-
44
16
15
14
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
26
tTHL
,
output transition time
tTLH
-
-
-
19
7
75
15
13
ns
ns
ns
6
tW
pulse width
clock HIGH or LOW
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
14
5
-
-
-
ns
ns
ns
4
master reset LOW
60
12
10
17
6
-
-
-
ns
ns
ns
5
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
11 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics 74HC273 …continued
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
trec recovery time MR to CP
Conditions
Min
Typ
Max
Unit
see Figure 8
VCC = 2.0 V
+50
+10
+9
−6
−2
−2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
tsu
set-up time Dn to CP
see Figure 9
VCC = 2.0 V
60
12
10
11
4
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
th
hold time Dn to CP
see Figure 9
VCC = 2.0 V
+3
+3
+3
−6
−2
−2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum input clock frequency
see Figure 7
VCC = 2.0 V
6.0
30
-
20.6
103
66
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
35
-
122
20
[1]
CPD
power dissipation capacitance
per flip-flop; VI = GND to VCC
Tamb = −40 °C to +85 °C
tPHL propagation delay CP to Qn
tPLH
,
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
185
37
ns
ns
ns
31
tPHL
HIGH-to-LOW propagation delay see Figure 8
MR to Qn
VCC = 2.0 V
-
-
-
-
-
-
185
37
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
31
tTHL
tTLH
,
output transition time
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
95
19
15
ns
ns
ns
tW
pulse width
clock HIGH or LOW
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
-
-
-
-
-
-
ns
ns
ns
17
master reset LOW
75
15
13
-
-
-
-
-
-
ns
ns
ns
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
12 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics 74HC273 …continued
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
trec recovery time MR to CP
Conditions
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
65
13
11
-
-
-
-
-
-
ns
ns
ns
tsu
set-up time Dn to CP
75
15
13
-
-
-
-
-
-
ns
ns
ns
th
hold time Dn to CP
3
3
3
-
-
-
-
-
-
ns
ns
ns
fmax
maximum input clock frequency
4.8
24
28
-
-
-
-
-
-
MHz
MHz
MHz
Tamb = −40 °C to +125 °C
tPHL propagation delay CP to Qn
tPLH
,
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
38
tPHL
HIGH-to-LOW propagation delay see Figure 8
MR to Qn
VCC = 2.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
38
tTHL
tTLH
,
output transition time
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
110
22
ns
ns
ns
19
tW
pulse width
clock HIGH or LOW
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
120
24
-
-
-
-
-
-
ns
ns
ns
20
master reset LOW
90
18
15
-
-
-
-
-
-
ns
ns
ns
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
13 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 9:
Dynamic characteristics 74HC273 …continued
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
trec recovery time MR to CP
Conditions
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
75
15
13
-
-
-
-
-
-
ns
ns
ns
tsu
set-up time Dn to CP
90
18
15
-
-
-
-
-
-
ns
ns
ns
th
hold time Dn to CP
3
3
3
-
-
-
-
-
-
ns
ns
ns
fmax
maximum input clock frequency
4.0
20
24
-
-
-
-
-
-
MHz
MHz
MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
Table 10: Dynamic characteristics 74HCT273
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL
tPLH
,
propagation delay CP to Qn
see Figure 7
VCC = 4.5 V
-
-
16
15
30
-
ns
ns
VCC = 5 V; CL = 15 pF
tPHL
HIGH-to-LOW propagation delay see Figure 8
MR to Qn
VCC = 4.5 V
-
-
-
23
20
7
34
-
ns
ns
ns
VCC = 5 V; CL = 15 pF
tTHL
,
output transition time
VCC = 4.5 V; see Figure 7
15
tTLH
tW
pulse width
clock HIGH or LOW
master reset LOW
VCC = 4.5 V; see Figure 7
VCC = 4.5 V; see Figure 8
16
16
9
8
-
-
ns
ns
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
14 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
Table 10: Dynamic characteristics 74HCT273 …continued
Voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF unless otherwise specified; for test circuit see
Figure 10.
Symbol Parameter
trec recovery time MR to CP
tsu
Conditions
Min
+10
12
Typ
−2
5
Max
Unit
ns
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 9
see Figure 7
-
-
-
set-up time Dn to CP
ns
th
hold time Dn to CP
+3
−4
ns
fmax
maximum input clock frequency
VCC = 4.5 V
30
-
56
36
23
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
per flip-flop; VI = GND to (VCC − 1.5 V)
[1]
CPD
power dissipation capacitance
-
Tamb = −40 °C to +85 °C
tPHL propagation delay CP to Qn
tPLH
,
VCC = 4.5 V; see Figure 7
-
-
-
-
-
-
38
43
19
ns
ns
ns
tPHL
HIGH-to-LOW propagation delay VCC = 4.5 V; see Figure 8
MR to Qn
tTHL
,
output transition time
VCC = 4.5 V; see Figure 7
tTLH
tW
pulse width
clock HIGH or LOW
master reset LOW
VCC = 4.5 V; see Figure 7
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 7
20
20
13
15
3
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
trec
tsu
recovery time MR to CP
set-up time Dn to CP
hold time Dn to CP
maximum input clock frequency
ns
ns
th
ns
fmax
24
MHz
Tamb = −40 °C to +125 °C
tPHL propagation delay CP to Qn
tPLH
,
VCC = 4.5 V; see Figure 7
-
-
-
-
-
-
45
51
22
ns
ns
ns
tPHL
HIGH-to-LOW propagation delay VCC = 4.5 V; see Figure 8
MR to Qn
tTHL
,
output transition time
VCC = 4.5 V; see Figure 7
tTLH
tW
pulse width
clock HIGH or LOW
master reset LOW
VCC = 4.5 V; see Figure 7
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 7
24
24
15
18
3
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
trec
tsu
recovery time MR to CP
set-up time Dn to CP
hold time Dn to CP
maximum input clock frequency
ns
ns
th
ns
fmax
20
MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
15 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
∑(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
1/f
max
V
I
CP input
V
t
V
t
M
M
GND
t
t
W
W
PHL
PLH
V
OH
90%
V
Qn output
M
10%
V
OL
t
t
TLH
001aae062
THL
Measurement points are given in Table 11.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 7. Propagation delay clock input (CP) to output (Qn), clock (CP) pulse width, output
transition time and the maximum clock pulse frequency
V
I
V
MR input
M
GND
t
t
rec
W
V
I
CP input
V
M
GND
t
PHL
V
Qn output
M
mna464
Measurement points are given in Table 11.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 8. Propagation delay master reset (MR) to output (Qn), pulse width master reset (MR)
and recovery time master reset (MR) to clock (CP)
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
16 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
V
I
V
M
CP input
GND
t
t
su
su
t
t
h
h
V
I
V
Dn input
M
GND
V
OH
V
Qn output
M
V
OL
mna767
Measurement points are given in Table 11.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 9. Data set-up and hold times data input (Dn)
Table 11: Measurement points
Type
Input
VM
Output
VM
74HC273
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT273
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
17 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
t
W
V
I
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
PULSE
GENERATOR
open
DUT
R
T
C
L
001aad983
Test data is given in Table 12.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 10. Load circuitry for measuring switching times
Table 12: Test data
Type
Input
VI
Load
CL
S1 position
tr, tf
6 ns
6 ns
RL
tPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC273
VCC
3 V
15 pF, 50 pF 1 kΩ
15 pF, 50 pF 1 kΩ
open
open
GND
GND
VCC
VCC
74HCT273
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
18 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
13. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 11. Package outline SOT146-1 (DIP20)
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
19 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 12. Package outline SOT163-1 (SO20)
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
20 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 13. Package outline SOT339-1 (SSOP20)
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
21 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 14. Package outline SOT360-1 (TSSOP20)
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
22 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 15. Package outline SOT764-1 (DHVQFN20)
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
23 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
14. Abbreviations
Table 13: Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
MOS
Metal Oxide Semiconductor
15. Revision history
Table 14: Revision history
Document ID
74HC_HCT273_3
Modifications:
Release date Data sheet status Change notice Doc. number Supersedes
20060124 Product data sheet 74HC_HCT273_CNV_2
-
-
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Section 4 “Ordering information”, Section 6 “Pinning information” and Section 13 “Package
outline”: Added DHVQFN package information
• Section 10 “Static characteristics”: Added from the family specification
74HC_HCT273_CNV_2 19970827
Product
-
-
-
specification
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
24 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
16. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
17. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
19. Trademarks
Notice — All referenced brands, product names, service names and
18. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
20. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
25 of 26
74HC273; 74HCT273
Philips Semiconductors
Octal D-type flip-flop with reset; positive-edge trigger
21. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 6
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contact information . . . . . . . . . . . . . . . . . . . . 25
9
10
11
12
13
14
15
16
17
18
19
20
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 24 January 2006
Document number: 74HC_HCT273_3
Published in The Netherlands
相关型号：
74HC273PW-Q100J
74HC(T)273-Q100 - Octal D-type flip-flop with reset; positive-edge trigger TSSOP2 20-Pin
NXP
74HC273PW-T
IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20, FF/Latch
NXP
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