74HC299PW-T [NXP]
IC HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP1-20, Shift Register;
| 型号： | 74HC299PW-T |
| 厂家： | 
NXP |
| 描述： | IC HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP1-20, Shift Register 光电二极管 输出元件 |
| 文件： | 总24页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC299; 74HCT299
8-bit universal shift register; 3-state
Rev. 03 — 28 July 2008
Product data sheet
1. General description
The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are
pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified in
compliance with JEDEC standard no. 7A.
The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and
hold operations. An operation is determined by the mode select inputs S0 and S1, as
shown in Table 3.
Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data
inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in
serial shifting of longer words.
A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP
inputs and resets the flip-flops. All other state changes are initiated by the rising edge of
the clock pulse. Inputs can change when the clock is in either state, provided that the
recommended set-up and hold times are observed.
A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state
buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,
the shift, hold, load and reset operations still occur when preparing for a parallel load
operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.
2. Features
I Multiplexed inputs/outputs provide improved bit density
I Four operating modes:
N Shift left
N Shift right
N Hold (store)
N Load data
I Operates with output enable or at high-impedance OFF-state (Z)
I 3-state outputs drive bus lines directly
I Cascadable for n-bit word lengths
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74HC299
74HC299D
−40 °C to +125 °C
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads; body
width 7.5 mm
SOT163-1
SOT339-1
SOT146-1
74HC299DB
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
74HC299N
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
plastic dual in-line package; 20 leads (300 mil)
74HC299PW
TSSOP20
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
74HCT299
74HCT299D
−40 °C to +125 °C
−40 °C to +125 °C
SO20
plastic small outline package; 20 leads; body
width 7.5 mm
SOT163-1
SOT339-1
SOT146-1
74HCT299DB
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
74HCT299N
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
plastic dual in-line package; 20 leads (300 mil)
74HCT299PW
TSSOP20
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
4. Functional diagram
1
19
S1
S0
DSL
Q7
DSR
11
12
18
17
CP
MR
Q0
8-BIT SHIFT REGISTER
9
8
OE1
OE2
2
3
INPUT/3-STATE OUTPUT CIRCUITRY
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
7
13
6
14
5
15
4
16
001aai460
Fig 1. Functional diagram
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
2 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
9
2
3
R
SRG8
3EN5
&
1
19
12
0
1
0
3
M
C4/1 /2
11
7
1, 4D
3, 4D
1
19
11
18
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Q0
7
S0
8
Z6
S1
13
6
6, 5
13
DSR
DSL
3, 4D
5
14
5
6
14
5
12
9
15
4
CP
15
4
MR
16
8
16
2
3
3, 4D
7, 5 Z7
2, 4D
OE
17
18
Q7
17
001aai458
001aai459
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
3 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
DSR
S0
D
S1
Q
I/O0
CP
FF0
RD
CP
Q0
D
OE1
Q
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CP
FF1
RD
OE2
D
Q
CP
FF2
RD
D
Q
CP
FF3
RD
D
Q
CP
FF4
RD
D
Q
CP
FF5
RD
D
Q
CP
FF6
RD
DSL
D
Q
CP
FF7
RD
Q7
001aai461
MR
Fig 4. Logic diagram
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
4 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
5. Pinning information
5.1 Pinning
74HC299
74HCT299
1
2
20
19
18
17
16
15
14
13
12
11
S0
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
V
CC
74HC299
74HCT299
S1
3
DSL
Q7
1
2
20
19
18
17
16
15
14
13
12
11
S0
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
V
CC
4
S1
5
I/O7
I/O5
I/O3
I/O1
CP
3
DSL
Q7
4
6
5
I/O7
I/O5
I/O3
I/O1
CP
7
6
8
7
8
9
MR
9
MR
10
GND
DSR
10
GND
DSR
001aai511
001aai457
Fig 5. Pin configuration (SO20 and (T)SSOP20)
Fig 6. Pin configuration (DIP20)
5.2 Pin description
Table 2.
Symbol
S0
Pin description
Pin
1
Description
mode select input
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
2
3-state output enable input (active LOW)
3-state output enable input (active LOW)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
serial output (standard output)
3
4
5
6
7
8
MR
9
asynchronous master reset input (active LOW)
ground (0 V)
GND
DSR
CP
10
11
12
13
14
15
16
17
serial data shift-right input
clock input (LOW to HIGH, edge-triggered)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
serial output (standard output)
I/O1
I/O3
I/O5
I/O7
Q7
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
5 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
Table 2.
Symbol
DSL
Pin description …continued
Pin
18
19
20
Description
serial data shift-left input
mode select input
S1
VCC
positive supply voltage
6. Functional description
Table 3.
Function table[1]
Input
MR
L
Response
S1
X
S0
X
CP
X
↑
asynchronous reset; Q0 to Q7 = LOW
H
H
L
H
H
L
parallel load; I/On → Qn
shift right; DSR → Q0, Q0 → Q1, etc.
shift left; DSL → Q7, Q7 → Q6, etc.
hold
H
↑
H
H
L
↑
H
L
X
[1] H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW to HIGH CP transition;
X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
-
-
±20
±20
mA
mA
IOK
IO
standard outputs
bus driver outputs
supply current
-
-
±25
±35
mA
mA
ICC
standard outputs
bus driver outputs
ground current
-
-
50
70
mA
mA
IGND
standard outputs
bus driver outputs
storage temperature
total power dissipation
−50
−70
−65
-
mA
mA
°C
-
Tstg
Ptot
+150
Tamb = −40 °C to +125 °C
DIP20 package
[2]
[3]
[4]
-
-
-
750
500
500
mW
mW
mW
SO20 package
(T)SSOP20 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
6 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
[2] Ptot derates linearly at 12 mW/K above 70 °C.
[3] Ptot derates linearly at 8 mW/K above 70 °C.
[4] Ptot derates linearly at 5.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
74HC299
74HCT299
Unit
Min Typ Max Min Typ Max
VCC
VI
supply voltage
2.0
0
5.0
6.0
4.5
0
5.0
5.5
V
V
V
input voltage
-
-
-
VCC
VCC
-
-
-
VCC
VCC
VO
output voltage
0
0
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
+125 −40
+125 °C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
625
-
-
-
-
-
ns/V
1.67 139
83
1.67 1.39 ns/V
-
-
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to
+85 °C
−40 °C to
+125 °C
Unit
Min
Typ
Max
Min
Max
Min
Max
74HC299
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
3.15
3.15
3.15
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
7 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to
+85 °C
−40 °C to
+125 °C
Unit
Min
Typ
Max
Min
Max
Min
Max
VOH
HIGH-level
VI = VIH or VIL
output voltage
all outputs
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
standard outputs
IO = −4.0 mA;
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
1.9
4.4
5.9
-
-
-
1.9
4.4
5.9
-
-
-
V
V
V
3.98 4.32
5.48 5.81
-
-
3.84
5.34
-
-
3.7
5.2
-
-
V
V
V
CC = 4.5 V
IO = −5.2 mA;
CC = 6.0 V
V
bus driver outputs
IO = −6.0 mA;
3.98 4.32
5.48 5.81
-
-
3.84
5.34
-
-
3.7
5.2
-
-
V
V
V
CC = 4.5 V
IO = −7.8 mA;
CC = 6.0 V
V
VOL
LOW-level
VI = VIH or VIL
output voltage
all outputs
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
standard outputs
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
0.1
0.1
0.1
-
-
-
0.1
0.1
0.1
V
V
V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
bus driver outputs
-
-
0.15 0.26
0.16 0.26
-
-
0.33
0.33
-
-
0.4
0.4
V
V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND;
-
-
-
0.15 0.26
0.16 0.26
-
-
-
0.33
0.33
±1.0
-
-
-
0.4
0.4
V
V
II
input leakage
current
-
-
-
±0.1
±0.5
8.0
±1.0 µA
±10.0 µA
160 µA
V
CC = 6.0 V
IOZ
ICC
OFF-state output
current
VI = VIH or VIL; VO = VCC or
GND; VCC = 6.0 V
-
-
-
-
±5.0
-
-
supply current
VI = VCC or GND; IO = 0 A;
80
V
CC = 6.0 V
CI
input capacitance
-
-
3.5
10
-
-
-
-
-
-
-
-
-
-
pF
pF
CI/O
input/output
capacitance
[1]
CPD
power dissipation per package
capacitance
-
120
1.6
-
-
-
-
-
-
-
-
pF
V
74HCT299
VIH
HIGH-level
VCC = 4.5 V to 5.5 V
2.0
2.0
2.0
input voltage
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
8 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to
+85 °C
−40 °C to
+125 °C
Unit
Min
Typ
Max
Min
Max
Min
Max
VIL
LOW-level
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = −20 µA
4.4
4.5
-
-
-
4.4
-
-
-
4.4
3.7
3.7
-
-
-
V
V
V
standard outputs
IO = −4.0 mA
3.98 4.32
3.98 4.32
3.84
3.84
bus driver outputs
IO = −6.0 mA
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = 20 µA
-
-
0
0.1
-
-
0.1
-
-
0.1
0.4
0.4
V
V
V
standard outputs
IO = 4.0 mA
0.15 0.26
0.16 0.26
0.33
bus driver outputs
IO = 6.0 mA
-
-
-
-
0.33
-
-
II
input leakage
current
VI = VCC or GND;
-
±0.1
±1.0
±1.0 µA
V
CC = 5.5 V
IOZ
OFF-state output
current
VI = VIH or VIL; VO = VCC or
GND per input pin; other
inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
-
-
±0.5
-
±5.0
-
±10.0 µA
ICC
supply current
VI = VCC or GND; IO = 0 A;
-
-
8.0
-
80
-
160 µA
V
CC = 5.5 V
∆ICC
additional supply
current
per input pin;
VI = VCC − 2.1 V;
other inputs at VCC or
GND; IO = 0 A;
V
CC = 4.5 V to 5.5 V
I/On, DSR, DSL, MR
and S1
-
25
90
-
112.5
-
122.5 µA
CP, S0
OEn
-
-
-
-
60
30
3.5
10
216
-
-
-
-
270
-
-
-
-
294 µA
147 µA
108
135
CI
input capacitance
-
-
-
-
-
-
pF
pF
CI/O
input/output
capacitance
[1]
CPD
power dissipation per package
capacitance
-
125
-
-
-
-
-
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
9 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
∑(CL × VCC2 × fo) = sum of outputs.
CL = output load capacitance in pF;
VCC = supply voltage in V;
VI = GND to VCC for 74HC299;
VI = GND to (VCC − 1.5 V) for 74HCT299.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to
+85 °C
−40 °C to Unit
+125 °C
Min Typ Max Min Max Min Max
74HC299
[1]
tpd
propagation
delay
CP to Q0, Q7; see Figure 7
VCC = 2.0 V
-
-
-
-
66
24
20
19
200
40
-
-
-
-
-
250
50
-
-
-
-
-
300 ns
60 ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
-
ns
34
43
51 ns
CP to I/On; see Figure 7
VCC = 2.0 V
-
-
-
-
66
24
20
19
200
40
-
-
-
-
-
250
50
-
-
-
-
-
300 ns
60 ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
-
ns
34
43
51 ns
[2]
MR to Q0, Q7 or I/On;
see Figure 8
VCC = 2.0 V
-
-
-
-
66
24
20
19
200
40
-
-
-
-
-
250
50
-
-
-
-
-
300 ns
60 ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
-
ns
34
43
51 ns
[3]
tt
transition time
bus driver (I/On); see Figure 7
VCC = 2.0 V
-
-
-
14
5
60
12
10
-
-
-
75
15
13
-
-
-
90 ns
18 ns
15 ns
VCC = 4.5 V
VCC = 6.0 V
4
standard (Q0, Q7); see Figure 7
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110 ns
22 ns
19 ns
VCC = 4.5 V
VCC = 6.0 V
6
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
10 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to
+85 °C
−40 °C to Unit
+125 °C
Min Typ Max Min Max Min Max
tW
pulse width
CP HIGH or LOW; see Figure 7
VCC = 2.0 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
17
20
MR LOW; see Figure 8
VCC = 2.0 V
80
16
14
19
7
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
17
20
[4]
tPZH
tPZL
tPHZ
tPLZ
trec
OFF-state to
HIGH
propagation
delay
OEn to I/On; see Figure 10
VCC = 2.0 V
-
-
-
50
18
14
155
31
-
-
-
195
39
-
-
-
235 ns
47 ns
40 ns
VCC = 4.5 V
VCC = 6.0 V
26
33
OFF-state to
LOW
propagation
delay
OEn to I/On; see Figure 10
VCC = 2.0 V
-
-
-
41
15
12
130
26
-
-
-
165
33
-
-
-
195 ns
39 ns
33 ns
VCC = 4.5 V
VCC = 6.0 V
22
28
[5]
HIGH to
OFF-state
propagation
delay
OEn to I/On; see Figure 10
VCC = 2.0 V
-
-
-
66
24
19
185
37
-
-
-
230
46
-
-
-
280 ns
56 ns
48 ns
VCC = 4.5 V
VCC = 6.0 V
31
39
LOW to
OEn to I/On; see Figure 10
VCC = 2.0 V
OFF-state
propagation
delay
-
-
-
55
20
16
155
31
-
-
-
195
39
-
-
-
235 ns
47 ns
40 ns
VCC = 4.5 V
VCC = 6.0 V
26
33
recovery time
MR to CP; see Figure 8
VCC = 2.0 V
5
5
5
−14
−5
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
−4
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
11 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to
+85 °C
−40 °C to Unit
+125 °C
Min Typ Max Min Max Min Max
tsu
set-up time
DSR, DSL to CP; see Figure 7
VCC = 2.0 V
100
20
33
12
10
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
17
21
26
S0, S1 to CP; see Figure 9
VCC = 2.0 V
100
20
33
12
10
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
17
21
26
I/On to CP; see Figure 7
VCC = 2.0 V
125
25
39
14
11
-
-
-
155
31
-
-
-
190
38
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
21
26
32
th
hold time
I/On, DSR, DSL to CP;
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
0
0
0
−14
−5
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 6.0 V
−4
S0, S1 to CP; see Figure 9
VCC = 2.0 V
0
0
0
−28
−10
−8
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum
frequency
CP input; see Figure 7
VCC = 2.0 V
5.0
25
-
15
45
50
54
-
-
-
-
4.0
20
-
-
-
-
-
3.4
17
-
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
29
24
20
74HCT299
[1]
tpd
propagation
delay
CP to Q0, Q7; see Figure 7
VCC = 4.5 V
-
-
22
19
37
-
-
-
46
-
-
-
56 ns
ns
VCC = 5.0 V; CL = 15 pF
CP to I/On; see Figure 7
VCC = 4.5 V
-
-
-
22
19
37
-
-
-
46
-
-
-
56 ns
ns
VCC = 5.0 V; CL = 15 pF
-
[2]
MR to Q0, Q7 or I/On;
see Figure 8
VCC = 4.5 V
-
-
27
23
46
-
-
-
58
-
-
-
69 ns
ns
VCC = 5.0 V; CL = 15 pF
-
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
12 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
Conditions
25 °C
−40 °C to
+85 °C
−40 °C to Unit
+125 °C
Min Typ Max Min Max Min Max
[3]
tt
transition time
pulse width
enable time
bus driver (I/On); see Figure 7
VCC = 4.5 V
-
-
5
12
15
-
-
-
15
19
-
-
-
18 ns
22 ns
standard (Q0, Q7); see Figure 7
VCC = 4.5 V
7
tW
clock HIGH or LOW; see Figure 7
VCC = 4.5 V
20
20
-
10
11
19
24
25
25
-
30
30
-
-
-
ns
ns
master reset LOW; see Figure 8
VCC = 4.5 V
-
-
[4]
[5]
ten
OEn to I/On; see Figure 10
VCC = 4.5 V
30
37
38
46
45 ns
56 ns
tPHZ
HIGH to
OFF-state
propagation
delay
OEn to I/On; see Figure 10
VCC = 4.5 V
-
-
-
tPLZ
LOW to
OEn to I/On; see Figure 10
VCC = 4.5 V
OFF-state
propagation
delay
-
20
2
32
-
-
40
-
-
48 ns
trec
recovery time
MR to CP; see Figure 8
VCC = 4.5 V
10
9
11
-
ns
tsu
set-up time
I/On, DSR, DSL to CP;
see Figure 7
VCC = 4.5 V
25
32
14
18
-
-
31
40
-
-
38
48
-
-
ns
ns
S0, S1 to CP; see Figure 9
VCC = 4.5 V
th
hold time
I/On, DSR, DSL to CP;
see Figure 7
VCC = 4.5 V
0
0
−11
−17
-
-
0
0
-
-
0
0
-
-
ns
ns
S0, S1 to CP; see Figure 9
VCC = 4.5 V
fmax
maximum
frequency
CP input; see Figure 7
VCC = 4.5 V
25
-
42
46
-
-
20
-
-
-
17
-
-
-
MHz
MHz
VCC = 5.0 V; CL = 15 pF
[1] tpd is the same as tPHL and tPLH
.
[2] tpd is the same as tPHL
[3] tt is the same as tTHL and tTLH
[4] ten is the same as tPZH and tPZL
.
.
.
[5] tdis is the same as tPHZ and tPLZ
.
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
13 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
[6] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching.
11. Waveforms
V
I
I/On, DSR, DSL
inputs
V
M
t
GND
t
t
h
h
t
su
su
1/f
max
V
I
CP input
GND
V
M
t
W
t
t
PHL
PLH
V
OH
I/On, Q0, Q7
outputs
V
M
V
OL
t
t
TLH
THL
001aai462
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock pulse to outputs I/On, Q0, Q7 propagation delays, the clock pulse width, the I/On, DSR and DSL to
clock pulse set-up and hold times, the output transition times and the maximum clock frequency
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
14 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
V
I
MR input
GND
V
M
t
W
t
rec
V
I
V
M
CP input
GND
t
PHL
V
OH
I/On, Q0, Q7
outputs
V
M
V
OL
001aai463
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and the
master reset to clock pulse removal time
V
I
I/On, DSR, DSL, Sn
inputs
V
M
GND
t
t
t
t
h
su
h
su
V
I
CP input
V
M
GND
001aai464
Measurement points are given in Table 8.
Fig 9. Set-up and hold times from the mode control inputs S0, S1 to the clock pulse
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
15 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
t
t
f
r
V
I
90 %
OEn input
V
M
10 %
GND
t
t
PZL
PLZ
V
OH
I/On output
LOW to OFF
OFF to LOW
V
M
10 %
V
OL
t
t
PZH
PHZ
V
OH
90 %
I/On output
HIGH to OFF
OFF to HIGH
V
M
V
OL
outputs
enabled
outputs
disabled
outputs
enabled
001aai465
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. 3-state enable and disable times for OEn inputs
Table 8.
Type
Measurement points
Input
Output
VI
VM
VM
74HC299
VCC
3 V
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT299
V
V
CC
CC
V
V
O
I
R = 1 kΩ S1
L
PULSE
GENERATOR
open
DUT
C
50 pF
L
R
T
001aai466
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 11. Test circuit for measuring switching times
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
16 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
Table 9.
Type
Test data
Input
VI
Load
S1 position
tr, tf
6 ns
6 ns
CL
RL
tPHL, tPLH
open
74HC299
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT299
open
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
17 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 12. Package outline SOT163-1 (SO20)
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
18 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 13. Package outline SOT339-1 (SSOP20)
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
19 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 14. Package outline SOT146-1 (DIP20)
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
20 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 15. Package outline SOT360-1 (TSSOP20)
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
21 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
13. Revision history
Table 10. Revision history
Document ID
74HC_HCT299_3
Modifications:
Release date
20080728
Data sheet status
Change notice
Supersedes
Product data sheet
-
74HC_HCT299_CNV_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3: Ordering information added
• Section 12: Package outline drawings added
• Section 9 “Static characteristics”: Family data added
• Section 11 “Waveforms”: Test circuit added
74HC_HCT299_CNV_2
19970828
Product specification
-
-
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
22 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
14.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
23 of 24
74HC299; 74HCT299
NXP Semiconductors
8-bit universal shift register; 3-state
16. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
7
8
9
10
11
12
13
14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14.1
14.2
14.3
14.4
15
16
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 July 2008
Document identifier: 74HC_HCT299_3
相关型号：
74HC2G00DP-G
Dual 2-input NAND gate - Description: PicoGate 2-Input NAND Gate ; Logic switching levels: CMOS ; Number of pins: 8 ; Output drive capability: +/- 5.6 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 9@5V ns; Voltage: 2.0-6.0 V
NXP
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