74HC356DB [NXP]
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| 型号： | 74HC356DB |
| 厂家： | 
NXP |
| 描述： | 暂无描述 复用器 |
| 文件： | 总13页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT356
8-input multiplexer/register; 3-state
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
FEATURES
• Non-transparent data latches
• Transparent address latch
• Easily expanding
The 74HC/HCT356 data selectors/multiplexers contain full
on-chip binary decoding, to select one-of-eight data
sources. The data select address is stored in transparent
latches that are enabled by a LOW on the latch enable
input LE.
• Complementary outputs
• Output capability: bus driver
• ICC category: MSI
Data on the 8 input lines (D0 to D7) is clocked into a
edge-triggered data register by a LOW-to-HIGH transition
of the clock (CP).
When the output enable input OE1 = HIGH, OE2 = HIGH
or OE3 = LOW, the outputs go to the high impedance
OFF-state.
GENERAL DESCRIPTION
The 74HC/HCT356 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
Operation of these output enable inputs does not affect the
state of the latches and register.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC = 5 V
Sn, LE to Y, Y
24
25
ns
ns
pF
pF
CP to Y, Y
20
22
CI
input capacitance
3.5
123
3.5
125
CPD
power dissipation capacitance per package
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
PIN DESCRIPTION
PIN NO.
SYMBOL
D0 to D7
CP
NAME AND FUNCTION
8, 7, 6, 5, 4, 3, 2, 1
data inputs
9
clock input data (LOW-to-HIGH, edge-triggered)
ground (0 V)
10
GND
LE
11
address latch enable input (active LOW)
select inputs
14, 13, 12
S0, S1, S2
OE1, OE2
OE3
15, 16
17
output enable inputs (active LOW)
output enable input (active HIGH)
3-state multiplexer output (active LOW)
3-state multiplexer output (active HIGH)
positive supply voltage
18
Y
19
Y
20
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
FUNCTION TABLE
INPUTS
OUTPUTS
Y
ADDRESS (1)
S1
OUTPUT ENABLE
OE1 OE2 OE3
DESCRIPTION
S2
S0
CP
Y
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
H
X
X
X
L
Z
Z
Z
Z
Z
Z
outputs in
high impedance
OFF-state
L
L
L
L
L
L
H
H
L
H
L
↑
↑
↑
↑
L
L
L
L
L
L
L
L
H
H
H
H
D0n
D1n
D2n
D3n
D0n
D1n
D2n
D3n
H
data is clocked
into latch
H
H
H
H
L
L
H
H
L
H
L
↑
↑
↑
↑
L
L
L
L
L
L
L
L
H
H
H
H
D4n
D5n
D6n
D7n
D4n
D5n
D6n
D7n
H
(2)
(2)
(2)
(2)
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
D0p
D1p
D2p
D3p
D0p
D1p
D2p
D3p
H
outputs do not
change states
(2)
(2)
(2)
(2)
H
H
H
H
L
L
H
H
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
D4p
D5p
D6p
D7p
D4p
D5p
D6p
D7p
H
Notes
1. This column shows the input address set-up with LE = LOW (address latch is transparent).
2. CP is HIGH, LOW or ↓.
3. D0n to D7n = data present at inputs D0 to D7 when the data latch clock made the transition from LOW-to-HIGH
D0p to D7p = data previously latched into the data latch by the LOW-to-HIGH transition of the data latch clock
H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition
↓ = HIGH-to-LOW CP transition
Z = high impedance OFF-state
December 1990
4
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
Fig.4 Functional diagram.
December 1990
5
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
Fig.5 Logic diagram.
December 1990
6
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Y, Y
66 240
24 48
19 41
300
60
51
360
72
61
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
t
t
t
t
PHL/ tPLH propagation delay
Sn to Y, Y
77 260
28 52
22 44
325
65
55
390
78
66
2.0 Fig.7
4.5
6.0
PHL/ tPLH propagation delay
LE to Y, Y
77 270
28 54
22 46
340
68
58
405
81
69
2.0 Fig.8
4.5
6.0
PZH/ tPZL 3-state output enable time
OEn to Y, Y
41 125
15 25
12 21
155
31
26
190
38
32
2.0 Fig.11
4.5
6.0
PZH/ tPZL 3-state output enable time
OE3 to Y, Y
47 150
17 30
14 26
190
38
33
225
45
38
2.0 Fig.11
4.5
6.0
tPHZ/ tPLZ 3-state output disable time
OEn to Y, Y
50 155
18 31
14 26
195
39
33
235
47
40
2.0 Fig.11
4.5
6.0
t
t
PHZ/ tPLZ 3-state output disable time
OE3 to Y, Y
58 155
21 31
17 26
195
39
33
235
47
40
2.0 Fig.11
4.5
6.0
THL/ tTLH output transition time
14 60
75
15
13
90
18
15
2.0 Figs 6, 7 and 8
4.5
6.0
5
4
12
10
tW
tW
tsu
clock pulse width CP
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
latch enable pulse width LE 80
LOW
17
6
5
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
16
14
set-up time
Dn to CP
50
10
9
11
4
3
65
13
11
75
15
13
2.0 Fig.10
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tsu
set-up time
Sn to LE
50
10
9
14
5
4
65
13
11
75
15
13
ns
ns
ns
2.0 Fig.9
4.5
6.0
th
hold time
Dn to CP
5
5
5
−6
−2
−2
5
5
5
5
5
5
2.0 Fig.10
4.5
6.0
th
hold time
Sn to LE
5
5
5
−8
−3
−2
5
5
5
5
5
5
2.0 Fig.9
4.5
6.0
December 1990
8
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn, Sn
OE3
LE
0.2
0.25
0.5
1.0
OEn, CP
December 1990
9
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Y, Y
26
28
29
17
18
17
20
5
51
59
63
34
34
33
33
12
64
74
79
43
43
41
41
15
77
89
95
51
51
50
50
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
tPHL/ tPLH propagation delay
Sn to Y, Y
4.5 Fig.7
tPHL/ tPLH propagation delay
LE to Y, Y
4.5 Fig.8
tPZH/ tPZL 3-state output enable time
OEn to Y, Y
4.5 Fig.11
4.5 Fig.11
4.5 Fig.11
4.5 Fig.11
4.5 Figs 6, 7 and 8
4.5 Fig.6
t
t
t
t
PZH/ tPZL 3-state output enable time
OE3 to Y, Y
PHZ/ tPLZ 3-state output disable time
OEn to Y, Y
PHZ/ tPLZ 3-state output disable time
OE3 to Y, Y
THL/ tTLH output transition time
tW
tW
tsu
tsu
th
clock pulse width CP
HIGH or LOW
16
16
10
10
5
8
20
20
13
13
5
24
24
15
15
5
latch enable pulse width
LE LOW
6
4.5 Fig.8
set-up time
Dn to CP
4
4.5 Fig.10
4.5 Fig.9
set-up time
Sn to LE
5
hold time
Dn to CP
0
4.5 Fig.10
4.5 Fig.9
th
hold time
Sn to LE
5
−2
5
5
December 1990
10
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (CP) to the output (Y, Y) propagation delays, the clock pulse width and the
output transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the select input (Sn) to output (Y, Y) propagation delays and the output transition
times (LE = LOW).
December 1990
11
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the address latch enable input (LE) pulse width, the latch enable input to output
(Y, Y) propagation delays and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the set-up and hold times for the select input (Sn) to the address latch enable input
(LE).
December 1990
12
Philips Semiconductors
Product specification
8-input multiplexer/register; 3-state
74HC/HCT356
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the set-up and hold times for the data input (Dn) to the clock (CP).
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the 3-state enable and disable times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
13
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