74HC393DB-T [NXP]
暂无描述;
| 型号： | 74HC393DB-T |
| 厂家： | 
NXP |
| 描述： | 暂无描述 计数器 |
| 文件： | 总7页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT393
Dual 4-bit binary ripple counter
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
74HC/HCT393
The 74HC/HCT393 are 4-bit binary ripple counters with
separate clocks (1CP and 2 CP) and master reset (1MR
and 2MR) inputs to each counter. The operation of each
half of the “393” is the same as the “93” except no external
clock connections are required.
FEATURES
• Two 4-bit binary counters with individual clocks
• Divide-by any binary module up to 28 in one package
• Two master resets to clear each 4-bit counter
The counters are triggered by a HIGH-to-LOW transition of
the clock inputs. The counter outputs are internally
connected to provide clock inputs to succeeding stages.
The outputs of the ripple counter do not change
synchronously and should not be used for high-speed
address decoding.
individually
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The master resets are active-HIGH asynchronous inputs
to each 4-bit counter identified by the “1” and “2” in the pin
description.
A HIGH level on the nMR input overrides the clock and
sets the outputs LOW.
The 74HC/HCT393 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
nCP to nQ0
12
20
ns
nQ to nQn+1
5
6
ns
nMR to nQn
11
99
3.5
23
15
53
3.5
25
ns
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
CPD
power dissipation capacitance per counter
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
74HC/HCT393
PIN DESCRIPTION
PIN NO.
SYMBOL
1CP, 2CP
1MR, 2MR
1Q0 to 1Q3, 2Q0 to 2Q3
GND
NAME AND FUNCTION
1, 13
clock inputs (HIGH-to-LOW, edge-triggered)
asynchronous master reset inputs (active HIGH)
flip-flop outputs
2, 12
3, 4, 5, 6, 11, 10, 9, 8
7
ground (0 V)
14
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
74HC/HCT393
Fig.4 Functional diagram.
Fig.5 State diagram.
COUNT SEQUENCE FOR 1 COUNTER
OUTPUTS
COUNT
Q0
Q1
Q2
Q3
0
1
2
3
L
H
L
L
L
H
H
L
L
L
L
L
L
L
L
H
4
5
6
7
L
H
L
L
L
H
H
H
H
H
H
L
L
L
L
H
8
9
10
11
L
H
L
L
L
H
H
L
L
L
L
H
H
H
H
H
12
13
14
15
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
Notes
Fig.6 Logic diagram (one counter).
1. H = HIGH voltage level
L = LOW voltage level
December 1990
4
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
74HC/HCT393
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQ0
41
15
12
125
25
21
155
31
26
190
38
32
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
4.5
6.0
t
PHL/ tPLH propagation delay
nQn to nQn+1
14
5
4
45
9
8
55
11
9
70
14
12
2.0 Fig.7
4.5
6.0
tPHL
propagation delay
nMR to nQn
39
14
11
140
28
24
175
35
30
210
42
36
2.0 Fig.8
4.5
6.0
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.7
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
tW
master reset pulse
width; HIGH
80
16
14
19
7
6
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
trem
removal time
nMR to nCP
5
5
5
3
1
1
5
5
5
5
5
5
2.0 Fig.8
4.5
6.0
fmax
maximum clock pulse
frequency
6
30
35
30
90
107
5
24
28
4
20
24
MHz 2.0 Fig.7
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
74HC/HCT393
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
1CP
2CP
1MR
2MR
0.4
0.4
1.0
1.0
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQ0
15
25
10
32
15
31
13
40
19
38
15
48
22
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.7
4.5 Fig.8
4.5 Fig.7
4.5 Fig.7
4.5 Fig.8
4.5 Fig.8
t
PHL/ tPLH propagation delay
nQn to nQn+1
6
tPHL
propagation delay
nMR to nQn
18
7
t
THL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
19
16
5
11
6
24
20
5
29
24
5
tW
master reset pulse
width; HIGH
trem
fmax
removal time
nMR to nCP
0
maximum clock pulse
frequency
27
48
22
18
MHz 4.5 Fig.7
December 1990
6
Philips Semiconductors
Product specification
Dual 4-bit binary ripple counter
74HC/HCT393
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock (nCP) to output (1Qn, 2Qn) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the master reset (nMR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (nCP) removal time.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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