74HC40102 [NXP]
8-bit synchronous BCD down counter; 8位同步的BCD减计数器
| 型号： | 74HC40102 |
| 厂家： | 
NXP |
| 描述： | 8-bit synchronous BCD down counter |
| 文件： | 总11页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT40102
8-bit synchronous BCD down
counter
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
When the synchronous preset enable input (PE) is LOW,
data at the jam input (P0 to P7) is clocked into the counter
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P0 to P7) is
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P0 to P7) represent
two 4-bit BCD words.
FEATURES
• Cascadable
• Synchronous or asynchronous preset
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal
99) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.
The 74HC/HCT40102 are high-speed Si-gate CMOS
devices and are pin compatible with the “40102” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40102 consist each of an 8-bit
If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 100 clock pulses long.
The “40102” may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.
synchronous down counter with a single output which is
active when the internal count is zero. The “40102” is
configured as two cascaded 4-bit BCD counters and has
control inputs for enabling or disabling the clock (CP), for
clearing the counter to its maximum count, and for
presetting the counter either synchronously or
APPLICATIONS
asynchronously. All control inputs and the terminal count
output (TC) are active-LOW logic.
• Divide-by-n counters
• Programmable timers
• Interrupt timers
In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero if TE is LOW, and remains LOW for
one full clock period.
• Cycle/program counters
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PHL/ tPLH
PARAMETER
CONDITIONS
UNIT
HC
30
HCT
31
t
propagation delay CP to TC
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V
ns
fmax
CI
30
3.5
20
30
3.5
25
MHz
pF
CPD
power dissipation capacitance per package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
December 1990
2
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
CP
clock input (LOW-to-HIGH, edge-triggered)
asynchronous master reset input (active LOW)
terminal enable input
2
MR
3
TE
4, 5, 6, 7, 10, 11, 12, 13
P0 to P7
GND
PL
jam inputs
8
ground (0 V)
9
asynchronous preset enable input (active LOW)
terminal count output (active LOW)
synchronous preset enable input (active LOW)
positive supply voltage
14
15
16
TC
PE
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
Fig.4 Functional diagram.
FUNCTION TABLE
CONTROL INPUTS
PRESET MODE ACTION
MR
PL
PE
TE
H
H
H
H
L
H
H
H
L
H
H
L
H
L
inhibit counter
count down
synchronous
asynchronous
X
X
X
preset on next LOW-to HIGH clock transition
preset asynchronously
X
X
X
clear to maximum count
Notes
1. Clock connected to CP.
2. Synchronous operation: changes occur on the LOW-to-HIGH CP transition.
3. Jam inputs: MSD = P7, LSD = P0.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
December 1990
4
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990
5
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to TC
96
35
28
300
60
51
375
75
64
450
90
77
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.8
4.5
6.0
t
t
PHL/ tPLH propagation delay
TE to TC
50
18
14
200
40
34
250
50
43
300
60
51
2.0 Fig.8
4.5
6.0
PHL/ tPLH propagation delay
Pn, PL to TC
110 240
40
32
425
85
72
510
102
87
2.0 Fig.8
4.5
6.0
68
58
tPLH
propagation delay
MR to TC
83
30
24
275
55
47
345
69
59
415
83
71
2.0 Fig.8
4.5
6.0
t
THL/ tTLH output transition time
9
7
6
75
15
13
95
19
16
110
22
19
2.0 Figs 8 and 8
4.5
6.0
tW
tW
tW
trem
tsu
tsu
clock pulse width
HIGH or LOW
165 22
205
41
35
250
50
43
2.0 Fig.8
4.5
6.0
33
28
8
6
master reset pulse width 150 30
LOW
190
38
33
225
45
38
2.0 Fig.8
4.5
6.0
30
26
11
9
preset enable pulse width 125 39
PL; LOW
155
31
26
190
38
32
2.0 Fig.8
4.5
6.0
25
21
14
11
removal time
PL; MR to CP
50
10
9
8
3
2
65
13
11
75
15
13
2.0 Fig.8
4.5
6.0
set-up time
PE to CP
100 36
125
25
21
150
30
26
2.0 Fig.8
4.5
6.0
20
17
13
10
set-up time
TE to CP
175 50
220
44
37
265
53
45
2.0 Fig.8
4.5
6.0
35
30
18
14
December 1990
6
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
T
amb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tsu
set-up time
Pn to CP
100 33
125
25
21
150
30
26
ns
ns
ns
ns
2.0 Fig.8
4.5
6.0
20
17
12
10
th
hold time
PE to CP
2
2
2
−8
−3
−2
2
2
2
2
2
2
2.0 Fig.8
4.5
6.0
th
hold time
TE to CP
0
0
0
−41
−15
−12
0
0
0
0
0
0
2.0 Fig.8
4.5
6.0
th
hold time
Pn to CP
2
2
2
−5
−5
−5
2
2
2
2
2
2
2.0 Fig.8
4.5
6.0
fmax
maximum clock pulse
frequency
3
15
18
8.9
27
32
2
12
14
2
10
12
MHz 2.0 Fig.8
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
CP, PE
MR
TE
Pn
PL
1.50
1.00
0.80
0.25
0.35
December 1990
8
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Pn; CP to TC
38
25
49
31
7
63
50
83
55
15
79
95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Figs 8 and 8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Figs 8 and 8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
4.5 Fig.8
t
PHL/ tPLH propagation delay
TE to TC
63
75
t
PHL/ tPLH propagation delay
PL to TC
104
69
125
83
tPLH
propagation delay
MR to TC
t
THL/ tTLH output transition time
19
22
tW
tW
tW
trem
tsu
tsu
tsu
th
clock pulse width
HIGH or LOW
33
11
16
25
1
41
38
54
13
25
50
25
0
50
45
65
15
30
60
30
0
master reset pulse width 30
LOW
preset enable pulse width 43
PL; LOW
removal time
PL; MR to CP
10
20
40
20
0
set-up time
PE to CP
10
20
12
−4
−15
−6
27
set-up time
TE to CP
set-up time
Pn to CP
hold time
PE to CP
th
hold time
TE to CP
0
0
0
th
hold time
Pn to CP
0
0
0
fmax
maximum clock pulse
frequency
15
12
10
MHz 4.5 Fig.8
December 1990
9
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the clock input (CP) to
TC propagation delays, the clock pulse
width, the output transition times and the
maximum clock pulse frequency.
Fig.8 Waveforms showing the TE to
TC propagation delays.
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing removal time for
MR and PL.
Fig.9 Waveforms showing PL, MR, Pn to
TC propagation delays.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing hold and set-up times
for MR or PE to CP.
Fig.12 Waveforms showing hold and set-up times
for Pn, PE to CP.
December 1990
10
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
74HC/HCT40102
APPLICATION INFORMATION
Fig.13 Programmable timer.
Fig.14 Divide-by-N counter.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
11
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