74HC40105N,652_技术文档

74HC40105; 74HCT40105

4-bit x 16-word FIFO register

Rev. 3 — 25 September 2013

Product data sheet

1. General description

The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that

can store 16 4-bit words. It can handle input and output data at different shifting rates.

This feature makes it particularly useful as a buffer between asynchronous systems. Each

word position in the register is clocked by a control flip-flop, which stores a marker bit. A

logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in

that position. The control flip-flop detects the state of the preceding flip-flop and

communicates its own status to the succeeding flip-flop. When a control flip-flop is in the

logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The

clock pulse transfers data from the preceding four data latches into its own four data

latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have

buffered outputs. All empty locations "bubble" automatically to the input end, and all valid

data ripples through to the output end. As a result, the status of the first control flip-flop

(data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop

(data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest

data is removed from the bottom of the data stack (output end), all data entered later will

automatically ripple toward the output. Inputs include clamp diodes that enable the use of

current limiting resistors to interface inputs to voltages in excess of V_CC

.

2. Features and benefits

 Independent asynchronous inputs and outputs

 Expandable in either direction

 Reset capability

 Status indicators on inputs and outputs

 3-state outputs

 Input levels:

 For 74HC40105: CMOS level

 For 74HCT40105: TTL level

 3-state outputs

 Complies with JEDEC standard JESD7A

 ESD protection:

 HBM JESD22-A114F exceeds 2 000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature

range

Name

Description

Version

74HC40105N

74HCT40105N

74HC40105D

74HCT40105D

74HC40105DB

74HCT40105DB

40 C to +125 C DIP16

40 C to +125 C SO16

40 C to +125 C SSOP16

plastic dual in-line package; 16 leads (300 mil)

SOT38-4

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

SOT338-1

SOT403-1

plastic shrink small outline package; 16 leads;

body width 5.3 mm

74HC40105PW 40 C to +125 C TSSOP16

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

4. Functional diagram

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Fig 1. Logic symbol

Fig 2. IEC logic symbol

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

2 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

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Fig 3. Functional diagram

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LOW on S input of FF1 and FF5 sets Q output to HIGH independent of state on R input.

LOW on R input of FF2, FF3 and FF4 sets Q output to LOW independent of state on S input.

Fig 4. Logic diagram

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

3 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

5. Pinning information

5.1 Pinning

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Fig 5. Pin configuration DIP16 and SO16

Fig 6. Pin configuration (T)SSOP16

5.2 Pin description

Table 2.

Symbol

OE

Pin description

Description

1

output enable input (active LOW)

data-in-ready output

DIR

2

SI

3

shift-in input (LOW-to-HIGH, edge triggered)

parallel data input

D0 to D3

GND

MR

4, 5, 6, 7

8

ground (0 V)

9

asynchronous master-reset input (active HIGH)

data output

Q0 to Q3

DOR

SO

13, 12, 11, 10

14

15

16

data-out-ready output

shift-out input (HIGH-to-LOW, edge triggered)

supply voltage

V_CC

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

4 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

6. Functional description

6.1 Inputs and outputs

6.1.1 Data inputs (D0 to D3)

As there is no weighting of the inputs, any input can be assigned as the MSB. The size of

the FIFO memory can be reduced from the 4 x 16 configuration. For example, it can be

reduced to 3 x 16, down to 1 x 16, by tying unused data input pins to V_CCor GND.

6.1.2 Data outputs (Q0 to Q3)

As there is no weighting of the outputs, any output can be assigned as the MSB. The size

of the FIFO memory can be reduced from the 4 x 16 configuration as described for data

inputs. In a reduced format, the unused data outputs pins must be left open circuit.

6.1.3 Master-reset (MR)

When MR is HIGH, the control functions within the FIFO are cleared, and date content is

declared invalid. The data-in ready (DIR) flag is set HIGH and the data-out-ready (DOR)

flag is set LOW. The output stage remains in the state of the last word that was shifted out,

or in the random state existing at power-up.

6.1.4 Status flag outputs (DIR, DOR)

Two status flags, data-in-ready (DIR) and data-out-ready (DOR), indicate the status of the

FIFO:

1. DIR = HIGH indicates that the input stage is empty and ready to accept valid data;

2. DIR = LOW indicates that the FIFO is full or that a previous shift-in operation is not

complete (busy);

3. DOR = HIGH assures valid data is present at the outputs Q0 to Q3 (does not indicate

that new data is awaiting transfer into the output stage);

4. DOR = LOW indicates that the output stage is busy or there is no valid data.

6.1.5 Shift-in control (SI)

Data is loaded into the input stage on a LOW-to-HIGH transition of SI. It also triggers an

automatic data transfer process (ripple through). If SI is held HIGH during reset, data is

loaded at the falling edge of the MR signal.

6.1.6 Shift-out control (SO)

A HIGH-to-LOW transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW

transition of SO causes upstream data to move into the output stage, and empty locations

to move towards the input stage (bubble-up).

6.1.7 Output enable (OE)

The outputs Q0 to Q3 are enabled when OE = LOW. When OE = HIGH the outputs are in

the high impedance OFF-state.

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

5 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

6.2 Data input

Following power-up, the master-reset (MR) input is pulsed HIGH to clear the FIFO

memory (see Figure 7). The data-in-ready flag (DIR = HIGH) indicates that the FIFO input

stage is empty and ready to receive data. When DIR is valid (HIGH), data present at D0 to

D3 can be shifted-in using the SI control input. With SI = HIGH, data is shifted into the

input stage. DIR going LOW provides a busy indication. The data remains at the first

location in the FIFO until DIR is set to HIGH and data moves through the FIFO to the

output stage, or to the last empty location. If the FIFO is not full after the SI pulse, DIR

again becomes valid (HIGH) to indicate that space is available in the FIFO. The DIR flag

remains LOW if the FIFO is full (see Figure 8). To complete the shift-in process, the SI use

must be made LOW. With the FIFO full, SI can be held HIGH until a shift-out (SO) pulse

occurs. Then, following a shift-out of data, an empty location appears at the FIFO input

and DIR goes HIGH to allow the next data to be shifted-in. This data remains at the first

FIFO location until SI goes LOW (see Figure 9).

6.3 Data transfer

After data has been transferred from the input stage of the FIFO following SI = LOW, data

moves through the FIFO asynchronously and is stacked at the output end of the register.

Empty locations appear at the input end of the FIFO as data moves through the device.

6.4 Data output

The data-out-ready flag (DOR = HIGH) indicates that there is valid data at the output (Q0

to Q3). The initial master-reset at power-on (MR = HIGH) sets DOR to LOW (see

Figure 7). After MR = LOW, data shifted into the FIFO moves through to the output stage

causing DOR to go HIGH. As the DOR flag goes HIGH, data can be shifted-out using the

SO = HIGH, data in the output stage is shifted out. DOR going LOW provides a busy

indication. When SO is made LOW, data moves through the FIFO to fill the output stage

and an empty location appears at the input stage. When the output stage is filled DOR

goes HIGH, but if the last of the valid data has been shifted-out leaving the FIFO empty

the DOR flag remains LOW (see Figure 11). With the FIFO empty, the last word that was

shifted-out is latched at the output Q0 to Q3.

With the FIFO empty, the SO input can be held HIGH until the SI control input is used.

Following an SI pulse, data moves through the FIFO to the output stage, resulting in the

DOR flag pulsing HIGH and a shift-out of data occurring. The SO control must be made

LOW before additional data can be shifted-out (see Figure 14).

6.5 High-speed burst mode

Assuming the shift-in/shift-out pulses are not applied until the respective status flags are

valid, it follows that the status flags determine the shift-in/shift-out rates. However, without

the status flags, a high-speed burst can be implemented. In this mode, pulse widths

determine the burst-in/ burst-out rates of the shift-in/shift-out inputs. Burst rates of 35 MHz

can be obtained. Shift pulses can be applied without regard to the status flags but shift-in

pulses that would overflow the storage capacity of the FIFO are not allowed (see

Figure 12 and Figure 13).

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

6 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

6.6 Expanded format

With the addition of a logic gate, the FIFO is easily expanded to increase word length (see

Figure 19). The basic operation and timing are identical to a single FIFO, except for an

additional gate delay on the flag outputs. If during application, the following occurs:

• SI is held HIGH when the FIFO is empty, some additional logic is required to produce

a composite DIR pulse (see Figure 9 and Figure 20).

Due to the part-to-part spread of the ripple through time, the SI signals of FIFOA and

FIFOB do not always coincide. As a result, the AND-gate does not produce a composite

flag signal. The solution is given in Figure 20. The “40105” is easily cascaded to increase

the word capacity and no external components are needed. In the cascaded

configuration, the FIFOs perform all necessary communications and timing. The minimum

flag pulse widths and the flag delays determine the intercommunication speed. The data

rate of cascaded devices is typically 25 MHz. Word-capacity can be expanded to and

beyond 32-words x 4-bits (see Figure 21).

7. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7

Unit

V

supply voltage

0.5

input clamping current

output clamping current

output current

V_I< 0.5 V or V_I> V_CC+ 0.5 V

V_O< 0.5 V or V_O> V_CC+ 0.5 V

V_O= 0.5 V to (V_CC+ 0.5 V)

-

20

25

+50

-

mA

C

I_OK

-

I_O

-

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

50

storage temperature

total power dissipation

65

+150

750

500

[1]

[2]

[3]

DIP16 package

-

mW

SO16 package

(T)SSOP16 package

[1] For DIP16 packages: above 70 C the value of P_totderates linearly with 12 mW/K.

[2] For SO16 packages: above 70 C the value of P_totderates linearly with 8 mW/K.

[3] For SSOP16 and TSSOP16 packages: above 60 C the value of P_totderates linearly with 5.5 mW/K.

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

7 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

8. Recommended operating conditions

Table 4.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions

74HC40105

74HCT40105

Unit

Min

Typ

Max

6.0

Min

Typ

Max

5.5

V_CC

V_I

supply voltage

2.0

5.0

4.5

5.0

V

input voltage

0

-

V_CC

+125

625

139

83

0

-

V_CC

V_O

output voltage

0

-

+25

-

0

-

+25

-

T_amb

t/V

ambient temperature

input transition rise and fall rate V_CC= 2.0 V

V_CC= 4.5 V

40

+125 C

-

ns/V

1.67

-

1.67

-

139 ns/V

V_CC= 6.0 V

-

ns/V

9. Static characteristics

Table 5.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 C

Min Typ

40 C to +85 C 40 C to +125 C Unit

Max

Min

Max

Min

Max

74HC40105

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

1.5

1.2

2.4

3.2

0.8

-

1.5

-

1.5

-

V

V_CC= 4.5 V

3.15

V_CC= 6.0 V

4.2

-

4.2

-

4.2

-

V_IL

LOW-level

input voltage

V_CC= 2.0 V

-

0.5

-

0.5

1.35

1.8

-

0.5

1.35

1.8

V_CC= 4.5 V

2.1 1.35

V_CC= 6.0 V

2.8

1.8

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

I_O= 4 mA; V_CC= 4.5 V

1.9

4.4

5.9

2.0

4.5

6.0

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

5.9

3.98 4.32

3.84

5.34

I_O= 5.2 mA; V_CC= 6.0 V 5.48 5.81

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

I_O= 4 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

-

0

0.1

-

0.1

-

0.1

0.4

1.0

V

0.1

V

0.15 0.26

0.33

1.0

V

I_I

input leakage

current

V_I= V_CCor GND;

V_CC= 6.0 V

-

0.1

A

I_OZ

OFF-state

V_I= V_IHor V_IL;

-

0.5

-

5.0

-

10.0 A

output current V_O= V_CCor GND;

V_CC= 6.0 V

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

8 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

Table 5.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ

Max

Min

Max

Min

Max

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

8

-

80

-

160

A

C_I

input

-

3.5

-

pF

capacitance

74HCT40105

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

1.6

1.2

-

2.0

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 A

4.4

4.5

-

4.4

-

4.4

3.7

-

V

I_O= 4 mA

3.98 4.32

3.84

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 A

-

0

0.1

-

0.1

-

0.1

0.4

V

I_O= 4 mA

0.15 0.26

0.33

1.0

V

I_I

input leakage

current

V_I= V_CCor GND;

V_CC= 5.5 V

-

0.1

1.0

A

I_OZ

OFF-state

V_I= V_IHor V_IL; V_CC= 5.5 V;

-

0.5

-

5.0

-

10

A

output current V_O= V_CCor GND per input

pin; other inputs at V_CCor

GND; I_O= 0 A

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

-

8

-

80

-

160

I_CC

additional

V_I= V_CC 2.1 V;

supply current other inputs at V_CCor GND;

V_CC= 4.5 V to 5.5 V;

I_O= 0 A

per input pin; Dn inputs

per input pin; OE input

per input pin; SI input

per input pin; MR input

per input pin; SO input

-

30

75

108

270

144

540

144

-

135

338

180

675

180

-

147

368

196

735

196

A

pF

40

150

40

C_I

input

3.5

capacitance

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

9 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

10. Dynamic characteristics

Table 6.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 18.

Symbol Parameter Conditions

74HC40105

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

[1]

t_pd

propagation MR to DIR or DOR; see

delay

Figure 7

V_CC= 2.0 V

-

52

19

16

15

175

35

-

220

44

-

265

53

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

30

37

45

[1]

SO to Qn; see Figure 10

V_CC= 2.0 V

-

116

42

400

80

-

500

100

-

600

120

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

37

34

68

85

102

t_PHL

HIGH to

LOW

propagation

delay

SI to DIR; see Figure 8

V_CC= 2.0 V

-

52

19

16

15

210

42

-

265

53

-

315

63

-

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

36

45

54

SO to DOR; see

Figure 11

V_CC= 2.0 V

V_CC= 4.5 V

-

55

20

17

16

210

42

-

265

53

-

315

63

-

ns

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

36

45

54

[1][5]

[1][6]

[2]

t_PLH

LOW to

HIGH

propagation

delay

SI to DOR; see Figure 14

V_CC= 2.0 V

-

564 2000

-

2500

500

-

3000

600

ns

V_CC= 4.5 V

205

165

400

340

V_CC= 6.0 V

425

510

SO to DIR; see Figure 9

V_CC= 2.0 V

-

701 2500

-

3125

625

-

3750

750

ns

V_CC= 4.5 V

255

204

500

425

V_CC= 6.0 V

532

638

t_en

enable time OE to Qn; see Figure 16

V_CC= 2.0 V

-

41

15

12

150

30

-

190

38

-

225

45

ns

V_CC= 4.5 V

V_CC= 6.0 V

26

33

38

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

10 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

Table 6.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 18.

Symbol Parameter Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

[3]

[4]

t_dis

disable time OE to Qn; see Figure 16

V_CC= 2.0 V

V_CC= 4.5 V

-

41

15

12

140

28

-

175

35

-

210

42

ns

V_CC= 6.0 V

24

30

36

t_t

transition

time

Qn; see Figure 10

V_CC= 2.0 V

-

19

7

75

15

13

-

95

19

16

-

110

22

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

19

t_W

pulse width SI HIGH or LOW;

see Figure 8

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

80

16

14

19

7

-

100

20

-

120

24

-

ns

6

17

20

SO HIGH or LOW;

see Figure 11

V_CC= 2.0 V

V_CC= 4.5 V

120

24

39

14

11

-

150

30

-

180

36

-

ns

V

_CC= 6.0 V

20

26

31

DIR HIGH; see Figure 9

V_CC= 2.0 V

12

6

58

21

17

180

36

10

5

225

45

10

5

270

54

ns

V_CC= 4.5 V

V_CC= 6.0 V

5

31

4

38

4

46

DOR LOW; see Figure 14

V_CC= 2.0 V

12

6

55

20

16

170

34

10

5

215

43

10

5

255

51

ns

V_CC= 4.5 V

V_CC= 6.0 V

5

29

4

37

4

43

MR HIGH; see Figure 7

V_CC= 2.0 V

80

16

14

22

8

-

100

20

-

120

24

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

17

20

t_rec

recovery

time

MR to SI; see Figure 15

V_CC= 2.0 V

50

10

9

14

5

-

65

13

11

-

75

15

13

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

4

t_su

set-up time Dn to SI; see Figure 17

V_CC= 2.0 V

5

39

14

11

-

5

-

5

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

11 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

Table 6.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 18.

Symbol Parameter Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

t_h

hold time

Dn to SI; see Figure 17

V_CC= 2.0 V

125

25

44

16

13

-

155

31

-

190

38

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

21

26

32

f_max

maximum

frequency

SI, SO using flags or

burst mode; see Figure 8

and Figure 11; see

Figure 12 and Figure 13

V_CC= 2.0 V

3.6

18

-

10

30

33

36

-

2.8

14

-

2.4

12

-

MHz

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

21

16

14

SI, SO cascaded; see

Figure 8 and Figure 11

V_CC= 2.0 V

V_CC= 4.5 V

3.6

18

21

-

10

30

-

2.8

14

16

-

2.4

12

14

-

MHz

pF

V_CC= 6.0 V

36

[7]

C_PD

power

V_I= GND to V_CC

134

dissipation

capacitance

74HC_HCT40105

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Product data sheet

Rev. 3 — 25 September 2013

12 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

Table 6.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 18.

Symbol Parameter Conditions

74HCT40105

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

[1]

t_pd

propagation MR to DIR or DOR; see

delay

Figure 7

V_CC= 4.5 V

-

18

15

35

-

44

-

53

-

ns

V_CC= 5 V; C_L= 15 pF

SO to Qn; see Figure 10

V_CC= 4.5 V

[1]

-

40

35

80

-

100

-

120

-

ns

V_CC= 5 V; C_L= 15 pF

SI to DIR; see Figure 8

V_CC= 4.5 V

t_PHL

HIGH to

LOW

-

21

18

42

-

53

-

63

-

ns

propagation

delay

V_CC= 5 V; C_L= 15 pF

SO to DOR; see

Figure 11

V_CC= 4.5 V

-

20

18

42

-

53

-

63

-

ns

V_CC= 5 V; C_L= 15 pF

SI to DOR; see Figure 14

V_CC= 4.5 V

[1][5]

[1][6]

[2]

t_PLH

LOW to

HIGH

propagation

delay

-

188

244

18

400

500

35

-

500

625

44

-

600

750

53

ns

SO to DIR; see Figure 9

V_CC= 4.5 V

t_en

t_dis

t_t

enable time OE to Qn; see Figure 16

V_CC= 4.5 V

[3]

disable time OE to Qn; see Figure 16

V_CC= 4.5 V

15

30

38

45

[4]

transition

time

Qn; see Figure 10

V_CC= 4.5 V

7

15

19

22

t_W

pulse width SI HIGH or LOW;

see Figure 8

V_CC= 4.5 V

16

6

-

20

-

24

-

ns

SO HIGH or LOW;

see Figure 11

V_CC= 4.5 V

16

6

7

20

19

7

-

34

-

20

5

-

43

-

24

5

-

51

-

ns

DIR HIGH; see Figure 9

V_CC= 4.5 V

DOR LOW; see Figure 14

V_CC= 4.5 V

6

5

MR HIGH; see Figure 7

V_CC= 4.5 V

16

15

20

19

24

22

t_rec

recovery

time

MR to SI; see Figure 15

V_CC= 4.5 V

7

-

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

13 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

Table 6.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 18.

Symbol Parameter Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

t_su

set-up time Dn to SI; see Figure 17

V_CC= 4.5 V

5

14

-

4

-

4

-

ns

t_h

hold time

Dn to SI; see Figure 17

V_CC= 4.5 V

27

16

34

41

f_max

maximum

frequency

SI, SO using flags or

burst mode; see Figure 8

and Figure 11; see

Figure 12 and Figure 13

V_CC= 4.5 V

-

28

31

-

12

-

10

-

MHz

V_CC= 5 V; C_L= 15 pF

SI, SO cascaded; see

Figure 8 and Figure 11

V_CC= 4.5 V

-

28

-

12

-

10

-

MHz

pF

[7]

C_PD

power

V_I= GND to V_CC 1.5 V

145

dissipation

capacitance

[1] t_pdis the same as t_PLHand t_PHL

[2] t_enis the same as t_PZHand t_PZL

[3] _disis the same as t_PLZand t_PHZ

[4] t_tis the same as t_THLand t_TLH

.

t

.

[5] This is the ripple through delay.

[6] This is the bubble-up delay.

[7]

C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

(C_L V_CC² f_o) = sum of outputs.

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

14 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

11. Waveforms

11.1 Master reset applied with FIFO full

ꢋꢃꢎ

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0

W

:

W

3/+

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9

0

ꢋꢂꢎ

ꢋꢁꢎ

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3+/

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Measurement points are given in Table 7.

V

_OLand V_OHare typical voltage output levels that occur with the output load.

(1) DIR LOW; output ready HIGH; assume that FIFO is full

(2) MR pulse HIGH; clears FIFO

(3) DIR goes HIGH; flag indicates input prepared for valid data

(4) DOR goes LOW; flag indicates FIFO empty

Fig 7. Propagation delay MR input to DIR output, DOR output and Qn outputs and the MR pulse width.

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

15 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

11.2 Shifting in sequence FIFO empty to FIFO full

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0

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:

3+/

ꢋꢁꢎ

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',5ꢉRXWSXW

'QꢉLQSXW

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Measurement points are given in Table 7.

V_OLand V_OHare typical voltage output levels that occur with the output load.

(1) DIR initially HIGH; FIFO is prepared for valid data

(2) SI set HIGH; data loaded into input stage

(3) DIR drops LOW; input stage “busy”

(4) DIR goes HIGH; status flag indicates FIFO prepared for additional data

(5) SI set LOW; data from first location “ripple through”

(6) To load 2^ndword through to 16^thword into FIFO, repeat the process.

(7) DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.

Fig 8. Propagation delay SI input to DIR output, the SI pulse width and the SI maximum frequency

Table 7.

Type

Measurement points

Input

V_M

Output

V_M

V_X

V_Y

74HC40105

0.5V_CC

1.3 V

0.1V_CC

0.9V_CC

74HCT40105

1.3 V

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

16 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

11.3 With FIFO full; SI held HIGH in anticipation of empty location

ꢋꢃꢎ

9

0

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6,ꢉꢉ,1387

9

ꢋꢁꢎ

0

ꢋꢅꢎ

W

:

3/+

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GHOD\

9

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Measurement points are given in Table 7.

V_OLand V_OHare typical voltage output levels that occur with the output load.

(1) FIFO is initially full, shift-in is held HIGH

(2) SO pulse; data in output stage is unloaded, “bubble-up” process of empty location begins

(3) DIR HIGH; when empty location reaches input stage, flag indicates that FIFO is prepared for data input

(4) DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again

(5) SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full

Fig 9. Bubble-up delay SO input to DIR output, the DIR pulse width.

11.4 SO input to Qn outputs propagation delay

9

62ꢉꢉꢉ,1387

0

W

3+/

3/+

ꢈꢀꢉꢑ

9

4Qꢉ287387

0

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PJDꢅꢅꢇ

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7+/

7/+

Measurement points are given in Table 7.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 10. Propagation delay SO input to Qn outputs and the output transition time

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

17 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

11.5 Shifting out sequence; FIFO full to FIFO empty

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9

0

ꢋꢂꢎ

ꢋꢆꢎ

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:

W

3/+

ꢋꢅꢎ

ꢋꢁꢎ

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0

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4QꢉRXWSXW

0

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Measurement points are given in Table 7.

V_OLand V_OHare typical voltage output levels that occur with the output load.

(1) DOR HIGH; no data transfer in progress, valid data is present at the output stage

(2) SO set HIGH; result in DOR going LOW

(3) SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input stage

(4) DOR drops LOW; output stage “busy”

(5) DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay

(6) To unload the 3^rdthrough the 16^thword from FIFO, repeat the process

(7) DOR remains LOW; FIFO is empty

Fig 11. Propagation delay SO input to DOR output, the SO pulse width and the SO maximum frequency.

11.6 Shift-in operation; high-speed burst mode

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Measurement points are given in Table 7.

V_OLand V_OHare typical voltage output levels that occur with the output load.

In the high-speed mode, the minimum shift-in HIGH and shift-in LOW specifications determines the burst-in rate. The DIR

status flag is a “don’t care” condition, and a shift-in pulse can be applied regardless of the flag. An SI pulse which would

overflow the storage capacity of the FIFO is ignored.

Fig 12. The SI pulse width and the SI maximum frequency, in high-speed shift-in burst mode

74HC_HCT40105

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Product data sheet

Rev. 3 — 25 September 2013

18 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

11.7 Shift-out operation; high-speed burst mode

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Measurement points are given in Table 7.

V_OLand V_OHare typical voltage output levels that occur with the output load.

In the high-speed mode, the minimum shift-out HIGH and shift-out LOW specifications determine the burst-out rate. The DOR

flag is a “don’t care” condition, and an SO pulse can be applied without regard to the flag.

Fig 13. The SO pulse width and the SO maximum frequency, in high-speed shift-out burst mode

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

19 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

11.8 With FIFO empty; SO is held HIGH in anticipation

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Measurement points are given in Table 7.

_OLand V_OHare typical voltage output levels that occur with the output load.

V

(1) FIFO is initially empty. SO is held HIGH.

(2) SI pulse; loads data into FIFO and initiates ripple through process

(3) Output transition; data arrives at output stage after the specified propagation delay between the rising and falling edge of the

DOR pulse to the Qn output

(4) DOR flag signals the arrival of valid data at the output stage

(5) SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty

(6) DOR goes LOW; data shift-out is completed, FIFO is empty again

Fig 14. Ripple through delay SI input to DOR output, propagation delay DOR input to Qn outputs and the DOR

pulse width

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

20 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

11.9 MR to SI recovery time

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Measurement points are given in Table 7.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 15. MR to SI recovery time

11.10 Enable and disable times

V

I

OE input

V

M

GND

t

PZL

PLZ

V

CC

Qn output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

Qn output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aah078

Measurement points are given in Table 7.

V

_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 16. Enable and disable times

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

21 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

11.11 Set-up and hold times

9

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VX

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Measurement points are given in Table 7.

_OLand V_OHare typical voltage output levels that occur with the output load.

The shaded areas indicate when the output is permitted to change for predictable output performance

V

Fig 17. Set-up and hold times

11.12 Test circuit for measuring switching times

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

CC

V

O

I

R

L

S1

G

open

DUT

R

T

C

L

001aad983

Test data is given in Table 8.

Definitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

R_L= Load resistance.

S1 = Test selection switch.

Fig 18. Test circuit for measuring switching times

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

22 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

Table 8.

Type

Test data

Input

Load

S1 position

V_I

t_r, t_f

6 ns

C_L

R_L

t_PHL, t_PLH

open

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

V_CC

74HC40105

V_CC

3 V

15 pF, 50 pF

1 k

74HCT40105

open

GND

V_CC

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

23 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

12. Application information

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The 74HC40105; 74HCT40105 is easily expanded to increase word length. Composite DIR and DOR flags are formed with the

addition of an AND gate. The basic operation and timing are identical to a single FIFO, except for an added gate delay on the

flags.

Fig 19. Expanded FIFO for increased word length; 16 words x 8 bits

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This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are

started (see Figure 9).

Fig 20. Expanded FIFO for increased word length

12.1 Expanded format

Figure 21 shows two cascaded FIFOs providing a capacity of 32 words x 4 bits. Figure 22

shows the signals on the nodes of both FIFOs after the application of the SI pulse, when

both FIFOs are initially empty. After a ripple through delay, data arrives at the output of

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

24 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The DORA pulse width and

the timing between the rising edge of DORA and QnA satisfy the requirements of SIB and

DnB. After a second ripple through delay data arrives at the output of FIFOB.

Figure 23 shows the signals on the nodes of both FIFOs after the application of the SOB

pulse, when both FIFOs are initially full. After a bubble-up delay, a DIRB pulse is

generated, which acts as a SOA pulse for FIFOA. One word is transferred from the output

of FIFOA to the input of FIFOB. The pulse width of DORB satisfy the requirements of the

SOA pulse for FIFOA. After a second bubble-up delay, an empty space arrives at DnA, at

which time DIRA goes HIGH. Figure 24 shows the waveforms at all external nodes of both

FIFOs during a complete shift-in and shift-out sequence.

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The 74HC40105; 74HCT40105 is easily cascaded to increase word capacity without external circuitry. In cascaded format, the

FIFOs handle all necessary communications. Figure 19 and Figure 21 demonstrate the communication timing between FIFOA

and FIFOB. Figure 24 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and shifted empty

again.

Fig 21. Cascading for increased word capacity; 32 words x 4 bits

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

25 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

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(1) FIFOA and FIFOB are initially empty, SOA held HIGH in anticipation of data

(2) Load one word into FIFOA; SI pulse; applied. results in DIR pulse

(3) Data-out A/ data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data

input set-up requirements of FIFOB.

(4) DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output

ready pulse, data is shifted into FIFOB

(5) DIRB and SOA go LOW; flag indicates that input stage of FIFOB is busy, shift-out of FIFOA is complete

(6) DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in anticipation

of additional data

(7) DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output

stage

Fig 22. FIFO to FIFO communication; input timing under empty condition

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

26 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

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(1) FIFOA and FIFOB initially empty, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up

(2) Unload one word from FIFOB; SO pulse applied, results in DOR pulse

(3) DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse, data is

shifted out of FIFOA

(4) DORA and SIB go LOW; flag indicates that the output stage of FIFOA is busy, shift-in of FIFOB is complete

(5) DORA and SIB go HIGH; flag indicates that valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting

bubble-up of empty location.

(6) DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA

Fig 23. FIFO to FIFO communication; output timing under full condition

74HC_HCT40105

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 September 2013

27 of 37

74HC40105; 74HCT40105

NXP Semiconductors

4-bit x 16-word FIFO register

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型号：	74HC40105N,652
厂家：	NXP
描述：	74HC(T)40105 - 4-bit x 16-word FIFO register DIP 16-Pin 时钟先进先出芯片光电二极管内存集成电路
文件：	总37页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC40105N,652 [NXP]

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