74HC4020N,652 [NXP]
74HC4020; 74HCT4020 - 14-stage binary ripple counter DIP 16-Pin;型号: | 74HC4020N,652 |
厂家: | NXP |
描述: | 74HC4020; 74HCT4020 - 14-stage binary ripple counter DIP 16-Pin 光电二极管 输出元件 逻辑集成电路 触发器 |
文件: | 总20页 (文件大小:211K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC4020; 74HCT4020
14-stage binary ripple counter
Rev. 5 — 6 August 2012
Product data sheet
1. General description
The 74HC4020; 74HCT4020 are high-speed Si-gate CMOS devices and are pin
compatible with the HEF4020B series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4020; 74HCT4020 are 14-stage binary ripple counters with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0, Q3
to Q13). The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
2. Features and benefits
Multiple package options
Complies with JEDEC standard no. 7A
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74HC4020N
74HCT4020N
74HC4020D
74HCT4020D
74HC4020DB
74HCT4020DB
40 C to +125 C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
40 C to +125 C
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SSOP16
plastic shrink small outline package; 16 leads; body SOT338-1
width 5.3 mm
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
Table 1.
Ordering information …continued
Type number
Package
Temperature range
Name
Description
Version
74HC4020PW 40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
74HCT4020PW
74HC4020BQ
74HCT4020BQ
40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
5. Functional diagram
10
11
CP
T
14-STAGE COUNTER
MR
C
D
9
7
5
4
6
13 12 14 15
1
2
3
Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13
001aal201
Fig 1. Functional diagram
CTR14
+
Q0
Q3
Q4
Q5
9
10
11
0
9
7
CT = 0
7
5
5
4
4
10
11
CP
Q6
Q7
6
6
13
12
14
15
1
13
12
14
15
1
CT
Q8
Q9
MR
Q10
Q11
Q12
Q13
2
2
3
13
3
001aal202
001aal203
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
2 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
FF
1
FF
2
FF
3
FF
4
FF
6
CP
T
T
T
T
T
RD
RD
RD
RD
RD
MR
Q0
Q3
Q13
001aal204
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
74HC4020
74HCT4020
terminal 1
index area
74HC4020
74HCT4020
2
3
4
5
6
7
15
14
13
12
11
10
Q12
Q10
Q9
Q13
Q5
Q4
Q6
Q3
1
2
3
4
5
6
7
8
16
V
Q11
Q12
Q13
Q5
CC
15
14
13
12
11
10
9
Q7
Q10
Q9
Q7
Q8
MR
CP
Q0
Q8
(1)
MR
CP
V
CC
Q4
Q6
Q3
001aal206
GND
Transparent top view
001aal205
(1) The substrate is attached to this pad using conductive
die attach material. It cannot be used as supply pin or
input. It is recommended that no connection is made at
all.
Fig 5. Pin configuration DIP16, SO16, SSOP16 and
TSSOP16
Fig 6. Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
Q0, Q3 to Q13
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3
output
GND
CP
8
ground (0 V)
10
11
16
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
positive supply voltage
MR
VCC
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
3 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
7. Functional description
Table 3.
Function table
Input
CP
Output
Q0, Q3 to Q13
no change
count
MR
L
L
X
H
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition.
7.1 Timing diagram
1
2
4
8
16
32
64 128 256 512 1024 2048 4096 8192 16384
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aal207
Fig 7. Timing diagram
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
4 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VI < 0.5 V or VI > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
50
50
+150
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
DIP16 package
65
[1]
Tamb = 40 C to +125 C
-
-
750
500
mW
mW
SO16, SSOP16, TSSOP16 and
DHVQFN16 packages
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
74HC4020
74HCT4020
Unit
Min
2.0
0
Typ
Max
6.0
Min
4.5
0
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
output voltage
5.0
5.0
V
V
V
-
-
VCC
VCC
-
-
VCC
VCC
VO
0
0
t/V
input transition rise and
fall rate
except for
Schmitt trigger inputs
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
625
139
83
-
-
-
ns/V
-
-
1.67
-
-
-
1.67
-
139 ns/V
ns/V
+125 C
-
Tamb
ambient temperature
40
+25
+125
40
+25
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
5 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC4020
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
O = 20 A; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
V
I
V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
8.0
-
A
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
-
-
80
-
-
-
160
-
A
input
3.5
pF
capacitance
74HCT4020
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 4.5 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
0.15 0.26
0.1
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
A
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
6 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
A
ICC
additional
VI = VCC 2.1 V; IO = 0 A;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pin MR
pin CP
-
-
-
110
85
396
306
-
-
-
-
495
383
-
-
-
-
539
417
-
A
A
pF
CI
input
3.5
capacitance
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC4020
[1]
tpd
propagation
delay
CP to Q0; see Figure 8
VCC = 2.0 V; CL = 50 pF
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V; CL = 50 pF
Qn to Qn+1; see Figure 9
VCC = 2.0 V; CL = 50 pF
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V; CL = 50 pF
-
-
-
-
39 140
-
-
-
-
175
35
-
-
-
-
-
210
42
-
ns
ns
ns
ns
14
11
11
28
-
24
30
36
-
-
-
-
22
8
75
15
-
-
-
-
-
95
19
-
-
-
-
-
110
22
-
ns
ns
ns
ns
6
6
13
16
19
tPHL
HIGH to LOW MR to Qn; see Figure 8
propagation
delay
VCC =2.0 V; CL = 50 pF
-
-
-
-
55 170
-
-
-
-
215
43
-
-
-
-
-
225
51
-
ns
ns
ns
ns
VCC = 4.5 V; CL = 50 pF
20
17
16
34
-
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V; CL = 50 pF
29
37
43
[2]
tt
transition
time
Qn; see Figure 8
VCC = 2.0 V; CL = 50 pF
VCC = 4.5 V; CL = 50 pF
VCC = 6.0 V; CL = 50 pF
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
6
19
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
7 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
tW
pulse width
CP HIGH or LOW;
see Figure 8
VCC = 2.0 V; CL = 50 pF
VCC = 4.5 V; CL = 50 pF
VCC = 6.0 V; CL = 50 pF
MR HIGH; see Figure 8
VCC = 2.0 V; CL = 50 pF
VCC = 4.5 V; CL = 50 pF
VCC = 6.0 V; CL = 50 pF
80
16
14
14
4
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
3
17
20
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
5
17
20
trec
recovery time MR to CP; see Figure 8
VCC = 2.0 V; CL = 50 pF
50
10
9
6
2
2
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
VCC = 4.5 V; CL = 50 pF
VCC = 6.0 V; CL = 50 pF
fmax
maximum
frequency
see Figure 8
VCC = 2.0 V; CL = 50 pF
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V; CL = 50 pF
6.0
30
-
30
92
-
-
-
-
-
4.8
24
-
-
-
-
-
-
4.0
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
101
35 109
28
-
24
-
[3]
[1]
CPD
power
-
19
dissipation
capacitance
74HCT4020
tpd
propagation
delay
CP to Q0; see Figure 8
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
Qn to Qn+1; see Figure 9
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
-
-
18
15
36
-
-
-
45
-
-
-
54
-
ns
ns
-
-
8
6
15
-
-
-
19
-
-
-
22
-
ns
ns
tPHL
HIGH to LOW MR to Qn; see Figure 8
propagation
delay
VCC = 4.5 V; CL = 50 pF
-
-
22
19
45
-
-
-
56
-
-
-
68
-
ns
ns
VCC = 5.0 V; CL = 15 pF
[2]
tt
transition
time
Qn; see Figure 8
VCC = 4.5 V; CL = 50 pF
-
7
15
-
19
-
22
ns
tW
pulse width
CP HIGH or LOW;
see Figure 8
VCC = 4.5 V; CL = 50 pF
MR HIGH; see Figure 8
VCC = 4.5 V; CL = 50 pF
20
20
10
7
8
2
-
-
-
25
25
13
-
-
-
30
30
15
-
-
-
ns
ns
ns
trec
recovery time MR to CP; see Figure 8
VCC = 4.5 V; CL = 50 pF
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
8 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
fmax
maximum
frequency
see Figure 8
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
25
-
47
52
20
-
-
-
20
-
-
-
-
17
-
-
-
-
MHz
MHz
pF
[3]
CPD
power
-
-
-
dissipation
capacitance
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
V
V
I
I
V
M
MR input
CP input
t
1/f
max
W
t
rec
V
M
t
W
t
t
t
PHL
PHL
PLH
90 %
90 %
Q0 or Qn
output
V
M
10 %
10 %
t
t
TLH
THL
001aad590
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Clock timing, propagation delays, pulse widths and measurement points
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
9 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
V
OH
Qn output
V
M
V
OL
t
t
PLH
PHL
V
OH
V
Qn+1 output
M
V
OL
001aai120
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Waveforms showing the output Qn to output Qn+1 propagation delays
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC4020
0.5 VCC
1.3 V
0.5 VCC
1.3 V
74HCT4020
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
10 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 10. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
Load
VI
tr, tf
6 ns
6 ns
CL
74HC4020
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
74HCT4020
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
11 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 11. Package outline SOT38-4 (DIP16)
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
12 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 12. Package outline SOT109-1 (SO16)
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
13 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 13. Package outline SOT338-1 (SSOP16)
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
14 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 14. Package outline SOT403-1 (TSSOP16)
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
15 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 15. Package outline SOT763-1 (DHVQFN16)
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
16 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
14. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Abbreviation
Complementary Metal Oxide Semiconductor
Device Under Test
15. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change
notice
Supersedes
74HC_HCT4020 v.5
Modifications:
20120806
Product data sheet
-
74HC_HCT4020 v.4
• Measurement points added to figure 8 (errata).
74HC_HCT4020 v.4
Modifications:
20111213
• Legal pages updated.
20100120 Product data sheet
Product specification
Product data sheet
-
74HC_HCT4020 v.3
74HC_HCT4020 v.3
-
-
74HC_HCT4020_CNV v.2
-
74HC_HCT4020_CNV v.2 19970901
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
17 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
18 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT4020
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 August 2012
19 of 20
74HC4020; 74HCT4020
NXP Semiconductors
14-stage binary ripple counter
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 August 2012
Document identifier: 74HC_HCT4020
相关型号:
74HC4020PW-T
IC HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16, Counter
NXP
74HC4020U
IC HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, UUC, CHIP ON WAFER, Counter
NXP
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