74HC4040D,653_技术文档

74HC4040; 74HCT4040

12-stage binary ripple counter

Rev. 4 — 20 March 2014

Product data sheet

1. General description

The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP),

an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to

Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears

all counter stages and forces all outputs LOW, independent of the state of CP. Each

counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of

current limiting resistors to interface inputs to voltages in excess of V_CC

.

2. Features and benefits

 Complies with JEDEC standard no. 7A

 Input levels:

 For 74HC4040: CMOS level

 For 74HCT4040: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

3. Applications

 Frequency dividing circuits

 Time delay circuits

 Control counters

4. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74HC4040N

74HCT4040N

74HC4040D

74HCT4040D

74HC4040DB

74HCT4040DB

40 C to +125 C

DIP16

plastic dual in-line package; 16 leads (300 mil);

long body

SOT38-1

40 C to +125 C

SO16

plastic small outline package; 16 leads; body

width 3.9 mm

SOT109-1

SSOP16

plastic shrink small outline package; 16 leads; body SOT338-1

width 5.3 mm

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

Table 1.

Ordering information …continued

Type number

Package

Temperature range

Name

Description

Version

74HC4040PW 40 C to +125 C

TSSOP16

plastic thin shrink small outline package; 16 leads; SOT403-1

body width 4.4 mm

74HCT4040PW

74HC4040BQ

74HCT4040BQ

40 C to +125 C

DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 16 terminals;

body 2.5  3.5  0.85 mm

SOT763-1

5. Functional diagram

10

11

CP

T

12-STAGE COUNTER

MR

C

D

9

7

6

5

3

2

4

13 12 14 15

1

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11

001aad589

Fig 1. Functional diagram

CTR12

Q0

Q1

Q2

9

7

6

0

9

7

6

+

10

11

CT = 0

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

5

3

2

4

13

12

14

15

1

5

3

2

4

13

12

14

15

1

10

11

CP

CT

MR

11

001aad585

001aad586

Fig 2. Logic symbol

Fig 3. IEC logic symbol

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

2 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

Q

FF

1

FF

2

FF

3

FF

4

FF

5

FF

6

T

CP

RD

MR

Q0

Q1

Q2

Q3

Q4

Q5

Q

FF

7

FF

8

FF

9

FF

10

FF

11

FF

12

T

RD

Q6

Q7

Q8

Q9

Q10

Q11

001aad588

Fig 4. Logic diagram

6. Pinning information

6.1 Pinning

terminal 1

index area

2

3

4

5

6

7

15

Q5

Q10

Q9

14

Q4

Q6

Q3

Q2

Q1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Q11

Q5

V

CC

13

12

11

10

Q7

Q10

Q9

Q7

Q8

MR

CP

Q0

4040

Q4

Q8

Q6

MR

CP

(1)

GND

4040

Q3

Q2

Q1

001aad584

GND

Transparent top view

001aad583

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration DIP16, SO16, SSOP16 and

TSSOP16

Fig 6. Pin configuration DHVQFN16

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

3 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

6.2 Pin description

Table 2.

Symbol

Q11

Q5

Pin description

1

Description

output 11

output 5

2

Q4

3

output 4

Q6

4

output 6

Q3

5

output 3

Q2

6

output 2

Q1

7

output 1

GND

Q0

8

ground (0 V)

output 0

9

CP

10

11

12

13

14

15

16

clock input (HIGH-to-LOW, edge-triggered)

MR

master reset input (active HIGH)

output 8

Q8

Q7

output 7

Q9

output 9

Q10

V_CC

output 10

positive supply voltage

7. Functional description

7.1 Function table

Table 3.

Function table

Input

CP



Output

Q0 to Q11

no change

count

MR

L



L

X

H

L

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition.

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

4 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

7.2 Timing diagram

1

2

4

8

16

32

64 128 256 512 1024 2048 4096

CP input

MR input

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

001aad587

Fig 7. Timing diagram

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+7

Unit

V

supply voltage

0.5

input clamping current

output clamping current

output current

V_I< 0.5 V or VI > V_CC+ 0.5 V

V_I< 0.5 V or V_I> V_CC+ 0.5 V

0.5 V < V_O< V_CC+ 0.5 V

-

20

25

50

+150

mA

C

I_OK

-

I_O

-

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

-

storage temperature

total power dissipation

DIP16 package

65

[1]

T_amb= 40 C to +125 C

-

750

500

mW

SO16, SSOP16, TSSOP16 and

DHVQFN16 packages

[1] For DIP16 packages: above 70 C, P_totderates linearly with 12 mW/K.

For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70 C, P_totderates linearly with 8 mW/K.

74HC_HCT4040

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 March 2014

5 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

9. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions

74HC4040

74HCT4040

Unit

Min

Typ

Max

6.0

Min

Typ

Max

5.5

V_CC

+125

-

V_CC

V_I

supply voltage

2.0

5.0

4.5

5.0

V

input voltage

0

-

V_CC

+125

625

139

83

0

-

V

V_O

output voltage

0

-

0

-

V

T_amb

t/V

ambient temperature

input transition rise and fall rate V_CC= 2.0 V

V_CC= 4.5 V

40

+25

40

+25

C

-

ns/V

1.67

-

1.67

-

139

-

V_CC= 6.0 V

10. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 C

Min Typ

40 C to +85 C 40 C to +125 C Unit

Max

Min

Max

Min

Max

74HC4040

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

1.5

1.2

2.4

3.2

0.8

-

1.5

-

1.5

-

V

V_CC= 4.5 V

3.15

V_CC= 6.0 V

4.2

-

4.2

-

4.2

-

V_IL

LOW-level

input voltage

V_CC= 2.0 V

-

0.5

-

0.5

1.35

1.8

-

0.5

1.35

1.8

V_CC= 4.5 V

2.1 1.35

V_CC= 6.0 V

2.8

1.8

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

1.9

4.4

5.9

2.0

4.5

6.0

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

5.9

I_O= 4.0 mA; V_CC= 4.5 V 3.98 4.32

I_O= 5.2 mA; V_CC= 6.0 V 5.48 5.81

V_I= V_IHor V_IL

3.84

5.34

V_OL

LOW-level

output voltage

I_O= 20 A; V_CC= 2.0 V

I_O= 20 A; V_CC= 4.5 V

I_O= 20 A; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

-

0

0.1

-

0.1

-

0.1

0.4

1.0

V

0.1

V

0.15 0.26

0.16 0.26

0.33

1.0

V

I_I

input leakage

current

V_I= V_CCor GND;

V_CC= 6.0 V

-

0.1

A

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

8.0

-

80

-

160

A

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

6 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

Table 6.

Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 C

Min Typ

40 C to +85 C 40 C to +125 C Unit

Max

Min

Max

Min

Max

C_I

input

-

3.5

-

pF

capacitance

74HCT4040

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

1.6

1.2

-

2.0

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 A

4.4

4.5

-

4.4

-

4.4

3.7

-

V

I_O= 4 mA

3.98 4.32

3.84

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 A

-

0

0.1

-

0.1

-

0.1

0.4

V

I_O= 4.0 mA

0.15 0.26

0.33

1.0

V

I_I

input leakage

current

V_I= V_CCor GND;

V_CC= 5.5 V

-

0.1

1.0

A

I_CC

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

-

8.0

-

80

-

160

A

additional

per input pin;

supply current V_I= V_CC 2.1 V; I_O= 0 A;

other inputs at V_CCor GND;

V_CC= 4.5 V to 5.5 V

pin CP

pin MR

-

85

110

3.5

306

396

-

383

495

-

417

539

A

pF

C_I

input

-

capacitance

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

7 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

11. Dynamic characteristics

Table 7.

Dynamic characteristics

GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 9.

Symbol Parameter

Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

74HC4040

[1]

t_pd

propagation

delay

CP to Q0; see Figure 8

V_CC= 2.0 V

-

47

17

14

150

30

-

190

38

-

225

45

ns

V_CC= 4.5 V

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

-

26

33

38

Qn to Qn+1; see Figure 8

V_CC= 2.0 V

-

28

10

8

100

20

-

125

25

-

150

30

-

ns

V_CC= 4.5 V

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

-

8

17

21

26

t_PHL

HIGH to LOW MR to Qn; see Figure 8

propagation

delay

V_CC= 2.0 V

-

61

22

18

185

37

-

230

46

-

280

ns

V_CC= 4.5 V

56

48

V_CC= 6.0 V

transition time Qn; see Figure 8

V_CC= 2.0 V

31

39

[2]

t_t

-

19

7

75

15

13

-

95

19

16

-

110

22

ns

V_CC= 4.5 V

V_CC= 6.0 V

6

19

t_W

pulse width

CP input, HIGH or LOW;

see Figure 8

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

80

16

14

5

-

100

20

-

120

24

-

ns

-

4

17

20

MR input, HIGH;

see Figure 8

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

80

16

14

22

8

-

100

20

-

120

24

-

ns

6

17

20

t_rec

recovery time MR to CP; see Figure 8

V_CC= 2.0 V

50

10

9

8

3

2

-

65

-

75

15

13

-

ns

V_CC= 4.5 V

13

11

V_CC= 6.0 V

f_max

maximum

frequency

CP input; see Figure 8

V_CC= 2.0 V

6

27

82

-

4.8

24

-

4

-

MHz

V_CC= 4.5 V

30

-

20

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

90

98

-

35

28

24

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

8 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

Table 7.

Dynamic characteristics …continued

GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit, see Figure 9.

Symbol Parameter

Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

Max

Min

Max

[3]

[1]

C_PD

power

dissipation

capacitance

V_I= GND to V_CC

-

20

-

pF

74HCT4040

t_pd

propagation

delay

CP to Q0; see Figure 8

V_CC= 4.5 V

-

19

40

-

50

-

60

ns

V_CC= 5.0 V; C_L= 15 pF

Qn to Qn+1; see Figure 8

V_CC= 4.5 V

16

-

10

8

20

-

25

-

30

-

ns

V_CC= 5.0 V; C_L= 15 pF

t_PHL

HIGH to LOW MR to Qn; see Figure 8

propagation

delay

V_CC= 4.5 V

-

23

7

45

15

-

56

19

-

68

22

ns

[2]

t_t

transition time Qn; see Figure 8

V_CC= 4.5 V

t_W

pulse width

CP input, HIGH or LOW;

see Figure 8

V_CC= 4.5 V

16

7

-

20

-

24

-

ns

MR input, HIGH;

see Figure 8

V_CC= 4.5 V

16

10

6

2

-

ns

t_rec

recovery time MR to CP; see Figure 8

V_CC= 4.5 V

13

15

20

f_max

maximum

frequency

CP input; see Figure 8

V_CC= 4.5 V

30

-

72

79

-

24

-

MHz

pF

V_CC= 5.0 V; C_L= 15 pF

V_I= GND to V_CC

-

[3]

C_PD

power

-

20

dissipation

capacitance

[1] t_pdis the same as t_PHL, t_PLH

.

[2] t_tis the same as t_THL, t_TLH

.

[3] C_PDis used to determine the dynamic power dissipation (P_Din W).

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

(C_L V_CC² f_o) = sum of outputs.

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

9 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

12. Waveform and test circuit

V

I

V

M

MR input

CP input

t

1/f

W

max

t

rec

V

I

V

M

t

W

t

PHL

PLH

90 %

Q0 or Qn

output

V

M

10 %

t

TLH

THL

001aad590

74HC4040: V_M= 50 %; V_I= GND to V_CC

.

74HCT4040: V_M= 1.3 V; V_I= GND to 3 V.

Fig 8. Clock propagation delays, pulse width, transition times, maximum pulse frequency and master resets

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

10 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

t

W

V

I

90 %

negative

pulse

V

M

10 %

GND

t

r

f

t

f

r

V

I

90 %

positive

pulse

M

10 %

GND

t

W

V

CC

V

O

I

G

DUT

R

T

C

L

001aah768

Test data is given in Table 8.

Definitions test circuit:

R_T= termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= load capacitance including jig and probe capacitance.

Fig 9. Test circuit for measuring switching times

Table 8.

Type

Test data

Input

V_I

Load

Test

t_r, t_f

C_L

74HC4040

V_CC

3.0 V

6.0 ns

15 pF, 50 pF

t_PLH, t_PHL

74HCT4040

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

11 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

16

9

M

H

pin 1 index

E

1

8

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

E

max.

min.

max.

1.40

1.14

0.53

0.38

0.32

0.23

21.8

21.4

6.48

6.20

3.9

3.4

8.25

7.80

9.5

8.3

4.7

0.51

3.7

2.54

0.1

7.62

0.3

0.254

0.01

2.2

0.021

0.015

0.013

0.009

0.86

0.84

0.32

0.31

0.055

0.045

0.26

0.24

0.15

0.13

0.37

0.33

inches

0.19

0.02

0.15

0.087

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT38-1

050G09

MO-001

SC-503-16

Fig 10. Package outline SOT38-1 (DIP16)

74HC_HCT4040

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Product data sheet

Rev. 4 — 20 March 2014

12 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 11. Package outline SOT109-1 (SO16)

74HC_HCT4040

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 March 2014

13 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

8

1

detail X

w M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

mm

2

0.25

0.65

1.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT338-1

MO-150

Fig 12. Package outline SOT338-1 (SSOP16)

74HC_HCT4040

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 March 2014

14 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 13. Package outline SOT403-1 (TSSOP16)

74HC_HCT4040

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 March 2014

15 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

7

L

1

8

9

E

h

e

16

15

10

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT763-1

- - -

MO-241

- - -

Fig 14. Package outline SOT763-1 (DHVQFN16)

74HC_HCT4040

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 March 2014

16 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

14. Abbreviations

Table 9.

Acronym

CMOS

ESD

Abbreviations

Description

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

HBM

Human Body Model

CDM

Charge-Device Model

TTL

Transistor-Transistor Logic

15. Revision history

Table 10. Revision history

Document ID

Release date

20140320

Data sheet status

Product data sheet

Change notice Supersedes

- 74HC_HCT4040 v.3

74HC_HCT4040 v.4

Modifications:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

74HC_HCT4040 v.3

20050914

Product data sheet

-

74HC_HCT4040_CNV v.2

74HC_HCT4040_CNV v.2 19901231

Product specification

-

74HC_HCT4040

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 March 2014

17 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

16.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74HC_HCT4040

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 March 2014

18 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74HC_HCT4040

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 March 2014

19 of 20

74HC4040; 74HCT4040

NXP Semiconductors

12-stage binary ripple counter

18. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.2

Functional description . . . . . . . . . . . . . . . . . . . 4

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . 5

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveform and test circuit. . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 19

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 20 March 2014

Document identifier: 74HC_HCT4040


型号：	74HC4040D,653
厂家：	NXP
描述：	74HC(T)4040 - 12-stage binary ripple counter SOP 16-Pin 光电二极管逻辑集成电路触发器
文件：	总20页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC4040D,653 [NXP]

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