74HC4050 [NXP]
Hex high-to-low level shifter; 六角高到低电平转换器
| 型号： | 74HC4050 |
| 厂家： | 
NXP |
| 描述： | Hex high-to-low level shifter |
| 文件： | 总7页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC4050
Hex high-to-low level shifter
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Hex high-to-low level shifter
74HC4050
therefore be used. This feature enables the non-inverting
buffers to be used as logic level translators, which will
convert high level logic to low level logic, while operating
from a low voltage power supply. For example 15 V logic
(“4000B series”) can be converted down to 2 V logic.
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The actual input switch level remains related to the VCC
and is the same as mentioned in the family characteristics.
The 74HC4050 is a high-speed Si-gate CMOS device and
is pin compatible with the “4050” of the “4000B” series. It
is specified in compliance with JEDEC standard no. 7A.
APPLICATIONS
The 74HC4050 provides six non-inverting buffers with a
modified input protection structure, which has no diode
connected to VCC. Input voltages of up to 15 V may
• Converting 15 V logic (“4000B” series) down to 2 V logic.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
tPHL / tPLH
CI
propagation delay nA to nY
input capacitance
CL = 15 pF; VCC = 5 V
7
ns
pF
pF
3.5
14
CPD
power dissipation capacitance per buffer
note 1
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi +∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Hex high-to-low level shifter
74HC4050
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
positive supply voltage
1
VCC
2, 4, 6, 10, 12, 15
1Y to 6Y
1A to 6A
GND
data outputs
data inputs
3, 5, 7, 9, 11, 14
8
ground (0 V)
not connected
13, 16
n.c.
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Hex high-to-low level shifter
74HC4050
Fig.5 Input protection for HC4050. Single sided
thick oxide field effect metal gate transistor as
input protection.
Fig.4 Functional diagram.
Fig.6 Logic diagram (one level shifter).
FUNCTION TABLE (1)
INPUT
nA
OUTPUT
nY
L
L
H
H
Note
1. H = HIGH voltage level
L = LOW voltage level
December 1990
4
Philips Semiconductors
Product specification
Hex high-to-low level shifter
74HC4050
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
DC supply voltage
MIN. MAX. UNIT
CONDITIONS
VCC
VIK
−0.5
−0.5
+7
V
DC input voltage range
DC input diode current
DC output diode current
+16
20
V
−IIK
±IOK
±IO
mA
mA
for VI < −0.5 V
20
for VO < −0.5 V or VO > VCC + 0.5 V
for −0.5 V < VO < VCC + 0.5 V
DC output source or sink current
- standard outputs
25
mA
DC VCC or GND current for types
with:
- standard outputs
±ICC
±IGND
;
50
mA
Tstg
storage temperature range
−65
+150 °C
power dissipation per package
for temperature range: −40 to +125 °C
74HC
Ptot
plastic DIL
750
500
mW
above +70 °C: derate linearly with 12 mW/K
above +70 °C: derate linearly with 8 mW/K
plastic mini-pack (SO)
mW
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER
VCC
74HC
typ.
UNIT
CONDITIONS
min.
2.0
GND
max.
6.0
DC supply voltage
DC input voltage range
5.0
V
VI
−
15
V
Tamb
Tamb
operating ambient temperature range −40
operating ambient temperature range −40
+85
+125
°C
°C
see DC and AC
characteristics
1000
500
400
650
1000
VCC = 2.0 V; VIN = 2.0 V
VCC = 4.5 V; VIN = 4.5 V
VCC = 6.0 V; VIN = 6.0 V
VCC = 6.0 V; VIN = 10.0 V
VCC = 6.0 V; VIN = 15.0 V
tr, tf
input rise and fall times
6.0
ns
December 1990
5
Philips Semiconductors
Product specification
Hex high-to-low level shifter
74HC4050
DC CHARACTERISTICS FOR 74HC
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
VCC
(V)
−40 to +85 −40 to +125
+25
VI
OTHER
min. typ. max. min. max. min. max.
VIH
HIGH level input
voltage
1.5 1.3
3.15 2.4
4.2 3.1
1.5
3.15
4.2
1.5
3.15
4.2
V
2.0
4.5
6.0
VIL
LOW level input
voltage
0.7 0.5
1.8 1.35
2.3 1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
2.0
4.5
6.0
VOH
VOH
VOL
VOL
± II
HIGH level output
voltage - all outputs
1.9 2.0
4.4 4.5
5.9 6.0
1.9
4.4
5.9
1.9
4.4
5.9
V
2.0 VIH
4.5 or
6.0 VIL
−IO = 20 µA
−IO = 20 µA
−IO = 20 µA
HIGH level output
voltage - standard
outputs
3.98
5.48
3.84
5.34
3.7
5.2
V
4.5 VIH
6.0 or
VIL
−IO = 4.0 mA
−IO = 5.2 mA
LOW level output
voltage - all outputs
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
2.0 VIH
4.5 or
6.0 VIL
IO = 20 µA
IO = 20 µA
IO = 20 µA
LOW level output
voltage - standard
outputs
0.26
0.26
0.33
0.33
0.4
0.4
V
4.5 VIH
6.0 or
VIL
IO = 4.0 mA
IO = 5.2 mA
input leakage current
0.1
0.5
2.0
1.0
1.0
5.0
µA
µA
VCC
6.0 or
GND
5.0
2.0 15 V
to
6.0
ICC
quiescent supply
current
20.0
40.0 µA
6.0 15 V
or
GND
December 1990
6
Philips Semiconductors
Product specification
Hex high-to-low level shifter
74HC4050
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
UNIT
74HC
SYMBOL
PARAMETER
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA to nY
25
9
7
85
17
14
105
21
18
130
26
22
ns
ns
2.0 Fig.7
4.5
6.0
tTHL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.7
4.5
6.0
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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