74HC573D/T3 [NXP]
IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, Bus Driver/Transceiver;型号: | 74HC573D/T3 |
厂家: | NXP |
描述: | IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, Bus Driver/Transceiver 驱动 光电二极管 输出元件 逻辑集成电路 |
文件: | 总26页 (文件大小:145K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Rev. 03 — 17 January 2006
Product data sheet
1. General description
The 74HC573; 74HCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type
inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable
(LE) input and an output enable (OE) input are common to all latches.
When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time its corresponding D input
changes.
When LE is LOW the latches store the information that was present at the D-inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
The 74HC573; 74HCT573 is functionally identical to:
• 74HC563; 74HCT563, but inverted outputs
• 74HC373; 74HCT373, but different pin arrangement
2. Features
■ Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
■ Useful as input or output port for microprocessors and microcomputers
■ 3-state non-inverting outputs for bus oriented applications
■ Common 3-state output enable input
■ Functionally identical to 74HC563; 74HCT563 and 74HC373; 74HCT373
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM EIA/JESD22-A114-C exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Symbol Parameter
74HC573
Conditions
Min
Typ
Max
Unit
tPHL,
tPLH
propagation delay
VCC = 5 V; CL = 15 pF
Dn to Qn
-
-
-
-
14
15
3.5
26
-
-
-
-
ns
ns
pF
pF
LE to Qn
Ci
input capacitance
[1]
CPD
power dissipation
capacitance
per latch;
VI = GND to VCC
74HCT573
tPHL, propagation delay
tPLH
VCC = 5 V; CL = 15 pF
Dn to Qn
-
-
-
-
17
15
3.5
26
-
-
-
-
ns
ns
pF
pF
LE to Qn
Ci
input capacitance
[1]
CPD
power dissipation
capacitance
per latch;
VI = GND to (VCC − 1.5 V)
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC573
74HC573N
74HC573D
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
plastic small outline package; 20 leads;
body width 7.5 mm
74HC573DB
74HC573PW
74HC573BQ
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SSOP20
plastic small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
TSSOP20
plastic small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1
very thin quad flat package; no leads;
20 terminals; body 2.5 × 4.5 × 0.85 mm
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
2 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 2:
Ordering information …continued
Type number
Package
Temperature range Name
Description
Version
74HCT573
74HCT573N
74HCT573D
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
plastic small outline package; 20 leads;
body width 7.5 mm
74HCT573DB
74HCT573PW
74HCT573BQ
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SSOP20
plastic small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
TSSOP20
plastic small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1
very thin quad flat package; no leads;
20 terminals; body 2.5 × 4.5 × 0.85 mm
5. Functional diagram
2
3
4
5
6
7
8
9
19
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1 18
17
16
15
14
13
12
Q2
Q3
LATCH
1 to 8
3-STATE
OUTPUTS Q4
Q5
Q6
Q7
LE
11
1
OE
mna809
Fig 1. Functional diagram
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
3 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
11
C1
1
EN1
1
2
19
1D
OE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
5
18
17
16
6
7
8
9
15
14
13
12
LE
mna807
11
mna808
Fig 2. Logic symbol
Fig 3. IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE
LE
LE
LE
LE
LE
LE
LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae075
Fig 4. Logic diagram
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
4 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
6. Pinning information
6.1 Pinning
74HC573
74HCT573
terminal 1
index area
74HC573
74HCT573
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
20
19
18
17
16
15
14
13
12
11
OE
D0
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
3
D1
4
D2
5
D3
(1)
6
GND
D4
7
D5
8
D6
9
D7
001aae077
10
GND
001aae076
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or input
Fig 5. Pin configuration DIP20, SO20,
SSOP20 and TSSOP20
Fig 6. Pin configuration DHVQFN20
6.2 Pin description
Table 3:
Pin description
Symbol
OE
D0
Pin
1
Description
3-state output enable input (active LOW)
data input 0
2
D1
3
data input 1
D2
4
data input 2
D3
5
data input 3
D4
6
data input 4
D5
7
data input 5
D6
8
data input 6
D7
9
data input 7
GND
LE
10
11
12
13
14
ground (0 V)
latch enable input (active HIGH)
3-state latch output 7
3-state latch output 6
3-state latch output 5
Q7
Q6
Q5
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
5 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 3:
Symbol
Q4
Pin description …continued
Pin
15
16
17
18
19
20
Description
3-state latch output 4
Q3
3-state latch output 3
3-state latch output 2
3-state latch output 1
3-state latch output 0
supply voltage
Q2
Q1
Q0
VCC
7. Functional description
Table 4:
Function table[1]
Operating mode
Control
Input
Internal
latches
Output
OE
LE
Dn
L
H
l
Qn
L
Enable and read register
(transparent mode)
L
H
L
H
L
H
L
Latch and read register
L
L
L
h
l
H
L
H
Z
Latch register and disable outputs
H
h
H
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max Unit
VCC
IIK
supply voltage
−0.5 +7
V
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
-
±20
mA
mA
mA
mA
mA
IOK
IO
-
±20
±35
70
-
ICC
IGND
Tstg
quiescent supply current
ground current
-
-
−70
storage temperature
−65
+150 °C
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
6 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 5:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Ptot total power dissipation
Conditions
Min
Max Unit
[1]
[2]
[3]
[3]
[4]
DIP20 package
-
-
-
-
-
750
500
500
500
500
mW
mW
mW
mW
mW
SO20 package
SSOP20 package
TSSOP20 package
DHVQFN20 package
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO20 package: Ptot derates linearly with 8 mW/K above 70 °C.
[3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 °C
[4] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol Parameter
74HC573
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.0
5.0
6.0
V
input voltage
0
-
VCC
VCC
+125
1000
500
400
V
VO
output voltage
0
-
V
Tamb
tr, tf
ambient temperature
input rise and fall time
−40
+25
°C
ns
ns
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
6.0
-
74HCT573
VCC
supply voltage
4.5
0
5.0
-
5.5
V
VI
input voltage
VCC
VCC
+125
500
V
VO
output voltage
0
-
V
Tamb
tr, tf
ambient temperature
input rise and fall time
−40
-
+25
6.0
°C
ns
VCC = 4.5 V
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
7 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
10. Static characteristics
Table 7:
Static characteristics 74HC573
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-state input voltage
VCC = 2.0 V
1.5
3.15
4.2
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
V
V
V
V
V
V
VCC = 4.5 V
-
VCC = 6.0 V
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 2.0 V
0.5
VCC = 4.5 V
-
1.35
VCC = 6.0 V
-
1.8
VOH
VI = VIH or VIL
-
-
-
-
-
-
-
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −6.0 mA; VCC = 4.5 V
IO = −7.8 mA; VCC = 6 V
VI = VIH or VIL
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
V
V
V
V
V
VOL
LOW-state output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6 V
VI = VCC or GND; VCC = 6 V
VI = VIH or VIL; VO = VCC or GND
VI = VCC or GND; IO = 0 A;
-
-
-
-
-
-
-
-
0
0.1
V
0
0.1
V
0
0.1
V
0.15
0.26
0.26
±0.1
±0.5
8.0
V
0.16
V
ILI
input leakage current
-
-
-
µA
µA
µA
IOZ
ICC
OFF-state output current
quiescent supply current
VCC = 6.0 V
Ci
input capacitance
-
3.5
-
pF
Tamb = −40 °C to +85 °C
VIH HIGH-state input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −6.0 mA; VCC = 4.5 V
IO = −7.8 mA; VCC = 6.0 V
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
4.4
5.9
3.84
5.34
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
8 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 7:
Static characteristics 74HC573 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6 V
VI = VCC or GND; VCC = 6 V
VI = VIH or VIL; VO = VCC or GND
VI = VCC or GND; IO = 0 A;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.1
V
0.1
V
0.33
0.33
±1.0
±5.0
80
V
V
ILI
input leakage current
µA
µA
µA
IOZ
ICC
OFF-state output current
quiescent supply current
VCC = 6.0 V
Tamb = −40 °C to +125 °C
VIH HIGH-state input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −6.0 mA; VCC = 4.5 V
IO = −7.8 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
VOL
LOW-state output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VIH or VIL; VO = VCC or GND
VI = VCC or GND; IO = 0 A;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
V
V
V
V
V
ILI
input leakage current
µA
IOZ
ICC
OFF-state output current
quiescent supply current
±10.0 µA
160 µA
VCC = 6.0 V
Table 8:
Static characteristics 74HCT573
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max Unit
Tamb = 25 °C
VIH
VIL
HIGH-state input voltage VCC = 4.5 V to 5.5 V
LOW-state input voltage VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
V
V
0.8
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
9 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 8:
Static characteristics 74HCT573 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
Min
Typ
Max Unit
VOH
HIGH-state output voltage VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4
4.5
-
-
V
V
IO = −6.0 mA
LOW-state output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
3.98 4.32
VOL
-
-
-
-
0
0.1
V
V
IO = 6.0 mA
0.16 0.26
ILI
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
±0.1 µA
±0.5 µA
IOZ
OFF-state output current VI = VIH or VIL; VO = VCC or GND per input pin;
other inputs at GND or VCC; IO = 0 A; VCC = 5.5 V
ICC
quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V
-
-
8.0
µA
∆ICC
additional quiescent
supply current
per input pin; VI = VCC − 2.1 V; other inputs at
CC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V
V
Dn
-
-
-
-
35
126
234
450
-
µA
µA
µA
pF
LE
65
OE
125
3.5
Ci
input capacitance
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH-state input voltage VCC = 4.5 V to 5.5 V
LOW-state input voltage VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
0.8
VOH
HIGH-state output voltage VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4
-
-
-
-
V
V
IO = −6.0 mA
LOW-state output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
3.84
VOL
-
-
-
-
-
-
0.1
V
V
IO = 6.0 mA
0.33
ILI
input leakage current
VI = VCC or GND; VCC = 5.5 V
±1.0 µA
±5.0 µA
IOZ
OFF-state output current VI = VIH or VIL; VO = VCC or GND per input pin;
other inputs at GND or VCC; IO = 0 A; VCC = 5.5 V
ICC
quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V
-
-
80
µA
∆ICC
additional quiescent
supply current
per input pin; VI = VCC − 2.1 V; other inputs at
VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V
Dn
LE
OE
-
-
-
-
-
-
158
293
563
µA
µA
µA
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
10 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 8:
Static characteristics 74HCT573 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max Unit
Tamb = −40 °C to +125 °C
VIH
VIL
HIGH-state input voltage VCC = 4.5 V to 5.5 V
LOW-state input voltage VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
0.8
VOH
HIGH-state output voltage VI = VIH or VIL; VCC = 4.5 V
IO = −20 µA
4.4
3.7
-
-
-
-
V
V
IO = −6.0 mA
LOW-state output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 µA
VOL
-
-
-
-
-
-
-
-
0.1
0.4
V
V
IO = 6.0 mA
ILI
input leakage current
VI = VCC or GND; VCC = 5.5 V
±1.0 µA
±10.0 µA
IOZ
OFF-state output current VI = VIH or VIL; VO = VCC or GND per input pin;
other inputs at GND or VCC; IO = 0 A; VCC = 5.5 V
ICC
quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V
-
-
160
µA
∆ICC
additional quiescent
supply current
per input pin; VI = VCC − 2.1 V; other inputs at
CC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V
V
Dn
LE
OE
-
-
-
-
-
-
172
319
613
µA
µA
µA
11. Dynamic characteristics
Table 9:
Dynamic characteristics 74HC573
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL
tPLH
,
propagation delay Dn to Qn
see Figure 7
VCC = 2.0 V
-
-
-
-
47
17
14
14
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
tPHL
tPLH
,
propagation delay LE to Qn
see Figure 8
VCC = 2.0 V
-
-
-
-
50
18
15
14
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
tPZH
tPZL
,
3-state output enable time OE to Qn
see Figure 9
VCC = 2.0 V
-
-
-
44
16
13
140
28
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
24
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
11 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 9:
Dynamic characteristics 74HC573 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
tPHZ
tPLZ
Conditions
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
per latch; VI = GND to VCC
Min
Typ
Max
Unit
,
3-state output disable time OE to Qn
-
-
-
55
20
16
150
30
ns
ns
ns
26
tTHL
,
output transition time
tTLH
-
-
-
14
5
60
12
10
ns
ns
ns
4
tW
pulse width LE HIGH
80
16
14
14
5
-
-
-
ns
ns
ns
4
tsu
set-up time Dn to LE
50
10
9
11
4
-
-
-
ns
ns
ns
3
th
hold time Dn to LE
5
5
5
-
3
-
-
-
-
ns
ns
ns
pF
1
1
[1]
CPD
power dissipation capacitance
26
Tamb = −40 to +85 °C
tPHL
tPLH
,
propagation delay Dn to Qn
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
190
38
ns
ns
ns
33
tPHL
tPLH
,
propagation delay LE to Qn
-
-
-
-
-
-
190
38
ns
ns
ns
33
tPZH
tPZL
,
,
3-state output enable time OE to Qn
3-state output disable time OE to Qn
-
-
-
-
-
-
175
35
ns
ns
ns
30
tPHZ
tPLZ
-
-
-
-
-
-
190
38
ns
ns
ns
33
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
12 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 9:
Dynamic characteristics 74HC573 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
tTHL
tTLH
Conditions
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
,
output transition time
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
-
-
-
-
-
-
75
15
13
ns
ns
ns
tW
tsu
th
100
20
-
-
-
-
-
-
ns
ns
ns
17
65
13
11
-
-
-
-
-
-
ns
ns
ns
5
5
5
-
-
-
-
-
-
ns
ns
ns
Tamb = −40 to +125 °C
tPHL
tPLH
,
propagation delay Dn to Qn
propagation delay LE to Qn
3-state output enable time OE to Qn
3-state output disable time OE to Qn
output transition time
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
38
tPHL
tPLH
,
-
-
-
-
-
-
225
45
ns
ns
ns
38
tPZH
tPZL
,
,
-
-
-
-
-
-
210
42
ns
ns
ns
36
tPHZ
tPLZ
-
-
-
-
-
-
225
45
ns
ns
ns
38
tTHL
,
tTLH
-
-
-
-
-
-
90
18
15
ns
ns
ns
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
13 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 9:
Dynamic characteristics 74HC573 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
Conditions
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
tW
tsu
th
pulse width LE HIGH
120
24
-
-
-
-
-
-
ns
ns
ns
20
set-up time Dn to LE
hold time Dn to LE
75
15
13
-
-
-
-
-
-
ns
ns
ns
5
5
5
-
-
-
-
-
-
ns
ns
ns
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
Table 10: Dynamic characteristics 74HCT573
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL
tPLH
,
propagation delay Dn to Qn
see Figure 7
VCC = 4.5 V
-
-
20
17
35
-
ns
ns
VCC = 5 V; CL = 15 pF
see Figure 8
tPHL
tPLH
,
propagation delay LE to Qn
VCC = 4.5 V
-
-
-
18
15
17
35
-
ns
ns
ns
VCC = 5 V; CL = 15 pF
VCC = 4.5 V; see Figure 9
tPZH
tPZL
,
,
3-state output enable time OE to Qn
3-state output disable time OE to Qn
output transition time
30
tPHZ
tPLZ
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 7
-
-
18
5
30
12
ns
ns
tTHL
,
tTLH
tW
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 10
VCC = 4.5 V; see Figure 10
16
13
9
5
-
-
-
-
ns
ns
ns
pF
tsu
th
7
4
[1]
CPD
power dissipation capacitance
per latch;
-
26
VI = GND to (VCC − 1.5 V)
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
14 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 10: Dynamic characteristics 74HCT573 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 to +85 °C
tPHL
tPLH
,
propagation delay Dn to Qn
propagation delay LE to Qn
3-state output enable time OE to Qn
3-state output disable time OE to Qn
output transition time
VCC = 4.5 V; see Figure 7
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 7
-
-
-
-
-
-
-
-
-
-
44
44
38
38
15
ns
ns
ns
ns
ns
tPHL
tPLH
,
tPZH
tPZL
,
,
tPHZ
tPLZ
tTHL
,
tTLH
tW
tsu
th
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 10
VCC = 4.5 V; see Figure 10
20
16
11
-
-
-
-
-
-
ns
ns
ns
Tamb = −40 to +125 °C
tPHL
tPLH
,
propagation delay Dn to Qn
propagation delay LE to Qn
3-state output enable time OE to Qn
3-state output disable time OE to Qn
output transition time
VCC = 4.5 V; see Figure 7
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 7
-
-
-
-
-
-
-
-
-
-
53
53
45
45
18
ns
ns
ns
ns
ns
tPHL
tPLH
,
tPZH
tPZL
,
,
tPHZ
tPLZ
tTHL
,
tTLH
tW
tsu
th
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 10
VCC = 4.5 V; see Figure 10
24
20
14
-
-
-
-
-
-
ns
ns
ns
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
15 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
12. Waveforms
Dn input
V
M
t
t
PHL
PLH
90 %
V
Qn output
M
10 %
TLH
t
t
THL
001aae082
Measurement points are given in Table 11.
Fig 7. Propagation delay data input (Dn) to output (Qn) and output transition time
LE input
V
M
t
W
t
t
PHL
PLH
90 %
Qn output
V
M
10 %
t
t
TLH
THL
001aae083
Measurement points are given in Table 11.
Fig 8. Pulse width latch enable input (LE), propagation delay latch enable input (LE) to
output (Qn) and output transition time
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
16 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
10%
V
OL
t
t
PZH
PHZ
V
OH
90%
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in Table 11.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 9. 3-state enable and disable times
V
h
LE input
M
t
t
su
su
t
t
h
V
Dn input
M
001aae084
Measurement points are given in Table 11.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 10. Set-up and hold times for data input (Dn) to latch input (LE)
Table 11: Measurement points
Type
Input
VM
Output
VM
74HC573
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT573
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
17 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
PULSE
GENERATOR
open
DUT
R
T
C
L
001aad983
Test data is given in Table 12.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 11. Load circuitry for measuring switching times
Table 12: Test data
Type
Input
VI
Load
CL
S1 position
tr, tf
6 ns
6 ns
RL
tPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC573
VCC
3 V
15 pF, 50 pF 1 kΩ
15 pF, 50 pF 1 kΩ
open
open
GND
GND
VCC
VCC
74HCT573
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
18 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
13. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 12. Package outline SOT146-1 (DIP20)
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
19 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 13. Package outline SOT163-1 (SO20)
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
20 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 14. Package outline SOT339-1 (SSOP20)
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
21 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 15. Package outline SOT360-1(TSSOP20)
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
22 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 16. Package outline SOT764-1 (DHVQFN20)
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
23 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
14. Abbreviations
Table 13: Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
TTL
Transistor-Transistor Logic
Machine Model
MM
15. Revision history
Table 14: Revision history
Document ID
74HC_HCT573_3
Modifications:
Release date Data sheet status
20060117 Product data sheet
Change notice Doc. number Supersedes
-
-
74HC_HCT573_CNV_2
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Added type numbers 74HC573BQ and 74HCT573BQ (package DHVQFN20)
• Added family specification
• Added abbreviations list
74HC_HCT573_CNV_2 19901201
Product specification -
-
-
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
24 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
16. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
17. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
19. Trademarks
Notice — All referenced brands, product names, service names and
18. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
20. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74HC_HCT573_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
25 of 26
74HC573; 74HCT573
Philips Semiconductors
Octal D-type transparent latch; 3-state
21. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contact information . . . . . . . . . . . . . . . . . . . . 25
8
9
10
11
12
13
14
15
16
17
18
19
20
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 17 January 2006
Document number: 74HC_HCT573_3
Published in The Netherlands
相关型号:
74HC573DB-Q100
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 5.30 MM, PLASTIC, MO-150, SOT339-1, SSOP-20
NXP
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