74HC590BQ [NXP]
8-bit binary counter with output register; 3-state; 与输出寄存器的8位二进制计数器;三态
| 型号： | 74HC590BQ |
| 厂家： | 
NXP |
| 描述： | 8-bit binary counter with output register; 3-state |
| 文件： | 总21页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC590
8-bit binary counter with output register; 3-state
Rev. 02 — 28 April 2009
Product data sheet
1. General description
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low
power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The
storage register has parallel (Q0 to Q7) outputs. The binary counter features a master
reset counter (MRC) and count enable (CE) inputs. The counter and storage register have
separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are
connected together, the counter state always is one count ahead of the register. Internal
circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided
for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of
the second stage. Cascading for larger count chains can be accomplished by connecting
RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks
are connected together, the counter state always is one count ahead of the register.
2. Features
I Counter and register have independent clock inputs
I Counter has master reset
I Complies with JEDEC standard no. 7A
I Multiple package options
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 2000 V
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC590N
74HC590D
−40 °C to +125 °C
−40 °C to +125 °C
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
SO16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC590PW −40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT403-1
74HC590BQ −40 °C to +125 °C
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals; body
2.5 × 3.5 × 0.85 mm
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
4. Functional diagram
12 CE
11 CPC
10 MRC
8-BIT BINARY COUNTER
13 CPR
RCO
9
8-BIT STORAGE REGISTER
Q0 15
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
3
4
5
6
7
14 OE
3-STATE OUTPUTS
001aac542
Fig 1. Functional diagram
14
13
OE
CPR
CE
EN3
C2
11
CPC
13
CPR
12
11
CTR8
G1
9
9
CPC
MRC
(CT=255)Z4
1+
RCO
RCO
10
15
1
CT=0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
15
1
2D
3
1D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
12
3
2
CE
4
3
5
4
6
5
7
6
MRC
10
OE
14
7
2D
3
001aac544
001aac545
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
2 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
14
OE
13
CPR
12
CE
11
9
RCO
CPC
15
1R
T
T
T
T
T
T
T
T
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C1
C1
C1
C1
C1
C1
C1
C1
10
R
R
R
R
R
R
R
R
1S
MRC
1
2
3
4
5
6
7
1R
1S
1R
1S
1R
1S
1R
1S
1R
1S
1R
1S
1R
1S
001aac543
Fig 4. Logic diagram
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
3 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
5. Pinning information
5.1 Pinning
74HC590
terminal 1
index area
2
3
4
5
6
7
15
14
13
12
11
10
Q2
Q3
Q4
Q5
Q6
Q7
Q0
74HC590
OE
CPR
CE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
Q2
V
CC
(1)
Q0
CPC
MRC
GND
74HC590
Q3
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
Q2
V
CC
Q4
CPR
CE
Q0
Q3
OE
Q5
Q4
CPR
CE
Transparent top view
001aac547
Q6
CPC
MRC
RCO
Q5
Q6
CPC
MRC
RCO
(1) The die substrate is attached to
the exposed die pad using
conductive die attach material. It
can not be used as a supply pin
or input.
Q7
Q7
GND
GND
001aaj535
001aac564
Fig 5. Pin configuration DIP16
Fig 6. Pin configuration SO16
and TSSOP16
Fig 7. Pin configuration
DHVQFN16
5.2 Pin description
Table 2.
Symbol
Q0 to Q7
GND
RCO
MRC
CPC
Pin description
Pin
Description
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
ground (0 V)
8
9
ripple carry output (active LOW)
10
11
12
13
14
16
master reset counter input (active LOW)
counter clock input (active HIGH)
count enable input (active LOW)
register clock input (active HIGH)
output enable input (active LOW)
supply voltage
CE
CPR
OE
VCC
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
4 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
6. Functional description
Table 3.
Function table[1] [2]
Inputs
Description
OE
H
L
CPR
X
MRC
CE
X
X
X
X
X
L
CPC
X
X
X
X
X
L
Q outputs disable
Q outputs enable
counter data stored into register
register stage is not changed
counter clear
X
X
X
↑
X
X
↓
X
X
X
X
X
X
H
H
H
↑
advance one count
no count
X
X
L
↓
X
X
H
X
no count
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition.
[2] RCO = Q0’ · Q1’ · Q2’ · Q3’ · Q4’ · Q5’ · Q6’ · Q7’ (Q0’ to Q7’ are internal outputs of the counter).
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
5 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
CPC
CPR
MRC
CE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
RCO
high-impedance
OFF-state
counter clear
count
inhibit
001aac548
Fig 8. Typical timing sequence
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
6 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
±20
±20
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to VCC + 0.5 V
RCO standard output
-
-
mA
mA
IOK
IO
-
±25
±35
70
mA
mA
mA
mA
°C
Qn bus driver output
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−70
−65
-
storage temperature
total power dissipation
+150
[2]
Tamb = −40 °C to +125 °C
DIP16 package
-
-
-
750
500
500
mW
mW
mW
SO16 package
TSSOP16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
For SO16 packages: Ptot derates linearly with 8 mW/K above 70 °C.
For TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN16 packages: Ptot derates linearly with 8 mW/K above 60 °C.
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
V
supply voltage
2.0
5.0
6.0
VI
input voltage
0
-
VCC
VCC
625
139
83
V
VO
output voltage
0
-
V
∆t/∆V
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
-
-
ns/V
ns/V
ns/V
°C
-
1.67
VCC = 6.0 V
-
-
-
Tamb
ambient temperature
−40
+125
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
7 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
1.5
3.15
4.2
-
Max
-
Min
1.5
3.15
4.2
-
Max
-
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5 1.2
3.15 2.4
4.2 3.2
-
-
V
V
V
V
V
V
VCC = 4.5 V
-
-
VCC = 6.0 V
-
-
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.8
0.5
0.5
1.35
1.8
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
-
-
VCC = 6.0 V
2.8
1.8
-
-
VOH
HIGH-level
VI = VIH or VIL
output voltage
all outputs
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
RCO standard output
IO = −4 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
Qn bus driver output
IO = −6.0 mA; VCC = 4.5 V
IO = −7.8 mA; VCC = 6.0 V
VI = VIH or VIL
1.9 2.0
4.4 4.5
5.9 6.0
-
-
-
1.9
4.4
5.9
-
-
-
1.9
4.4
5.9
-
-
-
V
V
V
4.18 4.31
5.68 5.80
-
-
4.13
5.63
-
-
4.1
5.6
-
-
V
V
4.18 4.31
5.68 5.80
-
-
4.13
5.63
-
-
4.1
5.6
-
-
V
V
VOL
LOW-level
output voltage
all outputs
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
RCO standard output
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
Qn bus driver output
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
0.1
0.1
0.1
-
-
-
0.1
0.1
0.1
V
V
V
-
-
0.17 0.26
0.18 0.26
-
-
0.33
0.33
-
-
0.4
0.4
V
V
-
-
-
0.17 0.26
0.18 0.26
-
-
-
0.33
0.33
±1.0
-
-
-
0.4
0.4
V
V
II
input leakage VI = VCC or GND;
-
±0.1
±1.0
µA
current
VCC = 6.0 V
IOZ
OFF-state
per pin; VI = VIH or VIL;
-
-
±0.5
-
±5.0
-
±10
µA
output current VO = VCC or GND;
other inputs at VCC or GND;
CC = 6.0 V
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 6.0 V
-
-
-
4.0
-
-
-
40
-
-
-
80
-
µA
V
input
3.5
pF
capacitance
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
8 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); for test circuit see Figure 15.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
[1]
tpd
propagation
delay
CPC to RCO; see Figure 9
VCC = 2.0 V
-
-
-
52 150
-
-
-
190
38
-
-
-
230
45
ns
ns
ns
VCC = 4.5 V
19
15
30
26
VCC = 6.0 V
33
40
CPR to Qn; see Figure 10
VCC = 2.0 V
-
-
-
50 140
-
-
-
175
35
-
-
-
210
42
ns
ns
ns
VCC = 4.5 V
17
14
28
24
VCC = 6.0 V
30
36
tPLH
LOW to HIGH MRC to RCO; see Figure 11
propagation
delay
VCC = 2.0 V
-
-
-
53 130
-
-
-
165
33
-
-
-
200
40
ns
ns
ns
VCC = 4.5 V
18
14
26
22
VCC = 6.0 V
28
34
[2]
[3]
ten
enable time
disable time
pulse width
OE to Qn; see Figure 12
VCC = 2.0 V
-
-
-
28 105
-
-
-
130
26
-
-
-
160
32
ns
ns
ns
VCC = 4.5 V
13
11
21
18
VCC = 6.0 V
22
27
tdis
OE to Qn; see Figure 12
VCC = 2.0 V
-
-
-
28 105
-
-
-
130
26
-
-
-
160
32
ns
ns
ns
VCC = 4.5 V
13
11
21
18
VCC = 6.0 V
22
27
tW
CPC and CPR; HIGH or
LOW; see Figure 9 and
Figure 10
VCC = 2.0 V
VCC = 4.5 V
100 24
-
-
-
125
25
-
-
-
145
29
-
-
-
ns
ns
ns
20
17
9
8
VCC = 6.0 V
21
25
MRC; LOW; see Figure 11
VCC = 2.0 V
75
15
13
28
8
-
-
-
95
19
16
-
-
-
110
22
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tsu
set-up time
CPC to CPR; see Figure 14
VCC = 2.0 V
100 46
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
14
10
VCC = 6.0 V
21
26
CE to CPC; see Figure 13
VCC = 2.0 V
100 44
-
-
-
125
25
-
-
-
150
30
-
-
-
ns
ns
ns
VCC = 4.5 V
20
17
11
9
VCC = 6.0 V
21
26
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
9 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); for test circuit see Figure 15.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
th
hold time
CE to CPC; see Figure 13
VCC = 2.0 V
0
0
0
-
-
-
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
trec
recovery time MRC to CPC; see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
75
15
13
28
7
-
-
-
95
19
16
-
-
-
110
22
-
-
-
ns
ns
ns
6
19
fmax
maximum
frequency
CPC or CPR; see Figure 9
and Figure 10
VCC = 2.0 V
VCC = 4.5 V
6.6 16
-
-
-
-
5.2
26
31
-
-
-
-
-
4.4
22
26
-
-
-
-
-
MHz
MHz
MHz
pF
33
39
-
52
61
44
VCC = 6.0 V
[4]
CPD
power
VI = GND to VCC
dissipation
capacitance
[1] tpd is the same as tPHL, tPLH
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
.
.
.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
10 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
11. Waveforms
1/f
max
V
I
CPC input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
RCO output
V
M
V
OL
001aac550
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 9. Waveforms showing the propagation delays from the counter clock input (CPC) to ripple carry (RCO)
output and the CPC pulse width
Table 8.
Type
Measurement points
Input
Output
VM
VI
VM
74HC590
VCC
0.5VCC
0.5VCC
1/f
max
V
I
CPR input
V
M
GND
t
W
t
t
PHL
PLH
V
OH
Qn output
V
M
V
OL
001aac549
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 10. Waveforms showing the propagation delays from the register clock input (CPR) to output (Qn) and the
register clock pulse width
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
11 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
t
W
V
I
MRC input
V
M
GND
t
PLH
V
OH
V
RCO output
CPC input
M
V
OL
t
rec
V
I
V
M
GND
001aac551
Measurement points are given in Table 8.
OL and VOH are the typical output voltage levels that occur with the output load.
V
Fig 11. Waveforms showing the propagation delays from the master reset counter input (MRC) to output (RCO),
the MRC pulse width and recovery time
V
I
OE input
output
V
M
GND
t
t
PZL
PLZ
V
CC
V
M
LOW-to-OFF
OFF-to-LOW
10 %
V
V
OL
t
t
PZH
PHZ
90 %
output
OH
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
001aac554
outputs
enabled
outputs
disabled
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 12. Waveforms showing the 3-state enable and disable times
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
12 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
V
I
CE input
GND
V
M
t
t
t
t
h
su
h
su
V
OH
CPC input
V
M
V
OL
001aac553
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 13. Waveforms showing the set-up and hold times for the count enable input (CE) to the counter clock input
(CPC)
V
I
CPC input
GND
V
M
t
t
h
su
V
OH
CPR input
V
M
V
OL
001aac552
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 14. Waveforms showing the set-up and hold times for the counter clock input (CPC) to the register clock
input (CPR)
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
13 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 15. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
VCC
Input
VI
Load
CL
Switch position
tr, tf
RL
tPHL, tPLH
tPZH, tPHZ
GND
tPZL, tPLZ
2.0 V to 6.0 V
VCC
6 ns
50 pF
1 kΩ
open
VCC
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
14 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
12. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 16. Package outline SOT38-4 (DIP16)
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
15 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 17. Package outline SOT109-1 (SO16)
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
16 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 18. Package outline SOT403-1 (TSSOP16)
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
17 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 19. Package outline SOT763-1 (DHVQFN16)
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
18 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74HC590_2
Release date
20090428
Data sheet status
Change notice
Supersedes
Product data sheet
-
74HC590_1
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Quick reference data incorporated in to Section 9 and Section 10.
• Added type number 74HC590N (DIP16 package)
74HC590_1
20050330
Product data sheet
-
-
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
19 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC590_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 28 April 2009
20 of 21
74HC590
NXP Semiconductors
8-bit binary counter with output register; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 April 2009
Document identifier: 74HC590_2
相关型号：
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