74HC7046AD-T_技术文档

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT7046A

Phase-locked-loop with lock

detector

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

amplifiers. With a passive low-pass

SIG_IN(pin 14) or COMP_IN(pin 3)

inputs between the HC and HCT

versions.

FEATURES

filter, the “7046” forms a second-order

loop PLL. The excellent VCO linearity

is achieved by the use of linear

op-amp techniques.

• Low power consumption

• Centre frequency up to 17 MHz

(typ.) at V_CC= 4.5 V

Phase comparators

• Choice of two phase comparators:

EXCLUSIVE-OR;

edge-triggered JK flip-flop;

The signal input (SIG_IN) can be

directly coupled to the self-biasing

amplifier at pin 14, provided that the

signal swing is between the standard

HC family input logic levels.

VCO

The VCO requires one external

capacitor C1 (between C1_Aand C1_B)

and one external resistor R1

(between R₁and GND) or two

external resistors R1 and R2

• Excellent VCO frequency linearity

• VCO-inhibit control for ON/OFF

keying and for low standby power

consumption

Capacitive coupling is required for

signals with smaller swings.

(between R₁and GND, and R₂and

GND). Resistor R1 and capacitor C1

determine the frequency range of the

VCO. Resistor R2 enables the VCO

to have a frequency offset if required.

• Minimal frequency drift

Phase comparator 1 (PC1)

• Operation power supply voltage

range:

VCO section 3.0 to 6.0 V

digital section 2.0 to 6.0 V

This is an EXCLUSIVE-OR network.

The signal and comparator input

frequencies (f_i) must have a 50% duty

factor to obtain the maximum locking

range. The transfer characteristic of

PC1, assuming ripple (f_r= 2f_i) is

suppressed,

The high input impedance of the VCO

simplifies the design of low-pass

filters by giving the designer a wide

choice of resistor/capacitor ranges. In

order not to load the low-pass filter, a

demodulator output of the VCO input

voltage is provided at pin 10

• Zero voltage offset due to op-amp

buffering

• Output capability: standard

• I_CCcategory: MSI

is:

V

V_DEMOUT

=

^CC(φ _SIGIN– φ_COMPIN

)

----------

π

GENERAL DESCRIPTION

(DEM_OUT). In contrast to conventional

techniques where the DEM_OUT

The 74HC/HCT7046 are high-speed

Si-gate CMOS devices and are

specified in compliance with JEDEC

standard no. 7.

voltage is one threshold voltage lower

than the VCO input voltage, here the

DEM_OUTvoltage equals that of the

VCO input. If DEM_OUTis used, a load

resistor (R_S) should be connected

from DEM_OUTto GND; if unused,

DEM_OUTshould be left open. The

VCO output (VCO_OUT) can be

connected directly to the comparator

input (COMP_IN), or connected via a

frequency-divider. The VCO output

signal has a duty factor of 50%

(maximum expected deviation 1%), if

the VCO input is held at a constant

DC level. A LOW level at the inhibit

input (INH) enables the VCO and

demodulator, while a HIGH level turns

both off to minimize standby power

consumption.

where V_DEMOUTis the demodulator

output at pin 10;

The 74HC/HCT7046 are

V_DEMOUT= V_PC1OUT(via low-pass

filter).

phase-locked-loop circuits that

comprise a linear voltage-controlled

oscillator (VCO) and two different

phase comparators (PC1 and PC2)

with a common signal input amplifier

and a common comparator input.

The phase comparator gain

is:

V_CC

K_p

=

(V ⁄ r) .

----------

π

A lock detector is provided and this

gives a HIGH level at pin 1 (LD) when

the PLL is locked. The lock detector

capacitor must be connected

The average output voltage from

PC1, fed to the VCO input via the

low-pass filter and seen at the

between pin 15 (C_LD) and pin 8

(GND). The value of the C_LDcapacitor

can be determined, using information

supplied in Fig.32. The input signal

can be directly coupled to large

voltage signals, or indirectly coupled

(with a series capacitor) to small

voltage signals. A self-bias input

circuit keeps small voltage signals

within the linear region of the input

demodulator output at pin 10

(V_DEMOUT), is the resultant of the

phase differences of signals (SIG_IN)

and the comparator input (COMP_IN)

as shown in Fig.6. The average of

V_DEMOUTis equal to 1/2 V_CCwhen

there is no signal or noise at SIG_IN

and with this input the VCO oscillates

at the centre frequency (f_o). Typical

The only difference between the HC

and HCT versions is the input level

specification of the INH input. This

input disables the VCO section. The

comparators’ sections are identical,

so that there is no difference in the

December 1990

2

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

waveforms for the PC1 loop locked at

f_oare shown in Fig.7.

the low-pass filter. With no signal

present at SIG_INthe VCO adjusts, via

PC2, to its lowest frequency.

The phase comparator gain is:

V

K_p

=

^CC(V ⁄ r) .

----------

The frequency capture range (2f_c) is

defined as the frequency range of

input signals on which the PLL will

lock if it was initially out-of-lock. The

frequency lock range (2f_L) is defined

as the frequency range of input

signals on which the loop will stay

locked if it was initially in lock. The

capture range is smaller or equal to

the lock range.

4π

APPLICATIONS

V

_DEMOUTis the resultant of the initial

• FM modulation and demodulation

phase differences of SIG_INand

COMP_INas shown in Fig.8. Typical

waveforms for the PC2 loop locked at

f_oare shown in Fig.9.

• Frequency synthesis and

multiplication

• Frequency discrimination

• Tone decoding

When the frequencies of SIG_INand

COMP_INare equal but the phase of

SIG_INleads that of COMP_IN, the

p-type output driver at PC2_OUTis held

“ON” for a time corresponding to the

phase difference (φ_DEMOUT). When

the phase of SIG_INlags that of

• Data synchronization and

conditioning

With PC1, the capture range depends

on the low-pass filter characteristics

and can be made as large as the lock

range. This configuration retains lock

even with very noisy input signals.

Typical behaviour of this type of

phase comparator is that it can lock to

input frequencies close to the

harmonics of the VCO centre

frequency.

• Voltage-to-frequency conversion

• Motor-speed control

COMP_IN, the n-type driver is held

“ON”.

When the frequency of SIG_INis higher

than that of COMP_IN, the p-type

output driver is held “ON” for most of

the input signal cycle time, and for

the remainder of the cycle both n and

p- type drivers are “OFF” (3-state). If

the SIG_INfrequency is lower than the

COMP_INfrequency, then it is the

n-type driver that is held “ON” for

most of the cycle. Subsequently, the

voltage at the capacitor (C2) of the

low-pass filter connected to PC2_OUT

varies until the signal and comparator

inputs are equal in both phase and

frequency. At this stable point the

voltage on C2 remains constant as

the PC2 output is in 3-state and the

VCO input at pin 9 is a high

Phase comparator 2 (PC2)

This is a positive edge-triggered

phase and frequency detector. When

the PLL is using this comparator, the

loop is controlled by positive signal

transitions and the duty factors of

SIG_INand COMP_INare not important.

PC2 comprises two D-type flip-flops,

control-gating and a 3-state output

stage. The circuit functions as an

up-down counter (Fig.5) where SIG_IN

causes an up-count and COMP_IN

a

down-count. The transfer function of

PC2, assuming ripple (f_r= f_i) is

suppressed,

is:

impedance.

V

Thus, for PC2, no phase difference

exists between SIG_INand COMP_IN

over the full frequency range of the

VCO. Moreover, the power

V_DEMOUT

=

^CC(φ _SIGIN– φ_COMPIN

)

----------

4π

dissipation due to the low-pass filter is

reduced because both p and n-type

drivers are “OFF” for most of the

signal input cycle. It should be noted

that the PLL lock range for this type of

phase comparator is equal to the

capture range and is independent of

where V_DEMOUTis the demodulator

output at pin 10;

V_DEMOUT= V_PC2OUT(via low-pass

filter).

December 1990

3

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C;

TYPICAL

UNIT

SYMBOL PARAMETER

CONDITIONS

HC

HCT

f_o

VCO centre frequency

C1 = 40 pF; R1 = 3 kΩ; V_CC= 5 V

19

MHz

pF

C_I

input capacitance (pin 5)

3.5

24

3.5

24

C_PD

power dissipation capacitance per package notes 1 and 2

pF

Notes

1. Applies to the phase comparator section only (VCO disabled).

For power dissipation of VCO and demodulator sections see Figs 20, 21 and 22.

2. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

4

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

lock detector output (active HIGH)

phase comparator 1 output

comparator input

1

LD

2

PC1_OUT

COMP_IN

VCO_OUT

INH

3

4

VCO output

5

inhibit input

6

C1_A

capacitor C1 connection A

capacitor C1 connection B

ground (0 V)

7

C1_B

8

GND

VCO_IN

DEM_OUT

R₁

9

VCO input

10

11

12

13

14

15

16

demodulator output

resistor R1 connection

resistor R2 connection

phase comparator 2 output

signal input

R₂

PC2_OUT

SIG_IN

C_LD

lock detector capacitor input

positive supply voltage

V_CC

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

5

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

GM8A47

December 1990

6

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Fig.5 Logic diagram.

Fig.6 Phase comparator 1: average output

voltage versus input phase difference:

V

V_DEMOUT= V_PC1OUT

=

^CC(φ _SIGIN– φ_COMPIN

)

----------

π

Fig.7 Typical waveforms for PLL using phase

comparator 1, loop locked at f_o.

φ_DEMOUT= φ_SIGIN– φ_COMPIN

December 1990

7

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Fig.8 Phase comparator 2: average output

voltage versus input phase difference:

V

V_DEMOUT= V_PC2OUT

=

^CC(φ _SIGIN– φ_COMPIN

)

----------

4π

Fig.9 Typical waveforms for PLL using phase

comparator 2, loop locked at f_o.

˙

φ_DEMOUT= (φ_SIGIN– φ_COMPIN) .

December 1990

8

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT

74HC

74HCT

SYMBOL PARAMETER

UNIT CONDITIONS

min. typ. max. min. typ. max.

V_CC

DC supply voltage

3.0

2.0

5.0

6.0

4.5

5.0

5.5

V

DC supply voltage if VCO section is

not used

V_I

DC input voltage range

DC output voltage range

0

V_CC

+85

0

V_CC

+85

V

V_O

0

V

T_amb

operating ambient temperature range −40

−40

°C

see DC and AC

CHARACTER-

ISTICS

+125 −40

+125 °C

t_r, t_f

input rise and fall times (pin 5)

1000

500

V_CC= 2.0 V

6.0

500

ns

V_CC= 4.5 V

400

V_CC= 6.0 V

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Voltages are referenced to GND (ground = 0 V)

SYMBOL

V_CC

PARAMETER

MIN. MAX. UNIT CONDITIONS

DC supply voltage

−0.5 +7

V

±I_IK

DC input diode current

DC output diode current

DC output source or sink current

DC V_CCor GND current

20

25

mA

for V_I< −0.5 V or V_I> V_CC+ 0.5 V

for V_O< −0.5 V or V_O> V_CC+ 0.5 V

for − 0.5 V < V_O< V_CC+ 0.5 V

±I_OK

±I_O

±I_CC

±I_GND

;

50

mA

T_stg

storage temperature range

−65

+150 °C

P_tot

power dissipation per package

for temperature range: −40 to +125 °C

74HC/HCT

plastic DIL

750

500

mW

above +70 °C: derate linearly with 12 mW/K

plastic mini-pack (SO)

above +70 °C: derate linearly with 8 mW/K

December 1990

9

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

DC CHARACTERISTICS FOR 74HC

Quiescent supply current

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL

PARAMETER

UNIT

V_CC

(V)

+25

−40 to +85 −40 to +125

OTHER

min. typ. max. min. max. min. max.

8.0 80.0 160.0 µA

I_CC

quiescent supply

current

(VCO disabled)

6.0 pins 3, 5, and 14 at

V_CC; pin 9 at GND;

I_Iat pins 3 and 14

to be excluded

December 1990

10

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Phase comparator section

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL

PARAMETER

UNIT

V_CCV_I

(V)

+25

−40 to +85 −40 to +125

OTHER

min. typ. max. min. max. min. max.

DC coupled HIGH

level input voltage

SIG_IN, COMP_IN

1.5

3.15 2.4

4.2

1.2

1.5

3.15

4.2

1.5

3.15

4.2

2.0

4.5

6.0

V_IH

V

3.2

DC coupled LOW level

input voltage

SIG_IN, COMP_IN

0.8

2.1

2.8

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

2.0

4.5

6.0

V_IL

HIGH level output

voltage

LD, PC_nOUT

1.9

4.4

5.9

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

2.0 V_IH−I_O= 20 µA

4.5 or −I_O= 20 µA

6.0 V_IL−I_O= 20 µA

V_OH

V_OL

HIGH level output

voltage

LD, PC_nOUT

V_IH

or

V_IL

3.98 4.32

5.48 5.81

3.84

5.34

3.7

5.2

4.5

6.0

−I_O= 4.0 mA

−I_O= 5.2 mA

LOW level output

voltage

LD, PC_nOUT

0

0.1

2.0 V_IHI_O= 20 µA

4.5 or I_O= 20 µA

6.0 V_ILI_O= 20 µA

LOW level output

voltage

LD, PC_nOUT

V_IH

or

V_IL

0.15 0.26

0.16 0.26

0.33

0.4

4.5

6.0

I_O= 4.0 mA

I_O= 5.2 mA

V_OL

V

±I_I

input leakage current

SIG_IN, COMP_IN

3.0

7.0

18.0

30.0

4.0

9.0

23.0

38.0

5.0

µA

2.0 V_CC

3.0 or

4.5 GND

6.0

11.0

27.0

45.0

±I_OZ

3-state

0.5

5.0

10.0 µA

6.0 V_IHV_O= V_CC

OFF-state current

PC2_OUT

or

V_IL

or GND

R_I

input resistance

SIG_IN, COMP_IN

800

250

150

kΩ

3.0 V_Iat self-bias

4.5 operating point;

6.0 ∆V_I= 0.5 V; see

Figs 10, 11 and 12

December 1990

11

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

VCO section

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HC

SYM-

BOL

PARAMETER

UNIT

V_CCV_I

OTHER

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

HIGH level

input voltage

INH

2.1

3.15 2.4

4.2

1.7

2.1

3.15

4.2

2.1

3.15

4.2

3.0

4.5

6.0

V_IH

V_IL

V

3.2

LOW level

input voltage

INH

1.3

2.1

2.8

0.9

1.35

1.8

0.9

1.35

1.8

0.9

1.35

1.8

3.0

4.5

6.0

V

HIGH level

output voltage

VCO_OUT

2.9

4.4

5.9

3.0

4.5

6.0

2.9

4.4

5.9

2.9

4.4

5.9

3.0 V_IH−I_O= 20 µA

V_OH

V_OL

±I_I

V

4.5 or

−I_O= 20 µA

6.0 V_IL−I_O= 20 µA

HIGH level

output voltage

VCO_OUT

V_IH

or

V_IL

3.98 4.32

5.48 5.81

3.84

5.34

3.7

5.2

4.5

6.0

−I_O= 4.0 mA

−I_O= 5.2 mA

V

LOW level

output voltage

VCO_OUT

0

0.1

3.0 V_IHI_O= 20 µA

4.5 or I_O= 20 µA

6.0 V_ILI_O= 20 µA

V

LOW level

output voltage

VCO_OUT

V_IH

or

V_IL

0.15 0.26

0.16 0.26

0.33

0.4

4.5

6.0

I_O= 4.0 mA

I_O= 5.2 mA

V

LOW level output

voltage C1_A,C1_B

(test purposes only)

V_IH

or

V_IL

0.40

0.47

0.54

4.5

6.0

I_O= 4.0 mA

I_O= 5.2 mA

V

V_CC

input leakage current

INH, VCO_IN

0.1

1.0

µA

kΩ

pF

6.0 or

GND

3.0

300

3.0

4.5

6.0

R1

resistor range

capacitor range

note 1

3.0

300

3.0

4.5

6.0

R2

40

3.0

4.5

6.0

no

limit

C1

over the range

speciﬁed for R1;

for linearity see

Figs 18 and 19.

1.1

1.9

3.4

4.9

3.0

4.5

6.0

operating voltage

range at VCO_IN

V_VCOIN

V

Note

1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2

are/is > 10 kΩ.

December 1990

12

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Demodulator section

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL

PARAMETER

UNIT

V_CC

(V)

+25

−40 to +85 −40 to +125

OTHER

min. typ. max. min. max. min. max.

R_S

resistor range

50

300

kΩ

mV

Ω

3.0 at R_S> 300 kΩ

4.5 the leakage

6.0 current can

inﬂuence

V_DEMOUT

V_OFF

offset voltage

VCO_INto V_DEMOUT

±30

±20

±10

3.0 V_I= V_VCOIN

4.5 1/2 V_CC

=

;

6.0 values taken

over R_Srange;

see Fig.13

R_D

dynamic output

resistance at DEM_OUT

25

3.0 V_DEMOUT=

4.5

6.0

1/2 V_CC

December 1990

13

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

AC CHARACTERISTICS FOR 74HC

Phase comparator section

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T

_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

OTHER

(V)

min. typ. max. min. max. min. max.

t

_PHL/ t_PLHpropagation delay

SIG_IN, COMP_IN

58

21

17

200

40

34

250

50

43

300 ns

60

51

2.0

4.5

6.0

Fig.14

to PC1_OUT

_PZH/ t_PZL3-state output enable

time SIG_IN, COMP_IN

to PC2_OUT

74

27

22

280

56

48

350

70

60

420 ns

84

71

2.0

4.5

6.0

Fig.15

t_PHZ/ t_PLZ3-state output disable

time SIG_IN, COMP_IN

to PC2_OUT

96

35

28

325

65

55

405

81

69

490 ns

98

83

2.0

4.5

6.0

Fig.15

t

_THL/ t_TLHoutput transition time

19

7

6

75

15

13

95

19

16

110

22

19

ns

2.0

4.5

6.0

Fig.14

V_I(p-p)

AC coupled input sensitivity

(peak-to-peak value) at

SIG_INor COMP_IN

9

mV

2.0

3.0

4.5

6.0

f_i= 1 MHz

11

15

33

VCO section

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

OTHER

74HC

SYM-

PARAMETER

BOL

UNIT

+25

−40 to +85

−40

to +125

V_CC

(V)

min. typ. max. typ. max. min. max.

∆f/T

frequency stability

with temperature

change

0.20

0.15

0.14

%/K 3.0 V_I= V_VCOIN=1/2 V_CC;

4.5 R1 = 100 kΩ; R2 = ∞;

6.0 C1 = 100 pF; see Fig.16

f_o

VCO centre

frequency

7.0

11.0 17.0

10.0

MHz 3.0 V_VCOIN= 1/2 V_CC

;

4.5 R1 = 3 kΩ; R2 = ∞;

(duty factor = 50%) 13.0 21.0

6.0 C1 = 40 pF; see Fig.17

∆f_VCOVCO frequency

1.0

0.4

0.3

%

3.0 R1 = 100 kΩ; R2 = ∞;

4.5 C1 = 100 pF; see Figs 18

6.0 and 19

linearity

δ_VCO

duty factor at

VCO_OUT

50

3.0

4.5

6.0

December 1990

14

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

DC CHARACTERISTICS FOR 74HCT

Quiescent supply current

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL

PARAMETER

UNIT

V_CC

(V)

+25

−40 to +85 −40 to +125

OTHER

min. typ. max. min. max. min. max.

I_CC

quiescent supply current

(VCO disabled)

8.0

80.0

160.0 µA

6.0 pins 3, 5 and 14

at V_CC; pin 9 at

GND; I_Iat pins 3

and 14 to be

excluded

∆I_CC

additional quiescent

supply current per input

pin for unit load coefﬁcient

is 1 (note 1)

100 360

450

490

µA

4.5 pins 3 and 14 at

to

V_CC; pin 9 at

5.5 GND; I_Iat pins 3

and 14 to be

V_I= V_CC− 2.1 V

excluded

Note

1. The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given above.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

INH

UNIT LOAD COEFFICIENT

1.00

December 1990

15

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Phase comparator section

Voltages are referenced to GND (ground = 0 V)

T

_amb(°C)

74HCT

−40 to +85 −40 to +125

min. typ. max min. max. min. max.

TEST CONDITIONS

SYM

BOL

PARAMETER

UNIT

V_CCV_I

(V)

+25

OTHER

DC coupled

V_IH

HIGH level input voltage 3.15 2.4

SIG_IN, COMP_IN

V

4.5

DC coupled

V_IL

LOW level input voltage

SIG_IN, COMP_IN

2.1 1.35

V

4.5

V_IH

or

V_IL

HIGH level output voltage

LD, PC_nOUT

V_OH

V_OL

±I_I

4.4

4.5

4.4

3.7

V

4.5

5.5

−I_O= 20 µA

−I_O= 4.0 mA

I_O= 20 µA

I_O= 4.0 mA

V_IH

or

V_IL

HIGH level output voltage

LD, PC_nOUT

3.98 4.32

3.84

V

V_IH

or

V_IL

LOW level output voltage

LD, PC_nOUT

0

0.1

0.33

38

0.1

0.4

45

V

V_IH

or

V_IL

LOW level output voltage

LD, PC_nOUT

0.15 0.26

V

V_CC

or

input leakage current

SIG_IN, COMP_IN

30

µA

GND

3-state

OFF-state current

PC2_OUT

V_IH

or

V_IL

V_O= V_CC

or GND

±I_OZ

0.5

5.0

10.0

V_Iat self-bias

input resistance

SIG_IN, COMP_IN

operating point;

∆V_I= 0.5 V; see Figs

10, 11 and 12

R_I

250

kΩ

4.5

December 1990

16

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

DC CHARACTERISTICS FOR 74HCT

VCO section

Voltages are referenced to GND (ground = 0 V)

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL

PARAMETER

UNIT

V_CCV_I

OTHER

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

V_IH

V_IL

HIGH level input

voltage

INH

2.0

1.6

2.0

V

4.5

to

5.5

LOW level input

voltage

INH

1.2 0.8

4.5

0.8

V

4.5

to

5.5

V_OH

V_OL

±I_I

HIGH level output

voltage

VCO_OUT

4.4

3.7

V

4.5 V_IH−I_O= 20 µA

or

V_IL

HIGH level output

voltage

VCO_OUT

3.98 4.32

3.84

V

4.5 V_IH−I_O= 4.0 mA

or

V_IL

LOW level output

voltage

VCO_OUT

0

0.1

0.4

0.54

1.0

V

4.5 V_IHI_O= 20 µA

or

V_IL

LOW level output

voltage

VCO_OUT

0.15 0.26

0.40

0.33

0.47

1.0

V

4.5 V_IHI_O= 4.0 mA

or

V_IL

LOW level output

voltage C1_A, C1_B

(test purposes only)

V

4.5 V_IHI_O= 4.0 mA

or

V_IL

input leakage

current

0.1

µA

5.5 V_CC

or

INH, VCO_IN

GND

R1

R2

C1

resistor range

capacitor range

3.0

40

300

kΩ

pF

4.5

note 1

no

limit

V_VCOIN

operating voltage

range at VCO_IN

1.1

3.4

V

4.5

over the range

speciﬁed for

R1;

for linearity see

Figs 18 and 19.

Note

1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2

are/is > 10 kΩ.

December 1990

17

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Demodulator section

Voltages are referenced to GND (ground = 0 V)

T

_amb(°C)

74HCT

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

TEST CONDITIONS

SYMBOL

PARAMETER

UNIT

V_CC

+25

OTHER

(V)

R_S

resistor range

50

300

kΩ

4.5 at R_S> 300 kΩ the

leakage current can

inﬂuence V_DEMOUT

V_OFF

offset voltage

VCO_INto V_DEMOUT

±20

mV

4.5 V_I= V_VCOIN= 1/2

V_CC; values taken

over R_Srange;

see Fig.13

R_D

dynamic output

25

Ω

4.5 V_DEMOUT= 1/2 V_CC

resistance at DEM_OUT

AC CHARACTERISTICS FOR 74HCT

Phase comparator section

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST

CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85

−40 to +125

OTHER

(V)

min. typ. max. min. max. min. max.

t

_PHL/ t_PLHpropagation delay

21

27

35

40

56

65

15

50

70

81

19

60

84

98

22

ns

4.5

Fig.14

SIG_IN, COMP_IN

to PC1_OUT

t_PZH/ t_PZL3-state output enable

time SIG_IN, COMP_IN

to PC2_OUT

4.5

Fig.15

Fig.14

t

_PHZ/ t_PLZ3-state output disable

time SIG_IN, COMP_IN

to PC2_OUT

t

_THL/ t_TLHoutput transition time

7

ns

4.5

V_I(p-p)

AC coupled input sensitivity

(peak-to-peak value) at

SIG_INor COMP_IN

15

mV

f_i=

1 MHz

December 1990

18

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

VCO section

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

(V)

+25

−40 to +85 −40 to +125

OTHER

min. typ. max. typ. max. min. max.

∆f/T

frequency stability

with temperature

change

0.15

%/K 4.5 V_I= V_COINwithin

recommended

range;

R1 = 100 kΩ;

R2 = ∞;

C1 = 100 pf;

see Fig.16b

f_o

VCO centre frequency 11.0 17.0

(duty factor = 50%)

MHz 4.5 V_VCOIN= 1/2 V_CC;

R1 = 3 kΩ; R2 = ∞;

C1 = 40 pF;

see Fig.17

∆f_VCO

VCO frequency

linearity

0.4

50

%

4.5 R1 = 100 kΩ;

R2 = ∞;

C1 = 100 pF; see

Figs 18 and 19

δ_VCO

duty factor at VCO_OUT

4.5

December 1990

19

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

FIGURE REFERENCES FOR DC CHARACTERISTICS

Fig.11 Input resistance at SIG_IN, COMP_INwith

∆V_I= 0.5 V at self-bias point.

Fig.10 Typical input resistance curve at SIG_IN,

COMP_IN.

____ R_S= 50 kΩ

- - - - R_S= 300 kΩ

Fig.12 Input current at SIG_IN, COMP_INwith

Fig.13 Offset voltage at demodulator output as a

function of VCO_INand R_S.

∆V_I= 0.5 V at self-bias point.

December 1990

20

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

AC WAVEFORMS

(1) HC : V_M= 50%; V_I= GND to V_CC

.

Fig.14 Waveforms showing input (SIG_IN, COMP_IN) to output (PC1_OUT) propagation delays and the output

transition times.

(1) HC : V_M= 50%; V_I= GND to V_CC

.

Fig.15 Waveforms showing the 3-state enable and disable times for PC2_OUT

.

December 1990

21

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

AC WAVEFORMS

To obtain optimum temperature stability, C₁must be a small as possible, but larger than 100 pF.

Fig.16 Continued.

December 1990

23

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Fig.17 Graphs showing VCO frequency (f_VCO) as a function of the VCO input voltage (V_VCOIN).

December 1990

24

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Fig.18 Definition of VCO frequency linearity:

∆V = 0.5 V over the V_CCrange:

for VCO linearity

f₁+ f₂

f′₀

=

--------------

2

Fig.19 Frequency linearity as a function of R1, C1

f′₀– f

linearity =

⁰× 100%

----------------

and V_CC: R2 = ∞ and ∆V = 0.5 V.

f′₀

December 1990

25

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

____ C1 = 40 pF

- - - - C1 = 1 µF

Fig.20 Power dissipation versus the value of R1:

Fig.21 Power dissipation versus the value of R2:

C_L= 50 pF; R1 = ∞; V_VCOIN= GND = 0 V;

T_amb= 25 °C.

C_L= 50 pF; R2 = ∞; V_VCOIN= 1/2 V_CC

T_amb= 25 °C.

;

Fig.22 Typical dc power dissipation of demodulator

section as a function of R_S: R1 = R2 = ∞;

T_amb= 25 °C; V_VCOIN= 1/2 V_CC

.

December 1990

26

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

APPLICATION INFORMATION

This information is a guide for the approximation of values of external components to be used with the 74HC/HCT7046

in a phase-lock-loop system.

References should be made to Figs 27, 28 and 29 as indicated in the table.

Values of the selected components should be within the following ranges:

R1

R2

between 3 kΩ and 300 kΩ;

R1 + R2 parallel value > 2.7 kΩ;

C1

greater than 40 pF.

PHASE

COMPARATOR

SUBJECT

DESIGN CONSIDERATIONS

VCO frequency characteristic

VCO frequency

without extra

offset

PC1, PC2

With R2 = ∞ and R1 within the range 3 kΩ < R1 < 300 kΩ, the characteristics

of the VCO operation will be as shown in Fig. 23.

(Due to R1, C1 time constant a small offset remains when R2 = ∞.)

Fig. 23 Frequency characteristic of VCO operating without offset:

f_o= centre frequency; 2f_L= frequency lock range.

Selection of R1 and C1

PC1

PC2

Given f_o, determine the values of R1 and C1 using Fig.27.

Given f_maxand f_o, determine the values of R1 and C1 using Fig.27,

use Fig.29 to obtain 2f_Land then use this to calculate f_min.

December 1990

27

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

PHASE

COMPARATOR

SUBJECT

DESIGN CONSIDERATIONS

VCO frequency characteristic

VCO frequency

with extra

offset

PC1, PC2

With R1 and R2 within the ranges 3 kΩ < R1 < 300 kΩ, 3 kΩ < R2 < 300 kΩ,

the characteristics of the VCO operation will be as shown in Fig. 24.

Fig. 24 Frequency characteristic of VCO operating with offset:

f_o= centre frequency; 2f_L= frequency lock range.

Selection of R1, R2 and C1

PC1, PC2

Given f₀and f_L, determine the value of product R1C1 by using Fig.29.

Calculate f_offfrom the equation f_off= f_o− 1.6f_L.

Obtain the values of C1 and R2 by using Fig.28.

Calculate the value of R1 from the value of C1 and the product R1C1.

December 1990

28

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

PHASE

COMPARATOR

SUBJECT

DESIGN CONSIDERATIONS

PLL conditions

with no signal at

the SIG_INinput

PC1

VCO adjusts to f_owith φ_DEMOUT= 90° and V_VCOIN= 1/2 V_CC(see Fig.6).

VCO adjusts to f_owith φ_DEMOUT= −360° and V_VCOIN= min. (see Fig.8).

PC2

PLL frequency

capture range

PC1, PC2

Loop ﬁlter component selection

(a) τ = R3 x C2

(b) amplitude characteristic

(c) pole-zero diagram

Fig. 25 Simple loop ﬁlter for PLL without offset; R3 ≥ 500 Ω.

(a) τ1 = R3 x C2;

τ2 = R4 x C2;

(b) amplitude characteristic

(c) pole-zero diagram

τ3 = (R3 + R4) x C2

Fig. 26 Simple loop ﬁlter for PLL with offset; R3 + R4 ≥ 500 Ω.

PLL locks on

harmonics at

centre frequency

PC1

PC2

yes

no

noise rejection at PC1

high

low

signal input

PC2

AC ripple content PC1

when PLL is

locked

f_r= 2f_i, large ripple content at φ_DEMOUT= 90°

PC2

f_r= f_i, small ripple content at φ_DEMOUT= 0°

December 1990

29

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.

(2) Interpolation for various values of R1 can be easily calculated because a constant R1C1 product will produce

almost the same VCO output frequency.

Fig.27 Typical value of VCO centre frequency (f_o) as a function of C1: R2 = ∞; V_VCOIN= 1/2 V_CC; INH = GND;

T_amb= 25 °C.

December 1990

30

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

APPLICATION INFORMATION

(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.

(2) Interpolation for various values of R2 can be easily calculated because a constant R2C2 product will produce

almost the same VCO output frequency.

Fig.28 Typical value of frequency offset as a function of C1: R1 = ∞; V_VCOIN= 1/2 V_CC; INH = GND; T_amb= 25 °C.

December 1990

31

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Fig.29 Typical frequency lock range (2f_L) versus the product R1C1: V_VCOINrange = 0.9 to (V_CC− 0.9) V;

R2 = ∞; VCO gain:

2f_L

K_V

=

2 π (r/s/V).

------------------------------------

V_VCOINrange

December 1990

32

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

on the application, the phase error can be defined as the

limit, a phase error of greater magnitude would be

considered out-of-lock. An example of an in-lock detection

circuit using the “7046A” is shown in Fig.30.

APPLICATION INFORMATION

Lock-detection circuit

The built-in lock-detection circuit will only work when used

in conjunction with the phase comparator PC2. The

lock-indication is derived from the phase error between

SIG_INand COMP_IN. The PC2 has a typical phase error of

zero degrees over the entire VCO operating range.

However, to remain in-lock the circuit requires some small

adjustments. The variation is dependent on the loop

parameters and back-lash time (typically 5 ns). Depending

If the PLL is in-lock, only very small pulses will come from

the “up” or “down” connections of PC2. These pulses are

filtered out by a RC network. A Schmitt trigger produces a

steady state level, a HIGH level indicates an in-lock

condition and a pulsed output indicates an out-of-lock

condition as shown in Fig.31.

See Fig.31 for input waveform.

Fig.30 An example of an in-lock detection circuit using the “7046A”.

(a)

(b)

Fig.31 Waveforms showing the lock detection process; (a) in-lock; (b) out-of-lock.

33

December 1990

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

C_LD

t_LD

=

capacitor connected to pin 15

(includes the parasitic input capacitance of the IC, approximately 3.5 pF).

phase difference between SIG_INand COMP_IN(positive-going edges).

Fig.32 C_LDcapacitor value versus typical t_LD

.

December 1990

34

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

The maximum permitted phase error

must be defined, before t_LDcan be

defined using the following formula:

φ_max

1

t_LD

=

×

.

----------- ------

360 f _IN

Using this calculated value in Fig.32,

it is possible to define the value of

C_LD, e.g. assuming the phase error is

36° and f_IN= 2 MHz:

36°

360 2 MHz

1

t _LD

=

×

= 50 ns,

--------- -----------------

and using Fig.32, it can be seen that

C_LDis 26 pF.

Fig.33 Steady state signal for lock indication.

With the addition of one retriggerable

monostable (e.g. “123”, “423” or

“4538”) a steady state LOW and

HIGH indication can be obtained, as

shown in Fig.33.

December 1990

35

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

The characteristics equation is:

PLL design example

1 + H (s) × G (s) = 0.

The frequency synthesizer, used in the design example

shown in Fig.34, has the following parameters:

This results in:

Output frequency: 2 MHz to 3 MHz

frequency steps : 100 kHz

1 + K_p× K_v× K_n× τ₂

K _p× K _v× K _n

s²+

s +

= 0.

-------------------------------

-----------------------------------------------------

(τ₁+ τ₂)

(τ ₁+ τ ₂)

settling time

overshoot

: 1 ms

: < 20%

The natural frequency ω_nis defined as follows:

˙

The open-loop gain is H (s) x G (s) = K_p× K_f× K_o× K_n.

K_p× K_v× K_n

ω_n

=

------------------------------- .

(τ₁+ τ₂)

Where:

K_p

K_f

=

phase comparator gain

low-pass filter transfer gain

K_v/s VCO gain

and the damping value ζ is defined as follows:

1 + K_p× K_v× K_n× τ₂

1

ζ =

×

.

---------- -----------------------------------------------------

K_o

K_n

2 ω _nτ₁+ τ₂

1/n divider ratio

The overshoot and settling time percentages are now used

to determine ω_n. From Fig.35 it can be seen that the

damping ratio ζ = 0.8 will produce an overshoot of less

than 20% and settle to within 5% at ω_nt = 4.5. The required

settling time is 1 ms. This results in:

The programmable counter ratio K_ncan be found as

follows:

f_out

2 MHz

---------------------

100 kHz

N_min.

=

= 20

----------

f_step

5

--

t

5

ω _n

=

= 5 × 10³r/s.

--------------

0.001

f_out

3 MHz

---------------------

100 kHz

N_max.

=

= 30

----------

f_step

Rewriting the equation for natural frequency results in:

K_p× K_v× K_n

The VCO is set by the values of R1, R2 and C1,

R2 = 10 kΩ (adjustable). The values can be determined

using the information in the section “DESIGN

CONSIDERATIONS”.

With f_o= 2.5 MHz and f_L= 500 kHz this gives the following

values (V_CC= 5.0 V):

(τ₁+ τ₂) =

.

-------------------------------

2

ω_n

The maximum overshoot occurs at N_max.:

0.4 × 2 × 10⁶

(τ ₁+ τ ₂) =

= 0.0011 s.

---------------------------------

5000²× 30

R1 = 10 kΩ

R2 = 10 kΩ

C1 = 500 pF

When C2 = 470 nF, then

(τ₁+ τ₂) × 2 × ω_n× ζ – 1

The VCO gain is:

R4 =

= 790 Ω.

----------------------------------------------------------------

K_p× K_v× K_n

2f_L× 2 × π

× 2 π ≈ 2 × 10⁶r/s/v

1 MHz

-----------------

3.2

K_V

=

= =

----------------------------------------------

0.9 – (V_CC– 0.9)

R3 is calculated using the damping ratio equation:

τ₁

The gain of the phase comparator is:

V_CC

R3 =

– R4 = 2 kΩ.

-------

C2

K_p

=

= 0.4 V/r.

------------

4 × π

The transfer gain of the filter is given by:

1 + τ₂s

K_f=

------------------------------------

1 + (τ₁+ τ₂) s

Where:

τ ₁= R3C2 and τ₂= R4C2.

December 1990

36

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Fig.34 Frequency synthesizer.

Note

For an extensive description and application example please refer to application note ordering number

9398 649 90011.

Also available a computer design program for PLL’s ordering number 9398 961 10061.

MGA959

1.6

−0.6

−0.4

−0.2

0

= 0.3

0.5

0.707

1.0

ζ

1.4

1.2

(t)

∆ Φ

e

∆ ω

e

∆ ω /ω

∆ Φ /ω

n

e

n

e

= 5.0

ζ

1.0

0.8

= 2.0

ζ

0.2

0.6

0.4

0.2

0.4

0.6

0.8

0

1.0

0

1

2

3

4

5

6

7

8

ω

t

n

Fig.35 Type 1, second order frequency step response.

Since the output frequency is proportional to the VCO control voltage, the PLL frequency response can be observed with

an oscilloscope by monitoring pin 9 of the VCO. The average frequency response, as calculated by the Laplace method,

is found experimentally by smoothing this voltage at pin 9 with a simple RC filter, whose time constant is long compared

to the phase detector sampling rate but short compared to the PLL response time.

December 1990

37

Philips Semiconductors

Product speciﬁcation

Phase-locked-loop with lock detector

74HC/HCT7046A

Fig.36 Frequency compared to the time response.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

38


型号：	74HC7046AD-T
厂家：	NXP
描述：	IC PHASE LOCKED LOOP, PDSO16, PLL or Frequency Synthesis Circuit 光电二极管
文件：	总38页 (文件大小：465K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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