74HC7266D,652 [NXP]
74HC7266 - Quad 2-input EXCLUSIVE-NOR gate SOIC 14-Pin;
| 型号： | 74HC7266D,652 |
| 厂家： | 
NXP |
| 描述： | 74HC7266 - Quad 2-input EXCLUSIVE-NOR gate SOIC 14-Pin 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总4页 (文件大小：33K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC7266
Quad 2-input EXCLUSIVE-NOR
gate
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-NOR gate
74HC7266
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC7266 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC7266 provide the EXCLUSIVE-NOR function with active push-pull output.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
11
tPHL/ tPLH
CI
propagation delay nA, nB to nY
input capacitance
CL = 15 pF; VCC = 5 V
ns
pF
pF
3.5
17
CPD
power dissipation capacitance per gate note 1
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-NOR gate
74HC7266
PIN DESCRIPTION
PIN NO.
1, 5, 8, 12
2, 6, 9, 13
3, 4, 10, 11
7
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
NAME AND FUNCTION
data inputs
data inputs
data outputs
ground (0 V)
14
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS
OUTPUT
nY
nA
nB
L
L
H
H
L
H
L
H
L
L
H
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
Fig.4 Functional diagram.
Fig.5 Logic diagram (one gate).
December 1990
3
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-NOR gate
74HC7266
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA, nB to nY
39
14
11
115
23
20
145
29
25
175
35
30
ns
ns
2.0
4.5
6.0
Fig.6
Fig.6
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
4
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