74HC9014DB-T [NXP]
暂无描述;
| 型号： | 74HC9014DB-T |
| 厂家： | 
NXP |
| 描述： | 暂无描述 驱动器 触发器 |
| 文件： | 总7页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT9014
Nine wide Schmitt trigger buffer/line
driver; inverting
December 1990
Product specification
Supersedes data of March 1988
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line
driver; inverting
74HC/HCT9014
The 74HC/HCT9014 are nine wide Schmitt trigger
FEATURES
inverting buffer/line drivers with Schmitt trigger inputs.
These inputs transform slowly changing input signals into
sharply defined jitter-free output signals.
• Schmitt trigger action on all data inputs
• Output capability: standard
• ICC category: MSI
The “9014” is identical to the “9015” but has inverting
inputs.
GENERAL DESCRIPTION
The 74HC/HCT9014 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CI
propagation delay An to Yn
input capacitance
CL = 15 pF; VCC = 5 V
12
3.5
30
13
3.5
32
ns
pF
pF
CPD
power dissipation capacitance per buffer
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver;
inverting
74HC/HCT9014
PIN DESCRIPTION
PIN NO.
SYMBOL
A0 to A8
GND
NAME AND FUNCTION
1, 2, 3, 4, 5, 6, 7, 8, 9
data inputs
10
ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12, 11
20
Y0 to Y8
VCC
data outputs
positive supply voltage
A
Y
page
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
page
1
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
11
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
A
A
A
A
A
A
A
A
Y
Y
Y
Y
Y
Y
Y
Y
11
MBA014
MBA015
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver;
inverting
74HC/HCT9014
handbook, halfpage
A
Y
n
n
MBA018
Fig.4 Functional diagram.
Fig.5 Logic diagram (one Schmitt trigger).
FUNCTION TABLE
INPUTS
An
OUTPUTS
Yn
L
H
H
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
December 1990
4
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver;
inverting
74HC/HCT9014
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Transfer characteristics are given below.
Output capability: standard
ICC category: MSI
TRANSFER CHARACTERISTICS FOR 74HC
Voltages are referred to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
VT+
VT−
VH
positive-going threshold 0.70 1.13 1.50 0.70 1.50 0.70 1.50
1.75 2.37 3.15 1.75 3.15 1.75 3.15
V
V
V
2.0 Figs 6 and 7
4.5
6.0
2.30 3.11 4.20 2.30 4.20 2.30 4.20
negative-going threshold 0.30 0.70 1.10 0.30 1.10 0.30 1.10
1.35 1.80 2.40 1.35 2.40 1.35 2.40
2.0 Figs 6 and 7
4.5
6.0
1.80 2.43 3.30 1.80 3.30 1.80 3.30
hysteresis (VT+ − VT−)
0.2
0.4
0.5
0.43 0.80 0.18 0.80 0.15 0.80
0.57 1.00 0.40 1.00 0.40 1.00
0.68 1.10 0.50 1.10 0.50 1.10
2.0 Figs 6 and 7
4.5
6.0
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
t
t
PHL/ tPLH propagation delay
An to Yn
33
12
10
105
21
18
130
26
22
160
32
27
ns
ns
2.0 Fig.8
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.8
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver;
inverting
74HC/HCT9014
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Transfer characteristics are given below.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
An
0.3
TRANSFER CHARACTERISTICS FOR 74HCT
Voltages are referred to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
VT+
VT−
VH
positive-going threshold 0.9
1.2
1.50 2.0
1.70 2.1
0.9
1.2
2.0
2.1
0.9
1.2
2.0
2.1
V
V
V
4.5 Figs 6 and 7
5.5
negative-going threshold 0.7
0.8
1.06 1.4
1.27 1.7
0.7
0.8
1.4
1.7
0.7
0.8
1.4
2.7
4.5 Figs 6 and 7
5.5
hysteresis (VT+ − VT−)
0.2
0.2
0.44 0.8
0.44 0.8
0.2
0.2
0.8
0.8
0.2
0.2
0.8
0.8
4.5 Figs 6 and 7
5.5
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An to Yn
19
32
40
48
ns
ns
4.5 Fig.8
4.5 Fig.8
t
THL/ tTLH output transition time
7
15
19
22
December 1990
6
Philips Semiconductors
Product specification
Nine wide Schmitt trigger buffer/line driver;
inverting
74HC/HCT9014
TRANSFER CHARACTERISTIC WAVEFORMS
Fig.7 Waveforms showing the definition of VT+,
VT− and VH.
Fig.6 Transfer characteristic.
AC WAVEFORMS
(1)
V
A
INPUT
n
M
t
t
PHL
PLH
(1)
V
OUTPUT
Y
M
n
t
t
MBA020
THL
TLH
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the input (An) to output (Yn) propagation delays and the output transition times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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