74HCT03D [NXP]
Quad 2-input NAND gate; 四路2输入与非门
| 型号： | 74HCT03D |
| 厂家： | 
NXP |
| 描述： | Quad 2-input NAND gate |
| 文件： | 总8页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT03
Quad 2-input NAND gate
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC/HCT03
The 74HC/HCT03 provide the 2-input NAND function.
FEATURES
The 74HC/HCT03 have open-drain N-transistor outputs,
which are not clamped by a diode connected to VCC. In
the OFF-state, i.e. when one input is LOW, the output
• Level shift capability
• Output capability: standard (open drain)
• ICC category: SSI
may be pulled to any voltage between GND and VOmax
.
This allows the device to be used as a LOW-to-HIGH or
HIGH-to-LOW level shifter. For digital operation and
OR-tied output applications, these devices must have a
pull-up resistor to establish a logic HIGH level.
GENERAL DESCRIPTION
The 74HC/HCT03 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
HC
HCT
10
tPZL/ tPLZ
CI
propagation delay
input capacitance
power dissipation capacitance per gate notes 1, 2 and 3
CL = 15 pF; RL = 1 kΩ; VCC = 5 V
8
3.5
4.0
3.5
4.0
pF
pF
CPD
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2× fi + ∑ (CL × VCC2 × fo) + ∑ (VO2/RL) × duty factor LOW, where:
fi = input frequency in MHz
fo = output frequency in MHz
VO = output voltage in V
CL = output load capacitance in pF
VCC = supply voltage in V
RL = pull-up resistor in MΩ
∑ (CL × VCC2 × fo) = sum of outputs
∑ (VO2/RL) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
3. The given value of CPD is obtained with:
CL = 0 pF and RL = ∞
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC/HCT03
PIN DESCRIPTION
PIN NO.
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
NAME AND FUNCTION
data inputs
data inputs
data outputs
ground (0 V)
14
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS
OUTPUT
nY
nA
nB
L
L
H
H
L
H
L
Z
Z
Z
L
H
Note
1. H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
Fig.4 Functional diagram.
Fig.5 Logic diagram (one gate).
December 1990
3
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC/HCT03
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
MIN.
−0.5
−0.5
MAX. UNIT CONDITIONS
VCC
VO
DC supply voltage
DC output voltage
+7
+7
20
20
25
V
V
IIK
DC input diode current
DC output diode current
DC output sink current
mA
mA
mA
for VI < −0.5 V or VI > VCC + 0.5 V
−IOK
−IO
for VO < −0.5 V
for − 0.5 V < VO
±ICC
;
DC VCC or GND current
50
mA
±IGND
Tstg
storage temperature range
−65
+150 °C
Ptot
power dissipation per package
for temperature range; −40 to +125 °C
74HC/HCT
plastic DIL
750
500
mW
mW
above +70 °C: derate linearly with 12 mW/K
above +70 °C: derate linearly with 8 mW/K
plastic mini-pack (SO)
December 1990
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC/HCT03
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that the VOH values are
not valid for open drain. They are replaced by IOZ as given below.
Output capability: standard (open drain), excepting VOH
ICC category: SSI
Voltages are referenced to GND (ground = 0 V)
T
amb (°C)
TEST CONDITIONS
VI OTHER
74HC
SYMBOL PARAMETER
UNIT VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
(1)
IOZ
HIGH level output
leakage current
2.0
to
VO = VO(max)
VIL or GND
0.5 5.0 10.0
µA
6.0
Note
1. The maximum operating output voltage (VO(max)) is 6.0 V.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tPZL
tPLZ
/
propagation delay
nA, nB to nY
28
10
8
95
19
16
120
24
20
145
29
25
2.0
4.5
6.0
Fig.6
Fig.6
ns
ns
tTHL
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC/HCT03
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”, except that the VOH values are
not valid for open drain. They are replaced by IOZ as given below.
Output capability: standard (open drain), excepting VOH
ICC category: SSI
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85
−40 to +125
VI
OTHER
min. typ. max. min. max. min. max.
4.5
to
5.5
(1)
HIGH level output
leakage current
VO = VO(max)
or GND
IOZ
0.5
5.0
10.0 µA
VIL
Note
1. The maximum operating output voltage (VO(max)) is 6.0 V.
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nA, nB
1.0
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
T
amb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PZL/ tPLZ propagation delay
nA, nB, to nY
12
7
24
15
30
19
36
22
ns
ns
4.5
4.5
Fig.6
Fig.6
tTHL
output transition time
December 1990
6
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC/HCT03
AC WAVEFORMS
HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
TEST CIRCUIT AND WAVEFORMS
Fig.8 Input pulse definitions.
Fig.7 Test circuit (open drain)
Definitions for Figs. 7, 8:
CL = load capacitance including jig and probe
capacitance
tr; tf
fmax
;
FAMILY AMPLITUDE
VM
(see AC CHARACTERISTICS for values).
PULSE OTHER
WIDTH
RT = termination resistance should be equal to the
output impedance ZO of the pulse generator.
74HC
VCC
50%
< 2 ns
< 2 ns
6 ns
6 ns
tr
= tf = 6 ns; when measuring fmax, there is no
constraint on tr, tf with 50% duty factor.
74HCT 3.0 V
1.3 V
December 1990
7
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC/HCT03
APPLICATION INFORMATION
(1) RON(max) = 0.26 V / 4 mA = 65 Ω (at 25 °C)
(b)
(a)
Fig.9 Pull-up configuration.
(1) VCC (R) = 2.0 V; VIL = 0.5 V.
(2) VCC (R) = 5.0 V; VIL = 0.8 V.
(3) VCC (R) = 4.5 V; VIL = 1.35 V.
(4) VCC (R) = 6.0 V; VIL = 1.8 V.
Fig.10 Minimum resistive load as a function of the pull-up voltage.
Notes to Figs 9 and 10
If VP − VCC (R) > 0.5 V a positive current will flow into the receiver (as described in the “USER GUIDE”; input/output
protection), this will not affect the receiver provided the current does not exceed 20 mA. At VCC < 4.5 V, RON (max) is not
guaranteed; RON(max) can be estimated using Figs 33 and 34 in the “USER GUIDE”.
Note to Application information
All values given are typical unless otherwise specified.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
8
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