74HCT08DB,118 [NXP]
74HC(T)08 - Quad 2-input AND gate SSOP1 14-Pin;
| 型号： | 74HCT08DB,118 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)08 - Quad 2-input AND gate SSOP1 14-Pin |
| 文件： | 总20页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74HC08; 74HCT08
Quad 2-input AND gate
Product specification
2003 Jul 25
Supersedes data of 1990 Dec 01
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
FEATURES
DESCRIPTION
• Complies with JEDEC standard no. 8-1A
The 74HC/HCT08 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/HCT08 provide the 2-input
AND function.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
74HC08
74HCT08
11
tPHL/tPLH propagation delay nA, nB to nY
CL = 15 pF; VCC = 5 V
7
ns
pF
pF
CI
input capacitance
power dissipation capacitance per gate notes 1 and 2
3.5
10
3.5
20
CPD
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. For 74HC08: the condition is VI = GND to VCC
.
For 74HCT08: the condition is VI = GND to VCC − 1.5 V.
FUNCTION TABLE
INPUT
OUTPUT
nA
L
nB
nY
L
L
H
L
L
L
H
H
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
2003 Jul 25
2
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74HC08N
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
14
14
14
14
14
14
14
14
14
14
DIP14
DIP14
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
SOT27-1
SOT27-1
74HCT08N
74HC08D
SO14
SOT108-1
SOT108-1
SOT337-1
SOT337-1
SOT402-1
SOT402-1
SOT762-1
SOT762-1
74HCT08D
74HC08DB
74HCT08DB
74HC08PW
74HCT08PW
74HC08BQ
74HCT08BQ
SO14
SSOP14
SSOP14
TSSOP14
TSSOP14
DHVQFN14
DHVQFN14
PINNING
PIN
SYMBOL
1A
DESCRIPTION
1
2
data input
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
VCC
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
3
4
5
6
7
8
9
10
11
12
13
14
2003 Jul 25
3
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
V
1A
1
handbook, halfpage
CC
14
handbook, halfpage
1A
1B
1
2
3
4
5
6
7
V
CC
14
13
12
11
10
9
1B
2
3
13 4B
12 4A
4B
4A
4Y
3B
3A
3Y
1Y
1Y
(1)
2A
2B
2Y
4
5
6
11 4Y
10 3B
GND
2A
08
2B
2Y
9
3A
8
GND
7
8
MNA220
GND 3Y
Top view
MCE183
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration DIP14, SO14 and
(T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
1
2
handbook, halfpage
&
&
&
&
3
6
handbook, halfpage
1
2
1A
1B
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
9
3A
3B
9
10
8
10
12
13
4A
4B
4Y 11
12
13
MNA222
11
MNA223
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
2003 Jul 25
4
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
handbook, halfpage
A
A
handbook, halfpage
Y
Y
B
B
MNB037
MNA221
Fig.5 HC logic diagram (one gate).
Fig.6 HCT logic diagram (one gate).
RECOMMENDED OPERATING CONDITIONS
74HC08
74HCT08
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN.
2.0
TYP. MAX. MIN. TYP. MAX.
VCC
VI
supply voltage
input voltage
output voltage
5.0
−
6.0
4.5
0
5.0
−
5.5
V
0
VCC
VCC
VCC
VCC
V
V
VO
0
−
0
−
Tamb
ambient
temperature
see DC and AC
characteristics per device
−40
+25
+125 −40
+25
+125 °C
tr, tf
input rise and fall VCC = 2.0 V
−
−
−
−
1000
500
−
−
−
−
−
ns
ns
ns
times
VCC = 4.5 V
6.0
−
6.0
−
500
−
VCC = 6.0 V
400
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+7.0
UNIT
VCC
IIK
V
input diode current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
−
±20
±20
±25
±50
+150
mA
mA
mA
mA
°C
IOK
IO
output diode current
−
output source or sink current
−
I
CC, IGND VCC or GND current
−
Tstg
Ptot
storage temperature
power dissipation
DIP14 package
−65
T
amb = −40 to +125 °C; note 1
amb = −40 to +125 °C; note 2
−
−
750
500
mW
mW
other packages
T
Notes
1. For DIP14 packages: above 70 °C derate linearly with 12 mW/K.
2. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 Jul 25
5
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
DC CHARACTERISTICS
Family 74HC08
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = 25 °C
VIH
HIGH-level input voltage
LOW-level input voltage
2.0
1.5
1.2
−
−
−
V
4.5
6.0
2.0
4.5
6.0
3.15
4.2
−
2.4
3.2
0.8
2.1
2.8
V
V
V
V
V
VIL
0.5
−
1.35
1.8
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA
IO = −20 µA
IO = −4.0 mA
IO = −20 µA
IO = −5.2 mA
2.0
4.5
4.5
6.0
6.0
1.9
2.0
−
−
−
−
−
V
V
V
V
V
4.4
4.5
3.98
5.9
4.32
6.0
5.48
5.81
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA
2.0
4.5
4.5
6.0
6.0
6.0
6.0
−
−
−
−
−
−
−
0
0.1
V
IO = 20 µA
0
0.1
V
IO = 4.0 mA
IO = 20 µA
0.15
0
0.26
0.1
V
V
IO = 5.2 mA
VI = VCC or GND
0.16
0.1
−
0.26
±.0.1
±.0.5
V
ILI
input leakage current
µA
µA
IOZ
3-state output OFF current VI = VIH or VIL;
VO = VCC or GND
ICC
quiescent supply current
VI = VCC or GND; IO = 0 6.0
−
−
2
µA
2003 Jul 25
6
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
TEST CONDITIONS
OTHER
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
−
−
−
−
−
−
−
−
−
V
3.15
4.2
−
V
V
V
V
V
VIL
LOW-level input voltage
0.5
−
1.35
1.8
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA
IO = −20 µA
IO = −4.0 mA
IO = −20 µA
IO = −5.2 mA
2.0
4.5
4.5
6.0
6.0
1.9
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
4.4
3.84
5.9
5.34
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA
2.0
4.5
4.5
6.0
6.0
6.0
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
IO = 20 µA
0.1
V
IO = 4.0 mA
IO = 20 µA
0.33
0.1
V
V
IO = 5.2 mA
VI = VCC or GND
0.33
±1.0
±.5.0
V
ILI
input leakage current
µA
µA
IOZ
3-state output OFF current VI = VIH or VIL;
VO = VCC or GND
ICC
quiescent supply current
VI = VCC or GND; IO = 0 6.0
−
−
20
µA
2003 Jul 25
7
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
TEST CONDITIONS
OTHER
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH HIGH-level input voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
−
−
−
−
−
−
−
−
−
V
3.15
4.2
−
V
V
V
V
V
VIL
LOW-level input voltage
0.5
−
1.35
1.8
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA
IO = −20 µA
IO = −4.0 mA
IO = −20 µA
IO = −5.2 mA
2.0
4.5
4.5
6.0
6.0
1.9
4.4
3.7
5.9
5.2
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 µA
2.0
4.5
4.5
6.0
6.0
6.0
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
IO = 20 µA
0.1
V
IO = 4.0 mA
IO = 20 µA
0.4
V
0.1
V
IO = 5.2 mA
VI = VCC or GND
0.4
V
ILI
input leakage current
±1.0
±10.0
µA
µA
IOZ
3-state output OFF current VI = VIH or VIL;
VO = VCC or GND
ICC
quiescent supply current
VI = VCC or GND; IO = 0 6.0
−
−
40
µA
2003 Jul 25
8
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
Family 74HCT08
At recommended operating conditions; voltages are referenced to GND (ground = 0).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
OTHER
VCC (V)
Tamb = 25 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
4.5 to 5.5 2.0
1.6
−
V
V
4.5 to 5.5
−
1.2
0.8
VOH
VI = VIH or VIL
IO = −20 µA
4.5
4.5
4.4
4.5
−
−
V
V
IO = −4.0 mA
VI = VIH or VIL
IO = 20 µA
3.84
4.32
VOL
LOW-level output voltage
4.5
4.5
5.5
5.5
−
−
−
−
0
0.1
V
IO = 4.0 mA
0.15
−
0.26
±0.1
±0.5
V
ILI
input leakage current
VI = VCC or GND
µA
µA
IOZ
3-state output OFF current
VI = VIH or VIL;
VO = VCC or GND;
IO = 0
−
ICC
quiescent supply current
VI = VCC or GND; 5.5
IO = 0
−
−
−
2
µA
µA
∆ICC
additional supply current per input VI = VCC − 2.1 V;
4.5 to 5.5
60
216
IO = 0
Tamb = −40 to +85 °C
VIH
VIL
HIGH-level input voltage
4.5 to 5.5 2.0
−
−
−
V
V
LOW-level input voltage
HIGH-level output voltage
4.5 to 5.5
−
0.8
VOH
VI = VIH or VIL
IO = −20 µA
4.5
4.5
4.4
−
−
−
−
V
V
IO = −4.0 mA
VI = VIH or VIL
IO = 20 µA
3.84
VOL
LOW-level output voltage
4.5
4.5
5.5
5.5
−
−
−
−
−
−
−
−
0.1
V
IO = 4.0 mA
0.33
±1.0
±5.0
V
ILI
input leakage current
VI = VCC or GND
µA
µA
IOZ
3-state output OFF current
VI = VIH or VIL;
VO = VCC or GND;
IO = 0
ICC
quiescent supply current
VI = VCC or GND; 5.5
IO = 0
−
−
−
−
20
µA
µA
∆ICC
additional supply current per input VI = VCC − 2.1 V;
4.5 to 5.5
270
IO = 0
2003 Jul 25
9
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
OTHER
VCC (V)
Tamb = −40 to +125 °C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
4.5 to 5.5 2.0
−
−
−
V
V
4.5 to 5.5
−
0.8
VOH
VI = VIH or VIL
IO = −20 µA
4.5
4.5
4.4
3.7
−
−
−
−
V
V
IO = −4.0 mA
VI = VIH or VIL
IO = 20 µA
VOL
LOW-level output voltage
4.5
4.5
5.5
5.5
−
−
−
−
−
−
−
−
0.1
V
IO = 4.0 mA
0.4
V
ILI
input leakage current
VI = VCC or GND
±1.0
±10
µA
µA
IOZ
3-state output OFF current
VI = VIH or VIL;
VO = VCC or GND;
IO = 0
ICC
quiescent supply current
VI = VCC or GND; 5.5
IO = 0
−
−
−
−
40
µA
µA
∆ICC
additional supply current per input VI = VCC − 2.1 V;
4.5 to 5.5
294
IO = 0
2003 Jul 25
10
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
AC CHARACTERISTICS
Family 74HC08
GND = 0 V; tf = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = 25 °C
tPHL/tPLH
propagation delay nA,
nB to nY
see Figs 7 and 8 2.0
−
−
−
−
−
−
25
90
18
15
75
15
13
ns
4.5
9
ns
ns
ns
ns
ns
6.0
7
tTHL/tTLH
output transition time
see Figs 7 and 8 2.0
19
7
4.5
6.0
6
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay nA,
nB to nY
see Figs 7 and 8 2.0
−
−
−
−
−
−
−
−
−
−
−
−
115
23
20
95
19
16
ns
ns
ns
ns
ns
ns
4.5
6.0
tTHL/tTLH
output transition time
see Figs 7 and 8 2.0
4.5
6.0
Tamb = −40 to +125 °C
tPHL/tPLH
propagation delay nA,
nB to nY
see Figs 7 and 8 2.0
−
−
−
−
−
−
−
−
−
−
−
−
135
27
ns
ns
ns
ns
ns
ns
4.5
6.0
23
tTHL/tTLH
output transition time
see Figs 7 and 8 2.0
110
22
4.5
6.0
19
2003 Jul 25
11
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
Family 74HCT08
GND = 0 V; tf = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = 25 °C
tPHL/tPLH
propagation delay nA,
nB to nY
see Figs 7 and 8 4.5
see Figs 7 and 8 4.5
−
−
14
24
15
ns
tTHL/tTLH
output transition time
7
ns
Tamb = −40 to +85 °C
tPHL/tPLH propagation delay nA,
see Figs 7 and 8 4.5
see Figs 7 and 8 4.5
−
−
−
−
30
19
ns
ns
nB to nY
tTHL/tTLH
output transition time
Tamb = −40 to +125 °C
tPHL/tPLH propagation delay nA,
see Figs 7 and 8 4.5
see Figs 7 and 8 4.5
−
−
−
−
36
22
ns
ns
nB to nY
tTHL/tTLH
output transition time
AC WAVEFORMS
V
handbook, halfpage
I
V
V
M
nA, nB input
M
GND
t
t
PHL
PLH
V
OH
90%
V
V
nY output
M
M
10%
V
OL
t
t
TLH
MNA726
THL
74HC08: VM = 50%; VI = GND to VCC
.
74HCT08: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
2003 Jul 25
12
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
V
handbook, halfpage
CC
V
V
I
O
PULSE
GENERATOR
D.U.T
R
C
50 pF
T
L
MGK565
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
2003 Jul 25
13
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
PACKAGE OUTLINES
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
2003 Jul 25
14
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
2003 Jul 25
15
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
2003 Jul 25
16
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
2003 Jul 25
17
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
2003 Jul 25
18
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jul 25
19
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/03/pp20
Date of release: 2003 Jul 25
Document order number: 9397 750 11265
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