74HCT107D [NXP]

Dual JK flip-flop with reset; negative-edge trigger; 双JK FL IP- FL运带复位;负边沿触发


型号：	74HCT107D
厂家：	NXP
描述：	Dual JK flip-flop with reset; negative-edge trigger 双JK FL IP- FL运带复位;负边沿触发触发器锁存器逻辑集成电路光电二极管
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中文：	中文翻译
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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT107

Dual JK flip-flop with reset;

negative-edge trigger

December 1990

Product speciﬁcation

File under Integrated Circuits, IC06

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

74HC/HCT107

The 74HC/HCT107 are dual negative-edge triggered

JK-type flip-flops featuring individual J, K, clock (nCP) and

reset (nR) inputs; also complementary Q and Q outputs.

FEATURES

• Output capability: standard

• I_CCcategory: flip-flops

The J and K inputs must be stable one set-up time prior to

the HIGH-to-LOW clock transition for predictable

operation.

GENERAL DESCRIPTION

The 74HC/HCT107 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The reset (nR) is an asynchronous active LOW input.

When LOW, it overrides the clock and data inputs, forcing

the Q output LOW and the Q output HIGH.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

t_PHL/ t_PLH

PARAMETER

propagation delay

CONDITIONS

UNIT

HCT

nCP to nQ

3.5

C_L= 15 pF;

V_CC= 5 V

nCP to nQ

nR to nQ, nQ

f_max

C_I

maximum clock frequency

input capacitance

MHz

3.5

power dissipation

capacitance per ﬂip-ﬂop

C_PD

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V.

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

74HC/HCT107

PIN DESCRIPTION

PIN NO.

1, 8, 4, 11

SYMBOL

1J, 2J, 1K, 2K

NAME AND FUNCTION

synchronous inputs; ﬂip-ﬂops 1 and 2

2, 6

3, 5

1Q, 2Q

GND

complement ﬂip-ﬂop outputs

true ﬂip-ﬂop outputs

ground (0 V)

12, 9

13, 10

1CP, 2CP

1R, 2R

V_CC

clock input (HIGH-to-LOW, edge-triggered)

asynchronous reset inputs (active LOW)

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

74HC/HCT107

Fig.4 Functional diagram.

Fig.5 Logic diagram (one flip-flop).

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

nCP

asynchronous reset

toggle

↓

load “0” (reset)

load “1” (set)

hold “no change”

Note

1. H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition

L = LOW voltage level

I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition

q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP

transition

X = don’t care

↓ = HIGH-to-LOW CP transition

December 1990

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

74HC/HCT107

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: flip-flops

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HC

SYMBOL PARAMETER

UNIT

WAVEFORMS

V_CC

(V)

+25

−40 to +85 −40 to +125

min. typ. max. min. max. min. max.

160

200

240

2.0

4.5

6.0

propagation delay

nCP to nQ

t_PHL/ t_PLH

Fig.6

Fig.7

Fig.6

Fig.7

Fig.6

160

200

240

2.0

4.5

6.0

propagation delay

nCP to nQ

_PHL/ t_PLH

155

195

235

2.0

4.5

6.0

propagation delay

nR to nQ, nQ

_PHL/ t_PLH

110

2.0

4.5

6.0

_THL/ t_TLHoutput transition time

100

120

2.0

4.5

6.0

clock pulse width

HIGH or LOW

t_W

100

120

2.0

4.5

6.0

reset pulse width

LOW

t_W

2.0

4.5

6.0

removal time

nR to nCP

t_rem

t_su

t_h

100 22

125

150

2.0

4.5

6.0

set-up time

nJ, nK to nCP

−6

−2

2.0

4.5

6.0

hold time

nJ, nK to nCP

6.0

4.8

4.0

2.0

4.5

6.0

maximum clock pulse

frequency

f_max

MHz

December 1990

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

74HC/HCT107

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

I_CCcategory: flip-flops

Note to HCT types

The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.

To determine ∆I_CCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT

UNIT LOAD COEFFICIENT

nCP, nJ

0.60

0.65

1.00

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t_f= t_f= 6 ns; C_L= 50 pF

T_amb(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V_CC

+25

−40 to +85 −40 to +125

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

propagation delay

t_PHL/ t_PLH

4.5

Fig.6

nCP to nQ

propagation delay

nCP to nQ

_PHL/ t_PLH

propagation delay

nR to nQ, nQ

4.5

Fig.7

Fig.6

t_THL/ t_TLHoutput transition time

clock pulse width

HIGH or LOW

t_W

reset pulse width

LOW

t_W

4.5

Fig.7

Fig.6

removal time

nR to nCP

t_rem

set-up time

t_su

nJ, nK to nCP

hold time

nJ, nK to nCP

t_h

−2

maximum clock pulse

frequency

f_max

MHz

December 1990

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with reset; negative-edge trigger

74HC/HCT107

AC WAVEFORMS

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J

and K to nCP set-up and hold times, the output transition times and the maximum clock pulse frequency.

(1) HC : V_M= 50%; V_I= GND to V_CC

HCT: V_M= 1.3 V; V_I= GND to 3 V.

Fig.7 Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays, the reset pulse width and

the nR to nCP removal time.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

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