74HCT109D-Q100 [NXP]
J-Kbar Flip-Flop;型号: | 74HCT109D-Q100 |
厂家: | NXP |
描述: | J-Kbar Flip-Flop 光电二极管 逻辑集成电路 触发器 |
文件: | 总17页 (文件大小:174K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC109-Q100; 74HCT109-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
Rev. 1 — 28 September 2016
Product data sheet
1. General description
The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop
featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD)
inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active
LOW inputs and operate independently of the clock input. The nJ and nK inputs control
the state changes of the flip-flops as described in the mode select function table. The nJ
and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a D-type flip-flop by
connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use
of current limiting resistors to interface inputs to voltages in excess of VCC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC109-Q100: CMOS level
For 74HCT109-Q100: TTL level
J and K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Specified in compliance with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name Description
40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Version
74HC109D-Q100
74HCT109D-Q100
4. Functional diagram
ꢀ
ꢁꢁ
ꢁ6' ꢂ6'
6'
ꢀ
ꢂ
ꢁꢁ
ꢁꢅ
6
6
ꢁ4
ꢂ4
ꢃ
ꢁꢄ
ꢂ
ꢁꢅ
ꢅ
ꢁꢂ
ꢈ
ꢁ-
ꢂ-
ꢁ&3
ꢂ&3
4
-
ꢁ-
ꢁ-
ꢃ
ꢆ
ꢁꢄ
ꢇ
&3
ꢅ
ꢈ
ꢁ
ꢁꢂ
ꢁꢈ
ꢁꢀ
&ꢁ
&ꢁ
))
ꢁ4
ꢂ4
ꢆ
ꢇ
ꢁ.
4
.
ꢁ.
5
ꢁ.
5
ꢁꢈ
ꢂ.
5'
ꢁ5' ꢂ5'
ꢁꢀ
ꢀDꢁ
ꢀEꢁ
ꢁ
PQDꢀꢁꢀ
PQDꢀꢁꢂ
Fig 1. Logic symbol
Fig 2. IEC logic symbol
4
4
&
&
&
&
&
&
&
&
.
-
6
5
&
&
&3
DDDꢃꢄꢅꢆꢄꢂꢂ
Fig 3. Logic diagram (one flip-flop)
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
2 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
5. Pinning information
5.1 Pinning
ꢂꢃ+&ꢄꢅꢆꢇ4ꢄꢅꢅ
ꢂꢃ+&7ꢄꢅꢆꢇ4ꢄꢅꢅ
ꢁ
ꢂ
ꢈ
ꢅ
ꢀ
ꢃ
ꢆ
ꢉ
ꢁꢃ
ꢁꢀ
ꢁꢅ
ꢁꢈ
ꢁꢂ
ꢁꢁ
ꢁꢄ
ꢇ
ꢁ5'
ꢁ-
9
&&
ꢂ5'
ꢂ-
ꢁ.
ꢁ&3
ꢁ6'
ꢁ4
ꢂ.
ꢂ&3
ꢂ6'
ꢂ4
ꢁ4
*1'
ꢂ4
DDDꢃꢄꢅꢆꢁꢇꢁ
Fig 4. Pin configuration for SO16
5.2 Pin description
Table 2.
Symbol
1RD, 2RD
1J, 2J
Pin description
Pin
Description
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
asynchronous reset input (active LOW)
synchronous input
1K, 2K
synchronous input
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
clock input (LOW-to-HIGH; edge-triggered)
asynchronous set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
VCC
16
supply voltage
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
3 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
6. Functional description
Table 3.
Function selection[1]
Operating modes
Input
nSD
L
Output
nRD
H
nCP
X
nJ
X
X
X
h
l
nK
X
X
X
l
nQ
H
L
nQ
L
Asynchronous set
Asynchronous reset
Undetermined
Toggle
H
L
X
H
H
q
L
L
X
H
q
H
H
Load 0 (reset)
Load 1 (set)
H
H
l
L
H
L
H
H
h
l
h
H
q
Hold no change
H
H
h
q
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition
X = don’t care
= LOW-to-HIGH CP transition
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
-
20
20
25
+50
-
mA
mA
mA
mA
mA
C
IOK
-
IO
-
-
ICC
supply current
IGND
Tstg
Ptot
ground current
50
65
-
storage temperature
total power dissipation
+150
500
[1]
SO16 package
mW
[1] For SO16 package: above 70 C, the value of Ptot derates linearly with 8 mW/K.
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
4 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC109-Q100
74HCT109-Q100
Unit
Min
Typ
Max
Min
Typ
Max
VCC
VI
supply voltage
2.0
5.0
6.0
VCC
VCC
+125
625
139
83
4.5
5.0
5.5
VCC
VCC
V
V
V
input voltage
0
-
0
-
VO
output voltage
0
-
+25
-
0
-
+25
-
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
40
+125 C
-
-
-
-
-
-
-
ns/V
1.67
-
1.67
-
139 ns/V
VCC = 6.0 V
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC109-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
4.0
-
40
-
80
A
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
5 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT109-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 5.2 mA; VCC = 5.5 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
0.15 0.26
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
4.0
-
40
-
80
A
additional
supply current VI = VCC 2.1 V;
other inputs at VCC or GND;
per input pin;
VCC = 4.5 V to 5.5 V
nJ, nK, nSD, nRD and
nCP inputs
-
-
35
126
-
-
-
157.5
-
-
-
171.5 A
pF
CI
input
3.5
-
capacitance
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
6 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
74HC109-Q100
[2]
tpd
propagation
delay
nCP to nQ, nQ;
see Figure 5
VCC = 2.0 V
-
-
-
-
50
18
15
14
175
35
-
-
-
-
-
220
44
-
-
-
-
-
265
53
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
30
37
45
tPLH
tPHL
tPHL
tPLH
tt
LOW to HIGH nSD to nQ, see Figure 6
propagation
delay
VCC = 2.0 V
-
-
-
-
30
11
12
9
120
24
-
-
-
-
-
150
30
-
-
-
-
-
180
36
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
20
26
31
HIGH to LOW nSD to nQ; see Figure 6
propagation
delay
VCC = 2.0 V
-
-
-
-
41
15
12
12
155
31
-
-
-
-
-
195
39
-
-
-
-
-
235
47
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
33
40
HIGH to LOW nRD to nQ; see Figure 6
propagation
delay
VCC = 2.0 V
-
-
-
-
41
15
12
12
185
37
-
-
-
-
-
230
46
-
-
-
-
-
280
56
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
31
39
48
LOW to HIGH nRD to nQ; see Figure 6
propagation
delay
VCC = 2.0 V
-
-
-
-
39
14
12
11
170
34
-
-
-
-
-
215
43
-
-
-
-
-
255
51
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
29
37
43
[3]
transition
time
nQ, nQ; see Figure 5
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
7 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
tW
pulse width
nCP HIGH or LOW;
see Figure 5
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
19
7
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
6
17
20
nSD, nRD HIGH or LOW;
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
4
17
20
trec
recovery time nSD, nRD to nCP;
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
70
14
12
19
7
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
6
18
tsu
set-up time
hold time
nJ and nK to nCP;
see Figure 5
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
70
14
12
17
6
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
5
18
th
nJ and nK to nCP;
see Figure 5
VCC = 2.0 V
VCC = 4.5 V
5
5
5
0
0
0
-
-
-
5
5
5
-
-
-
5
5
5
-
-
-
ns
ns
ns
VCC = 6.0 V
fmax
maximum
frequency
nCP; see Figure 5
VCC = 2.0 V
6
30
-
22
68
75
81
20
-
-
-
-
-
5
24
-
-
-
-
-
-
4
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
35
-
28
-
24
-
[4]
CPD
power
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
dissipation
capacitance
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
8 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
74HCT109-Q100
[2]
tpd
propagation
delay
nCP to nQ, nQ;
see Figure 5
VCC = 4.5 V
-
-
20
17
35
-
-
-
44
-
-
53
-
ns
ns
VCC = 5 V; CL = 15 pF
tPLH
tPHL
tPHL
tPLH
LOW to HIGH nSD to nQ, see Figure 6
propagation
delay
VCC = 4.5 V
-
-
13
14
26
-
-
-
33
-
-
-
39
-
ns
ns
VCC = 5 V; CL = 15 pF
HIGH to LOW nSD to nQ; see Figure 6
propagation
delay
VCC = 4.5 V
-
-
19
14
35
-
-
-
44
-
-
-
53
-
ns
ns
VCC = 5 V; CL = 15 pF
HIGH to LOW nRD to nQ; see Figure 6
propagation
delay
VCC = 4.5 V
-
-
19
15
35
-
-
-
44
-
-
-
53
-
ns
ns
VCC = 5 V; CL = 15 pF
LOW to HIGH nRD to nQ; see Figure 6
propagation
delay
VCC = 4.5 V
-
-
16
15
32
-
-
-
40
-
-
-
48
-
ns
ns
VCC = 5 V; CL = 15 pF
[3]
tt
transition
time
nQ, nQ; see Figure 5
VCC = 4.5 V
-
7
9
15
-
-
19
-
-
22
-
ns
ns
ns
ns
ns
ns
tW
pulse width
nCP HIGH or LOW;
see Figure 5
VCC = 4.5 V
18
16
16
18
3
23
20
20
23
3
27
24
24
27
3
nSD, nRD HIGH or LOW;
see Figure 6
VCC = 4.5 V
8
-
-
-
trec
recovery time nSD, nRD to nCP;
see Figure 6
VCC = 4.5 V
8
-
-
-
tsu
set-up time
hold time
nJ and nK to nCP;
see Figure 5
VCC = 4.5 V
8
-
-
-
th
nJ and nK to nCP;
see Figure 5
VCC = 4.5 V
3
-
-
-
fmax
maximum
frequency
nCP; see Figure 5
VCC = 4.5 V
27
-
55
61
-
-
22
-
-
-
18
-
-
-
MHz
MHz
VCC = 5 V; CL = 15 pF
74HC_HCT109_Q100
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Product data sheet
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9 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
[4]
CPD
power
CL = 50 pF; f = 1 MHz;
-
22
-
-
-
-
-
pF
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] All typical values are measured at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL
[3] tt is the same as tTHL and tTLH
[4] PD is used to determine the dynamic power dissipation (PD in W).
.
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9
,
Q-ꢊꢋQ.ꢋLQSXW
9
0
*1'
W
W
K
K
W
VX
W
VX
ꢁꢌI
PD[
9
,
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9
0
*1'
W
:
W
W
3/+
3+/
9
2+
ꢇꢄꢋꢍ
9
0
ꢇꢄꢋꢍ
ꢁꢄꢋꢍ
ꢁꢄꢋꢍ
W
9
2/
W
7/+
7+/
W
W
3+/
3/+
9
2+
ꢇꢄꢋꢍ
ꢇꢄꢋꢍ
9
0
Q4ꢋRXWSXW
ꢁꢄꢋꢍ
ꢁꢄꢋꢍ
9
2/
W
W
7/+
7+/
DDDꢃꢄꢅꢆꢄꢂꢈ
Measurement points are given in Table 8.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 5. Clock propagation delays, output transition time, pulse width, set-up, hold times, and maximum
frequency
74HC_HCT109_Q100
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Product data sheet
Rev. 1 — 28 September 2016
10 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
9
,
9
0
Q&3ꢋLQSXW
Q6'ꢋLQSXW
Q5'ꢋLQSXW
*1'
W
UHF
9
,
9
0
*1'
W
W
:
:
9
,
9
0
*1'
W
W
3/+
3+/
9
2+
9
9
Q4ꢋRXWSXW
Q4ꢋRXWSXW
0
9
2/
9
2+
0
9
2/
W
W
3/+
3+/
DDDꢃꢄꢅꢆꢄꢉꢄ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Set and reset propagation delays, pulse widths and recovery time
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC109-Q100
74HCT109-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
74HC_HCT109_Q100
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Product data sheet
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11 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
W
:
9
,
ꢇꢄꢋꢍ
QHJDWLYHꢋ
SXOVH
9
9
9
9
0
0
0
ꢁꢄꢋꢍ
ꢇꢄꢋꢍ
*1'
W
W
U
I
W
W
I
U
9
,
SRVLWLYHꢋ
SXOVH
0
ꢁꢄꢋꢍ
*
*1'
W
:
9
&&
9
,
9
2
'87
5
7
&
/
ꢄꢄꢇDDKꢉꢂꢀꢊ
ꢊ
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 7. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
6 ns
6 ns
CL
74HC109-Q100
74HCT109-Q100
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74HC_HCT109_Q100
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Product data sheet
Rev. 1 — 28 September 2016
12 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
12. Package outline
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Fig 8. Package outline SOT109-1 (SO16)
74HC_HCT109_Q100
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Product data sheet
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13 of 17
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NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20160928 Product data sheet
Change notice
Supersedes
74HC_HCT109_Q100 v.1
-
-
74HC_HCT109_Q100
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© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
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14 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
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Draft — The document is a draft version only. The content is still under
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modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
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Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
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Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
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data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
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NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
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Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
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source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
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applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
15 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT109_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 28 September 2016
16 of 17
74HC109-Q100; 74HCT109-Q100
NXP Semiconductors
Dual JK flip-flop with set and reset; positive-edge-trigger
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 September 2016
Document identifier: 74HC_HCT109_Q100
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