74HCT11DB,112 [NXP]
74HC(T)11 - Triple 3-input AND gate SSOP1 14-Pin;
| 型号： | 74HCT11DB,112 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)11 - Triple 3-input AND gate SSOP1 14-Pin |
| 文件： | 总15页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC11; 74HCT11
Triple 3-input AND gate
Rev. 04 — 25 March 2010
Product data sheet
1. General description
The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC11; 74HCT11 provides a triple 3-input AND function.
2. Features
Input levels:
For 74HC11: CMOS level
For 74HCT11: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC11N
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HCT11N
74HC11D
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT11D
74HC11DB
74HCT11DB
74HC11PW
74HCT11PW
SSOP14
TSSOP14
plastic shrink small outline package; 14 leads; body SOT337-1
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
4. Functional diagram
1
2
&
&
&
12
6
1
2
1A
1B
1C
2A
2B
2C
3A
3B
3C
13
1Y
2Y
12
6
13
3
3
4
5
4
5
A
9
9
10
11
3Y
8
10
11
Y
8
B
C
mna794
mna793
mna792
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram for one gate
5. Pinning information
5.1 Pinning
74HC11
74 HCT11
74HC11
74HCT11
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
1C
1Y
3C
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
2A
1C
1Y
3C
3B
3A
3Y
2A
2B
2B
2C
2C
2Y
2Y
8
GND
8
GND
001aal407
001aal408
Fig 4. Pin configuration DIP14 and SO14
Fig 5. Pin configuration (T)SSOP14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A
1B, 2B, 3B
GND
Pin description
Pin
Description
data input
1, 3, 9
2, 4, 10
7
data input
ground (0 V)
data input
1C, 2C, 3C
1Y, 2Y, 3Y
VCC
13, 5, 11
12, 6, 8
14
data output
supply voltage
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
2 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
6. Functional description
Table 3.
Function selection[1]
Input
nA
L
Output
nB
X
nC
X
nY
L
X
L
X
L
X
X
L
L
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
−0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
-
±20
±20
±25
50
mA
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−50
−65
-
storage temperature
total power dissipation
DIP14 package
+150
[2]
-
-
750
500
mW
mW
SO14 and (T)SSOP14
packages
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
3 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC11
74HCT11
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
VCC
VCC
VO
output voltage
0
-
0
-
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
−40
-
−40
-
+125 °C
-
-
-
-
1.67
-
-
-
-
-
1.67
-
-
ns/V
139 ns/V
VCC = 6.0 V
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74HC11
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −20 μA; VCC = 2.0 V
IO = −20 μA; VCC = 4.5 V
IO = −20 μA; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = −4.0 mA; VCC = 4.5 V 3.98 4.32
IO = −5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
±1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
±0.1
μA
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
2.0
-
20
-
40
μA
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
4 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT11
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −20 μA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = −4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA; VCC = 4.5 V
-
-
0
-
0.1
-
-
0.1
-
-
0.1
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
±0.1
±1
±1
μA
ICC
ΔICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
2.0
-
-
20
-
-
40
μA
μA
additional
per input pin;
100
360
450
490
supply current VI = VCC − 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Min
Typ
Max
74HC11
[1]
tpd
propagation delay nA, nB to nY; see Figure 6
VCC = 2.0 V
-
-
-
-
32
12
9
100
20
-
125
25
-
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
10
17
21
26
[2]
[3]
tt
transition time
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
19
7
75
15
13
-
95
19
16
-
110
22
19
-
ns
ns
ns
pF
6
CPD
power dissipation per package; VI = GND to VCC
capacitance
18
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
5 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
−40 °C to +125 °C Unit
Max Max
(85 °C) (125 °C)
Min
Typ
Max
74HCT11
[1]
tpd
propagation delay nA, nB to nY; see Figure 6
VCC = 4.5 V
-
-
-
-
16
11
7
24
-
30
-
36
-
ns
ns
ns
pF
VCC = 5.0 V; CL = 15 pF
[2]
[3]
tt
transition time
power dissipation per package;
capacitance VI = GND to VCC − 1.5 V
VCC = 4.5 V; see Figure 6
15
-
19
-
22
-
CPD
20
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑ (CL × VCC2 × fo) = sum of outputs.
11. Waveforms
V
I
V
M
nA, nB, nC input
GND
t
t
PLH
PHL
V
OH
V
Y
V
M
nY output
V
X
V
OL
t
t
THL
TLH
001aal409
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
Table 8.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC11
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HCT11
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
6 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
90 %
GND
t
t
r
f
t
t
f
r
V
I
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
C
L
T
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 7. Load circuitry for measuring switching times
Table 9.
Type
Test data
Input
VI
Load
Test
tr, tf
CL
74HC11
VCC
3.0 V
6.0 ns
6.0 ns
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74HCT11
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
7 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
12. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 8. Package outline SOT27-1 (DIP14)
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
8 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 9. Package outline SOT108-1 (SO14)
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
9 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
Fig 10. Package outline SOT337-1 (SSOP14)
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
10 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 11. Package outline SOT402-1 (TSSOP14)
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
11 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
74HC_HCT11_4
74HC_HCT11_3
Modifications:
Release date
Data sheet status
Product data sheet
Product data sheet
Change notice
Supersedes
20100325
20100209
-
-
74HC_HCT11_3
74HC_HCT11_CNV_2
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT11_CNV_2 19970827
Product specification
-
-
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
12 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
suitable for use in medical, military, aircraft, space or life support equipment,
15.2 Definitions
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
13 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT11_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 25 March 2010
14 of 15
74HC11; 74HCT11
NXP Semiconductors
Triple 3-input AND gate
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 March 2010
Document identifier: 74HC_HCT11_4
相关型号：
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