74HCT139PW-Q100 [NXP]
IC OTHER DECODER/DRIVER, Decoder/Driver;型号: | 74HCT139PW-Q100 |
厂家: | NXP |
描述: | IC OTHER DECODER/DRIVER, Decoder/Driver 驱动 |
文件: | 总18页 (文件大小:179K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC139-Q100; 74HCT139-Q100
Dual 2-to-4 line decoder/demultiplexer
Rev. 1 — 19 June 2014
Product data sheet
1. General description
The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs
(nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an
enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be
used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes
that enable the use of current limiting resistors to interface inputs to voltages in excess of
VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC139-Q100: CMOS level
For 74HCT139-Q100: TTL level
Demultiplexing capability
2 independent 2-to-4 decoders
Multifunction capability
Suitable for memory decoding, data routing or code conversion
Complies with JEDEC standard no. 7A
Active LOW mutually exclusive outputs
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC139D-Q100
40 C to +125 C
40 C to +125 C
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74 HCT139D-Q100
74HC139DB-Q100
74HCT139DB-Q100
74HC139PW-Q100
74HCT139PW-Q100
SSOP16
TSSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
SOT403-1
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
4. Functional diagram
ꢀ<ꢁ
ꢅ
ꢃ
ꢆ
ꢇ
ꢀ$ꢁ
ꢀ$ꢀ
ꢀ<ꢀ
ꢀ<ꢂ
ꢀ<ꢄ
ꢂ
ꢄ
'(&2'(5
ꢀ
ꢀ(
ꢀ(
ꢀ<ꢁ
ꢅ
ꢀ
ꢂ
ꢄ
ꢀ$ꢁ
ꢀ$ꢀ
ꢂ$ꢁ
ꢂ$ꢀ
ꢀ<ꢀ
ꢀ<ꢂ
ꢀ<ꢄ
ꢂ<ꢁ
ꢂ<ꢀ
ꢂ<ꢂ
ꢂ<ꢄ
ꢃ
ꢂ<ꢁ
ꢂ<ꢀ
ꢂ<ꢂ
ꢂ<ꢄ
ꢀꢂ
ꢀꢀ
ꢀꢁ
ꢈ
ꢆ
ꢂ$ꢁ
ꢂ$ꢀ
ꢇ
ꢀꢅ
ꢀꢄ
'(&2'(5
ꢀꢂ
ꢀꢀ
ꢀꢁ
ꢈ
ꢀꢅ
ꢀꢄ
ꢂ(
ꢀꢃ
ꢂ(
ꢀꢃ
DDDꢀꢁꢂꢃꢂꢄꢅ
DDDꢀꢁꢂꢃꢂꢄꢆ
Fig 1. Logic symbol
Fig 2. Functional diagram
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
2 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
';
;ꢉ<
ꢂ
ꢄ
ꢅ
ꢃ
ꢆ
ꢇ
ꢂ
ꢄ
ꢅ
ꢃ
ꢆ
ꢇ
ꢁ
ꢀ
ꢁ
ꢀ
ꢂ
ꢄ
ꢀ
ꢂ
ꢁ
ꢀ
ꢂ
ꢄ
ꢁ
ꢄ
*
*
ꢀ
ꢀ
(1
';
;ꢉ<
ꢀꢅ
ꢀꢄ
ꢀꢂ
ꢀꢀ
ꢀꢁ
ꢈ
ꢀꢅ
ꢀꢄ
ꢀꢂ
ꢀꢀ
ꢀꢁ
ꢈ
ꢁ
ꢀ
ꢁ
ꢀ
ꢂ
ꢄ
ꢀ
ꢂ
ꢁ
ꢀ
ꢂ
ꢄ
ꢁ
ꢄ
ꢀꢃ
ꢀꢃ
(1
DDDꢀꢁꢂꢃꢂꢄꢇ
DDDꢀꢁꢂꢃꢂꢄꢄ
a.
b.
Fig 3. IEC Logic symbol
<ꢁ
$ꢁ
$ꢀ
(
<ꢀ
<ꢂ
<ꢄ
DDDꢀꢁꢂꢃꢂꢄꢈ
Fig 4. Logic diagram (one decoder/demultiplexer)
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
3 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
5. Pinning information
5.1 Pinning
ꢀꢁ+&ꢂꢃꢄꢅ4ꢂꢆꢆ
ꢀꢁ+&7ꢂꢃꢄꢅ4ꢂꢆꢆ
ꢀꢆ
ꢀꢃ
ꢀꢅ
ꢀꢄ
ꢀꢂ
ꢀꢀ
ꢀꢁ
ꢈ
ꢀ
ꢂ
ꢄ
ꢅ
ꢃ
ꢆ
ꢇ
ꢊ
ꢀ(
ꢀ$ꢁ
ꢀ$ꢀ
ꢀ<ꢁ
ꢀ<ꢀ
ꢀ<ꢂ
ꢀ<ꢄ
*1'
9
&&
ꢂ(
ꢂ$ꢁ
ꢂ$ꢀ
ꢂ<ꢁ
ꢂ<ꢀ
ꢂ<ꢂ
ꢂ<ꢄ
DDDꢀꢁꢂꢃꢄꢄꢃ
Fig 5. Pin configuration SO16, SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
1E, 2E
Pin description
Pin
Description
1, 15
2, 3
enable input (active LOW)
address input
1A0, 1A1
1Y0, 1Y1, 1Y2, 1Y3
GND
4, 5, 6, 7
8
output (active LOW)
ground (0 V)
2Y0, 2Y1, 2Y2, 2Y3
2A0, 2A1
12, 11, 10, 9
14, 13
16
output (active LOW)
address input
VCC
positive supply voltage
6. Functional description
Table 3.
Function table[1]
Control
Input
Output
nE
H
L
nA1
X
nA0
X
nY3
H
nY2
H
nY1
H
nY0
H
L
L
H
H
H
L
L
L
H
H
H
L
H
L
H
L
H
L
H
H
L
H
H
L
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
4 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
25
50
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
50
65
-
storage temperature
total power dissipation
SO16 package
+150
[1]
[2]
[2]
-
-
-
500
500
500
mW
mW
mW
SSOP16 package
TSSOP16 package
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[2] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC139-Q100
74HCT139-Q100
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
+25
40
+25
C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
5 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb
Unit
25 C
Min Typ
40 C to +85 C 40 C to +125 C
Max
Min
Max
Min
Max
74HC139-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1.0
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.5
-
5.0
-
10.0 A
output current VO = VCC or GND;
VCC = 6.0 V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
8.0
-
-
-
80
-
-
-
160
-
A
input
3.5
pF
capacitance
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
6 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb
Unit
25 C
Min Typ
40 C to +85 C 40 C to +125 C
Max
Min
Max
Min
Max
74HCT139-Q100
VIH
VIL
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 4.0 mA
0.15 0.26
0.33
1.0
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
1.0
A
IOZ
OFF-state
per input pin; VI = VIH or VIL;
-
-
0.5
-
5.0
-
10
A
A
output current VO = VCC or GND;
other inputs at VCC or GND;
VCC = 5.5 V; IO = 0 A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
ICC
additional
VI = VCC 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; 1An inputs
per input pin; 2An inputs
per input pin; nE inputs
-
-
-
-
70
70
252
252
486
-
-
-
-
-
315
315
607.5
-
-
-
-
-
343
343
A
A
135
3.5
661.5 A
pF
CI
input
-
capacitance
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
7 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions
Tamb
Unit
25 C
40 C to +85 C 40 C to +125 C
Min
Typ Max
Min
Max
Min
Max
74HC139-Q100
[1]
tpd
propagation nAn to nYn; see Figure 6
delay
VCC = 2.0 V
-
-
-
-
39
14
145
29
-
-
-
-
-
180
36
-
-
-
-
-
220
44
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
11
11
25
31
38
[1]
nE to nYn; see Figure 7
VCC = 2.0 V
-
-
-
-
33
12
135
27
-
-
-
-
-
170
34
-
-
-
-
-
205
41
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
10
10
23
29
35
[2]
tt
transition
time
nYn; see Figure 6 and
Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
19
7
75
15
13
-
-
-
-
-
95
19
16
-
-
-
-
-
110
22
19
-
ns
ns
ns
pF
6
[3]
CPD
power
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
42
dissipation
capacitance
74HCT139-Q100
[1]
[1]
[2]
tpd
propagation nAn to nYn; see Figure 6
delay
VCC = 4.5 V
-
-
16
34
-
-
-
43
-
-
-
51
-
ns
ns
VCC = 5.0 V; CL = 15 pF
nE to nYn; see Figure 7
VCC = 4.5 V
13
-
-
16
13
34
-
-
-
43
-
-
-
51
-
ns
ns
VCC = 5.0 V; CL = 15 pF
tt
transition
time
nYn; see Figure 6 and
Figure 7
VCC = 4.5 V
-
7
15
-
19
-
22
ns
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
8 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions
Tamb
Unit
25 C
40 C to +85 C 40 C to +125 C
Min
Typ Max
Min
Max
Min
Max
[3]
CPD
power
CL = 50 pF; f = 1 MHz;
-
44
-
-
-
-
-
pF
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] tpd is the same as tPLH and tPHL
[2] tt is the same as tTHL and tTLH
.
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9
&&
Q$Q
LQSXW
9
0
*1'
W
W
3/+
3+/
9
2+
Q<Q
LQSXW
9
0
9
2/
W
W
7+/
7/+
DDDꢀꢁꢂꢃꢂꢄꢉ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay input (nAn) to output (nYn) and transition time output (nYn)
74HC_HCT139_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
9 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
9
&&
ꢀ(ꢋꢌꢂ(
LQSXW
9
0
*1'
W
W
3+/
3/+
9
2+
Q<Q
RXWSXW
9
0
9
2/
W
W
7+/
7/+
DDDꢀꢁꢂꢃꢂꢄꢊ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay enable input (nE) to output (nYn) and transition time output (nYn)
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC139-Q100
74HCT139-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
74HC_HCT139_Q100
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
10 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
W
:
9
,
ꢈꢁꢌꢍ
QHJDWLYHꢌ
SXOVH
9
9
9
0
0
0
ꢀꢁꢌꢍ
ꢁꢌ9
W
W
U
I
W
W
U
I
9
,
ꢈꢁꢌꢍ
SRVLWLYHꢌ
SXOVH
9
0
ꢀꢁꢌꢍ
ꢁꢌ9
W
:
9
9
&&
&&
9
,
9
2
ꢌ
5
/
6ꢀ
*
RSHQ
'87
5
7
&
/
ꢁꢁꢂDDGꢊꢉꢅ
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC139-Q100
VCC
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT139-Q100 3 V
open
GND
VCC
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
11 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
12. Package outline
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74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
12 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
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Fig 10. Package outline SOT338-1 (SSOP16)
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
13 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
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Fig 11. Package outline SOT403-1 (TSSOP16)
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
14 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
ESD
HBM
MIL
MM
Machine Model
14. Revision history
Table 11. Revision history
Document ID
Release date
20140619
Data sheet status
Change notice
Supersedes
74HC_HCT139_Q100 v.1
Product data sheet
-
-
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
15 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
16 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT139_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 June 2014
17 of 18
74HC139-Q100; 74HCT139-Q100
NXP Semiconductors
Dual 2-to-4 line decoder/demultiplexer
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 June 2014
Document identifier: 74HC_HCT139_Q100
相关型号:
74HCT14
Hex Schmitt−Trigger Inverter with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS
ONSEMI
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